llvm.org GIT mirror llvm / 360ee97
[PowerPC] Generate logical vector VSX instructions These instructions are essentially the same as their Altivec counterparts, but have access to the larger VSX register file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204782 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
2 changed file(s) with 168 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
657657 let isCommutable = 1 in
658658 def XXLAND : XX3Form<60, 130,
659659 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
660 "xxland $XT, $XA, $XB", IIC_VecGeneral, []>;
660 "xxland $XT, $XA, $XB", IIC_VecGeneral,
661 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
661662 def XXLANDC : XX3Form<60, 138,
662663 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
663 "xxlandc $XT, $XA, $XB", IIC_VecGeneral, []>;
664 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
665 [(set v4i32:$XT, (and v4i32:$XA,
666 (vnot_ppc v4i32:$XB)))]>;
664667 let isCommutable = 1 in {
665668 def XXLNOR : XX3Form<60, 162,
666669 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
667 "xxlnor $XT, $XA, $XB", IIC_VecGeneral, []>;
670 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
671 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
672 v4i32:$XB)))]>;
668673 def XXLOR : XX3Form<60, 146,
669674 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
670 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
675 "xxlor $XT, $XA, $XB", IIC_VecGeneral,
676 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
671677 def XXLXOR : XX3Form<60, 154,
672678 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
673 "xxlxor $XT, $XA, $XB", IIC_VecGeneral, []>;
679 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
680 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
674681 } // isCommutable
675682
676683 // Permutation Instructions
4141 ; CHECK: blr
4242 }
4343
44 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
45 entry:
46 %v = xor <4 x i32> %a, %b
47 ret <4 x i32> %v
48
49 ; CHECK-LABEL: @test5
50 ; CHECK: xxlxor 34, 34, 35
51 ; CHECK: blr
52 }
53
54 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
55 entry:
56 %v = xor <8 x i16> %a, %b
57 ret <8 x i16> %v
58
59 ; CHECK-LABEL: @test6
60 ; CHECK: xxlxor 34, 34, 35
61 ; CHECK: blr
62 }
63
64 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
65 entry:
66 %v = xor <16 x i8> %a, %b
67 ret <16 x i8> %v
68
69 ; CHECK-LABEL: @test7
70 ; CHECK: xxlxor 34, 34, 35
71 ; CHECK: blr
72 }
73
74 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
75 entry:
76 %v = or <4 x i32> %a, %b
77 ret <4 x i32> %v
78
79 ; CHECK-LABEL: @test8
80 ; CHECK: xxlor 34, 34, 35
81 ; CHECK: blr
82 }
83
84 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
85 entry:
86 %v = or <8 x i16> %a, %b
87 ret <8 x i16> %v
88
89 ; CHECK-LABEL: @test9
90 ; CHECK: xxlor 34, 34, 35
91 ; CHECK: blr
92 }
93
94 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
95 entry:
96 %v = or <16 x i8> %a, %b
97 ret <16 x i8> %v
98
99 ; CHECK-LABEL: @test10
100 ; CHECK: xxlor 34, 34, 35
101 ; CHECK: blr
102 }
103
104 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
105 entry:
106 %v = and <4 x i32> %a, %b
107 ret <4 x i32> %v
108
109 ; CHECK-LABEL: @test11
110 ; CHECK: xxland 34, 34, 35
111 ; CHECK: blr
112 }
113
114 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
115 entry:
116 %v = and <8 x i16> %a, %b
117 ret <8 x i16> %v
118
119 ; CHECK-LABEL: @test12
120 ; CHECK: xxland 34, 34, 35
121 ; CHECK: blr
122 }
123
124 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
125 entry:
126 %v = and <16 x i8> %a, %b
127 ret <16 x i8> %v
128
129 ; CHECK-LABEL: @test13
130 ; CHECK: xxland 34, 34, 35
131 ; CHECK: blr
132 }
133
134 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
135 entry:
136 %v = or <4 x i32> %a, %b
137 %w = xor <4 x i32> %v,
138 ret <4 x i32> %w
139
140 ; CHECK-LABEL: @test14
141 ; CHECK: xxlnor 34, 34, 35
142 ; CHECK: blr
143 }
144
145 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
146 entry:
147 %v = or <8 x i16> %a, %b
148 %w = xor <8 x i16> %v,
149 ret <8 x i16> %w
150
151 ; CHECK-LABEL: @test15
152 ; CHECK: xxlnor 34, 34, 35
153 ; CHECK: blr
154 }
155
156 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
157 entry:
158 %v = or <16 x i8> %a, %b
159 %w = xor <16 x i8> %v,
160 ret <16 x i8> %w
161
162 ; CHECK-LABEL: @test16
163 ; CHECK: xxlnor 34, 34, 35
164 ; CHECK: blr
165 }
166
167 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
168 entry:
169 %w = xor <4 x i32> %b,
170 %v = and <4 x i32> %a, %w
171 ret <4 x i32> %v
172
173 ; CHECK-LABEL: @test17
174 ; CHECK: xxlandc 34, 34, 35
175 ; CHECK: blr
176 }
177
178 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
179 entry:
180 %w = xor <8 x i16> %b,
181 %v = and <8 x i16> %a, %w
182 ret <8 x i16> %v
183
184 ; CHECK-LABEL: @test18
185 ; CHECK: xxlandc 34, 34, 35
186 ; CHECK: blr
187 }
188
189 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
190 entry:
191 %w = xor <16 x i8> %b,
192 %v = and <16 x i8> %a, %w
193 ret <16 x i8> %v
194
195 ; CHECK-LABEL: @test19
196 ; CHECK: xxlandc 34, 34, 35
197 ; CHECK: blr
198 }
199