llvm.org GIT mirror llvm / 35ac462
[X86] Remove fast-isel code for handling i8 shifts. This is handled by auto generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316797 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
1 changed file(s) with 7 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
17841784 bool X86FastISel::X86SelectShift(const Instruction *I) {
17851785 unsigned CReg = 0, OpReg = 0;
17861786 const TargetRegisterClass *RC = nullptr;
1787 if (I->getType()->isIntegerTy(8)) {
1788 CReg = X86::CL;
1789 RC = &X86::GR8RegClass;
1790 switch (I->getOpcode()) {
1791 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1792 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1793 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1794 default: return false;
1795 }
1796 } else if (I->getType()->isIntegerTy(16)) {
1787 assert(!I->getType()->isIntegerTy(8) &&
1788 "i8 shifts should be handled by autogenerated table");
1789 if (I->getType()->isIntegerTy(16)) {
17971790 CReg = X86::CX;
17981791 RC = &X86::GR16RegClass;
17991792 switch (I->getOpcode()) {
18381831
18391832 // The shift instruction uses X86::CL. If we defined a super-register
18401833 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1841 if (CReg != X86::CL)
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1843 TII.get(TargetOpcode::KILL), X86::CL)
1844 .addReg(CReg, RegState::Kill);
1834 assert(CReg != X86::CL && "CReg should be a super register of CL");
1835 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1836 TII.get(TargetOpcode::KILL), X86::CL)
1837 .addReg(CReg, RegState::Kill);
18451838
18461839 unsigned ResultReg = createResultReg(RC);
18471840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)