llvm.org GIT mirror llvm / 359956d
With the fix in r162954/162955 every cvt function returns true. Thus, have the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 7 years ago
2 changed file(s) with 61 addition(s) and 85 deletion(s). Raw diff Collapse all Expand all
180180 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
181181
182182 // Asm Match Converter Methods
183 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
183 void cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
184184 const SmallVectorImpl &);
185 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
185 void cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
186186 const SmallVectorImpl &);
187 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
187 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
188188 const SmallVectorImpl &);
189 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
190190 const SmallVectorImpl &);
191 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
191 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
192192 const SmallVectorImpl &);
193 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
193 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
194194 const SmallVectorImpl &);
195 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
196196 const SmallVectorImpl &);
197 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
197 void cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
198198 const SmallVectorImpl &);
199 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
199 void cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
200200 const SmallVectorImpl &);
201 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
201 void cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
202202 const SmallVectorImpl &);
203 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
203 void cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
204204 const SmallVectorImpl &);
205 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
205 void cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
206206 const SmallVectorImpl &);
207 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
207 void cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
208208 const SmallVectorImpl &);
209 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
209 void cvtLdrdPre(MCInst &Inst, unsigned Opcode,
210210 const SmallVectorImpl &);
211 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
211 void cvtStrdPre(MCInst &Inst, unsigned Opcode,
212212 const SmallVectorImpl &);
213 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
213 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
214214 const SmallVectorImpl &);
215 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
215 void cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
216216 const SmallVectorImpl &);
217 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
217 void cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
218218 const SmallVectorImpl &);
219 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
219 void cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
220220 const SmallVectorImpl &);
221 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
221 void cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
222222 const SmallVectorImpl &);
223 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
223 void cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
224224 const SmallVectorImpl &);
225225
226226 bool validateInstruction(MCInst &Inst,
38793879 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
38803880 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
38813881 /// when they refer multiple MIOperands inside a single one.
3882 bool ARMAsmParser::
3882 void ARMAsmParser::
38833883 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
38843884 const SmallVectorImpl &Operands) {
38853885 // Rt, Rt2
38913891 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
38923892 // pred
38933893 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3894 return true;
38953894 }
38963895
38973896 /// cvtT2StrdPre - Convert parsed operands to MCInst.
38983897 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
38993898 /// when they refer multiple MIOperands inside a single one.
3900 bool ARMAsmParser::
3899 void ARMAsmParser::
39013900 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
39023901 const SmallVectorImpl &Operands) {
39033902 // Create a writeback register dummy placeholder.
39093908 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
39103909 // pred
39113910 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3912 return true;
39133911 }
39143912
39153913 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
39163914 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39173915 /// when they refer multiple MIOperands inside a single one.
3918 bool ARMAsmParser::
3916 void ARMAsmParser::
39193917 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
39203918 const SmallVectorImpl &Operands) {
39213919 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39253923
39263924 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
39273925 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3928 return true;
39293926 }
39303927
39313928 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
39323929 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39333930 /// when they refer multiple MIOperands inside a single one.
3934 bool ARMAsmParser::
3931 void ARMAsmParser::
39353932 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
39363933 const SmallVectorImpl &Operands) {
39373934 // Create a writeback register dummy placeholder.
39393936 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39403937 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
39413938 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3942 return true;
39433939 }
39443940
39453941 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
39463942 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39473943 /// when they refer multiple MIOperands inside a single one.
3948 bool ARMAsmParser::
3944 void ARMAsmParser::
39493945 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
39503946 const SmallVectorImpl &Operands) {
39513947 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39553951
39563952 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
39573953 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3958 return true;
39593954 }
39603955
39613956 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
39623957 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39633958 /// when they refer multiple MIOperands inside a single one.
3964 bool ARMAsmParser::
3959 void ARMAsmParser::
39653960 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
39663961 const SmallVectorImpl &Operands) {
39673962 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39713966
39723967 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
39733968 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3974 return true;
39753969 }
39763970
39773971
39783972 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
39793973 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39803974 /// when they refer multiple MIOperands inside a single one.
3981 bool ARMAsmParser::
3975 void ARMAsmParser::
39823976 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
39833977 const SmallVectorImpl &Operands) {
39843978 // Create a writeback register dummy placeholder.
39863980 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39873981 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
39883982 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3989 return true;
39903983 }
39913984
39923985 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
39933986 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39943987 /// when they refer multiple MIOperands inside a single one.
3995 bool ARMAsmParser::
3988 void ARMAsmParser::
39963989 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
39973990 const SmallVectorImpl &Operands) {
39983991 // Create a writeback register dummy placeholder.
40003993 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
40013994 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
40023995 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4003 return true;
40043996 }
40053997
40063998 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
40073999 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40084000 /// when they refer multiple MIOperands inside a single one.
4009 bool ARMAsmParser::
4001 void ARMAsmParser::
40104002 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
40114003 const SmallVectorImpl &Operands) {
40124004 // Create a writeback register dummy placeholder.
40144006 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
40154007 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
40164008 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4017 return true;
40184009 }
40194010
40204011 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
40214012 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40224013 /// when they refer multiple MIOperands inside a single one.
4023 bool ARMAsmParser::
4014 void ARMAsmParser::
40244015 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
40254016 const SmallVectorImpl &Operands) {
40264017 // Rt
40334024 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
40344025 // pred
40354026 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4036 return true;
40374027 }
40384028
40394029 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
40404030 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40414031 /// when they refer multiple MIOperands inside a single one.
4042 bool ARMAsmParser::
4032 void ARMAsmParser::
40434033 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
40444034 const SmallVectorImpl &Operands) {
40454035 // Rt
40524042 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
40534043 // pred
40544044 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4055 return true;
40564045 }
40574046
40584047 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
40594048 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40604049 /// when they refer multiple MIOperands inside a single one.
4061 bool ARMAsmParser::
4050 void ARMAsmParser::
40624051 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
40634052 const SmallVectorImpl &Operands) {
40644053 // Create a writeback register dummy placeholder.
40714060 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
40724061 // pred
40734062 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4074 return true;
40754063 }
40764064
40774065 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
40784066 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40794067 /// when they refer multiple MIOperands inside a single one.
4080 bool ARMAsmParser::
4068 void ARMAsmParser::
40814069 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
40824070 const SmallVectorImpl &Operands) {
40834071 // Create a writeback register dummy placeholder.
40904078 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
40914079 // pred
40924080 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4093 return true;
40944081 }
40954082
40964083 /// cvtLdrdPre - Convert parsed operands to MCInst.
40974084 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40984085 /// when they refer multiple MIOperands inside a single one.
4099 bool ARMAsmParser::
4086 void ARMAsmParser::
41004087 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
41014088 const SmallVectorImpl &Operands) {
41024089 // Rt, Rt2
41084095 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
41094096 // pred
41104097 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4111 return true;
41124098 }
41134099
41144100 /// cvtStrdPre - Convert parsed operands to MCInst.
41154101 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41164102 /// when they refer multiple MIOperands inside a single one.
4117 bool ARMAsmParser::
4103 void ARMAsmParser::
41184104 cvtStrdPre(MCInst &Inst, unsigned Opcode,
41194105 const SmallVectorImpl &Operands) {
41204106 // Create a writeback register dummy placeholder.
41264112 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
41274113 // pred
41284114 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4129 return true;
41304115 }
41314116
41324117 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
41334118 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41344119 /// when they refer multiple MIOperands inside a single one.
4135 bool ARMAsmParser::
4120 void ARMAsmParser::
41364121 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
41374122 const SmallVectorImpl &Operands) {
41384123 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
41404125 Inst.addOperand(MCOperand::CreateImm(0));
41414126 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
41424127 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4143 return true;
41444128 }
41454129
41464130 /// cvtThumbMultiply - Convert parsed operands to MCInst.
41474131 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41484132 /// when they refer multiple MIOperands inside a single one.
4149 bool ARMAsmParser::
4133 void ARMAsmParser::
41504134 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
41514135 const SmallVectorImpl &Operands) {
41524136 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
41614145 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
41624146 Inst.addOperand(Inst.getOperand(0));
41634147 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4164
4165 return true;
4166 }
4167
4168 bool ARMAsmParser::
4148 }
4149
4150 void ARMAsmParser::
41694151 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
41704152 const SmallVectorImpl &Operands) {
41714153 // Vd
41764158 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
41774159 // pred
41784160 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4179 return true;
4180 }
4181
4182 bool ARMAsmParser::
4161 }
4162
4163 void ARMAsmParser::
41834164 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
41844165 const SmallVectorImpl &Operands) {
41854166 // Vd
41924173 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
41934174 // pred
41944175 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4195 return true;
4196 }
4197
4198 bool ARMAsmParser::
4176 }
4177
4178 void ARMAsmParser::
41994179 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
42004180 const SmallVectorImpl &Operands) {
42014181 // Create a writeback register dummy placeholder.
42064186 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
42074187 // pred
42084188 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4209 return true;
4210 }
4211
4212 bool ARMAsmParser::
4189 }
4190
4191 void ARMAsmParser::
42134192 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
42144193 const SmallVectorImpl &Operands) {
42154194 // Create a writeback register dummy placeholder.
42224201 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
42234202 // pred
42244203 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4225 return true;
42264204 }
42274205
42284206 /// Parse an ARM memory expression, return false if successful else return true
16771677 std::string ConvertFnBody;
16781678 raw_string_ostream CvtOS(ConvertFnBody);
16791679 // Start the unified conversion function.
1680 CvtOS << "bool " << Target.getName() << ClassName << "::\n"
1680 CvtOS << "void " << Target.getName() << ClassName << "::\n"
16811681 << "ConvertToMCInst(unsigned Kind, MCInst &Inst, "
16821682 << "unsigned Opcode,\n"
16831683 << " const SmallVectorImpl
16841684 << "> &Operands) {\n"
1685 << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n"
1685 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
16861686 << " uint8_t *Converter = ConversionTable[Kind];\n"
16871687 << " Inst.setOpcode(Opcode);\n"
16881688 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
16991699 std::string OperandFnBody;
17001700 raw_string_ostream OpOS(OperandFnBody);
17011701 // Start the operand number lookup function.
1702 OpOS << "bool " << Target.getName() << ClassName << "::\n"
1702 OpOS << "void " << Target.getName() << ClassName << "::\n"
17031703 << "GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n"
17041704 << " const SmallVectorImpl &Operands,"
17051705 << "\n unsigned OperandNum, unsigned &MCOperandNum) {\n"
1706 << " if (Kind >= CVT_NUM_SIGNATURES) return false;\n"
1706 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
17071707 << " MCOperandNum = 0;\n"
17081708 << " uint8_t *Converter = ConversionTable[Kind];\n"
17091709 << " for (uint8_t *p = Converter; *p; p+= 2) {\n"
17501750
17511751 // Add the handler to the conversion driver function.
17521752 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1753 << " return " << AsmMatchConverter
1754 << "(Inst, Opcode, Operands);\n";
1753 << " " << AsmMatchConverter << "(Inst, Opcode, Operands);\n"
1754 << " break;\n";
17551755
17561756 // FIXME: Handle the operand number lookup for custom match functions.
17571757 continue;
18981898 }
18991899
19001900 // Finish up the converter driver function.
1901 CvtOS << " }\n }\n return true;\n}\n\n";
1901 CvtOS << " }\n }\n return;\n}\n\n";
19021902
19031903 // Finish up the operand number lookup function.
1904 OpOS << " }\n }\n return true;\n}\n\n";
1904 OpOS << " }\n }\n return;\n}\n\n";
19051905
19061906 OS << "namespace {\n";
19071907
25752575 OS << " // This should be included into the middle of the declaration of\n";
25762576 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
25772577 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2578 OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, "
2578 OS << " void ConvertToMCInst(unsigned Kind, MCInst &Inst, "
25792579 << "unsigned Opcode,\n"
25802580 << " const SmallVectorImpl "
25812581 << "&Operands);\n";
2582 OS << " bool GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n"
2582 OS << " void GetMCInstOperandNum(unsigned Kind, MCInst &Inst,\n"
25832583 << " const SmallVectorImpl "
25842584 << "&Operands,\n unsigned OperandNum, unsigned "
25852585 << "&MCOperandNum);\n";
28632863 OS << "\n";
28642864 OS << " // We have selected a definite instruction, convert the parsed\n"
28652865 << " // operands into the appropriate MCInst.\n";
2866 OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n"
2867 << " it->Opcode, Operands))\n";
2868 OS << " return Match_ConversionFail;\n";
2866 OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
28692867 OS << "\n";
28702868
28712869 // Verify the instruction with the target-specific match predicate function.