llvm.org GIT mirror llvm / 358de24
Use an IndexedMap for LiveOutRegInfo to hide its dependence on TargetRegisterInfo::FirstVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123096 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
4 changed file(s) with 12 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
6464 storage_.resize(NewSize, nullVal_);
6565 }
6666
67 bool inBounds(IndexT n) const {
68 return toIndex_(n) < storage_.size();
69 }
70
6771 typename StorageT::size_type size() const {
6872 return storage_.size();
6973 }
1818 #include "llvm/Instructions.h"
1919 #include "llvm/ADT/APInt.h"
2020 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/IndexedMap.h"
2122 #include "llvm/ADT/SmallVector.h"
2223 #ifndef NDEBUG
2324 #include "llvm/ADT/SmallSet.h"
2627 #include "llvm/CodeGen/ISDOpcodes.h"
2728 #include "llvm/CodeGen/MachineBasicBlock.h"
2829 #include "llvm/Support/CallSite.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
2931 #include
3032
3133 namespace llvm {
103105 LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
104106 };
105107
106 /// LiveOutRegInfo - Information about live out vregs, indexed by their
107 /// register number offset by 'FirstVirtualRegister'.
108 std::vector LiveOutRegInfo;
108 /// LiveOutRegInfo - Information about live out vregs.
109 IndexedMap LiveOutRegInfo;
109110
110111 /// PHINodesToUpdate - A list of phi instructions whose operand list will
111112 /// be updated after processing the current basic block.
4343 #include "llvm/CodeGen/PseudoSourceValue.h"
4444 #include "llvm/CodeGen/SelectionDAG.h"
4545 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
4746 #include "llvm/Target/TargetData.h"
4847 #include "llvm/Target/TargetFrameInfo.h"
4948 #include "llvm/Target/TargetInstrInfo.h"
641640 // If the source register was virtual and if we know something about it,
642641 // add an assert node.
643642 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
644 !RegisterVT.isInteger() || RegisterVT.isVector())
643 !RegisterVT.isInteger() || RegisterVT.isVector() ||
644 !FuncInfo.LiveOutRegInfo.inBounds(Regs[Part+i]))
645645 continue;
646646
647 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
648 if (SlotNo >= FuncInfo.LiveOutRegInfo.size()) continue;
649
650647 const FunctionLoweringInfo::LiveOutInfo &LOI =
651 FuncInfo.LiveOutRegInfo[SlotNo];
648 FuncInfo.LiveOutRegInfo[Regs[Part+i]];
652649
653650 unsigned RegSize = RegisterVT.getSizeInBits();
654651 unsigned NumSignBits = LOI.NumSignBits;
481481
482482 // Only install this information if it tells us something.
483483 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
484 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
485 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
486 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
484 FuncInfo->LiveOutRegInfo.grow(DestReg);
487485 FunctionLoweringInfo::LiveOutInfo &LOI =
488486 FuncInfo->LiveOutRegInfo[DestReg];
489487 LOI.NumSignBits = NumSignBits;