llvm.org GIT mirror llvm / 358d8cc
Merging r276701 and r277439 The saturation instructions appeared in v6T2 / DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to v6T2 / DSP-enable only cores. Fixes PR28607. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@277440 91177308-0d34-0410-b5e6-96231b3b80d8 Renato Golin 4 years ago
7 changed file(s) with 55 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
38563856 // Try to convert two saturating conditional selects into a single SSAT
38573857 SDValue SatValue;
38583858 uint64_t SatConstant;
3859 if (isSaturatingConditional(Op, SatValue, SatConstant))
3859 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
3860 isSaturatingConditional(Op, SatValue, SatConstant))
38603861 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
38613862 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
38623863
36493649
36503650 def SSAT : AI<(outs GPRnopc:$Rd),
36513651 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3652 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3652 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
3653 Requires<[IsARM,HasV6]>{
36533654 bits<4> Rd;
36543655 bits<5> sat_imm;
36553656 bits<4> Rn;
36653666
36663667 def SSAT16 : AI<(outs GPRnopc:$Rd),
36673668 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3668 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3669 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
3670 Requires<[IsARM,HasV6]>{
36693671 bits<4> Rd;
36703672 bits<4> sat_imm;
36713673 bits<4> Rn;
36783680
36793681 def USAT : AI<(outs GPRnopc:$Rd),
36803682 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3681 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3683 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
3684 Requires<[IsARM,HasV6]> {
36823685 bits<4> Rd;
36833686 bits<5> sat_imm;
36843687 bits<4> Rn;
36943697
36953698 def USAT16 : AI<(outs GPRnopc:$Rd),
36963699 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3697 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3700 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
3701 Requires<[IsARM,HasV6]>{
36983702 bits<4> Rd;
36993703 bits<4> sat_imm;
37003704 bits<4> Rn;
22392239 def t2SSAT: T2SatI<
22402240 (outs rGPR:$Rd),
22412241 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2242 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2242 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2243 Requires<[IsThumb2]> {
22432244 let Inst{31-27} = 0b11110;
22442245 let Inst{25-22} = 0b1100;
22452246 let Inst{20} = 0;
22502251 def t2SSAT16: T2SatI<
22512252 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
22522253 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2253 Requires<[IsThumb2, HasDSP]> {
2254 Requires<[IsThumb2, HasDSP]> {
22542255 let Inst{31-27} = 0b11110;
22552256 let Inst{25-22} = 0b1100;
22562257 let Inst{20} = 0;
22642265 def t2USAT: T2SatI<
22652266 (outs rGPR:$Rd),
22662267 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2267 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2268 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
2269 Requires<[IsThumb2]> {
22682270 let Inst{31-27} = 0b11110;
22692271 let Inst{25-22} = 0b1110;
22702272 let Inst{20} = 0;
22742276 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
22752277 NoItinerary,
22762278 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2277 Requires<[IsThumb2, HasDSP]> {
2279 Requires<[IsThumb2, HasDSP]> {
22782280 let Inst{31-22} = 0b1111001110;
22792281 let Inst{20} = 0;
22802282 let Inst{15} = 0;
0 ; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
1
2 ; CHECK: Cannot select: intrinsic %llvm.arm.ssat
3 define i32 @ssat() nounwind {
4 %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
5 ret i32 %tmp
6 }
7
8 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
None ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
0 ; RUN: llc -mtriple=armv4t-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V4T
1 ; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=V6T2
12
23 ; Check for several conditions that should result in SSAT.
34 ; For example, the base test is equivalent to
1516 ; 32-bit base test
1617 define i32 @sat_base_32bit(i32 %x) #0 {
1718 ; CHECK-LABEL: sat_base_32bit:
18 ; CHECK: ssat r0, #24, r0
19 ; V6T2: ssat r0, #24, r0
20 ; V4T-NOT: ssat
1921 entry:
2022 %cmpLow = icmp slt i32 %x, -8388608
2123 %cmpUp = icmp sgt i32 %x, 8388607
2830 ; 16-bit base test
2931 define i16 @sat_base_16bit(i16 %x) #0 {
3032 ; CHECK-LABEL: sat_base_16bit:
31 ; CHECK: ssat r0, #12, r0
33 ; V6T2: ssat r0, #12, r0
34 ; V4T-NOT: ssat
3235 entry:
3336 %cmpLow = icmp slt i16 %x, -2048
3437 %cmpUp = icmp sgt i16 %x, 2047
4144 ; 8-bit base test
4245 define i8 @sat_base_8bit(i8 %x) #0 {
4346 ; CHECK-LABEL: sat_base_8bit:
44 ; CHECK: ssat r0, #6, r0
47 ; V6T2: ssat r0, #6, r0
48 ; V4T-NOT: ssat
4549 entry:
4650 %cmpLow = icmp slt i8 %x, -32
4751 %cmpUp = icmp sgt i8 %x, 31
5963 ; x < -k ? -k : (x < k ? x : k)
6064 define i32 @sat_lower_upper_1(i32 %x) #0 {
6165 ; CHECK-LABEL: sat_lower_upper_1:
62 ; CHECK: ssat r0, #24, r0
66 ; V6T2: ssat r0, #24, r0
67 ; V4T-NOT: ssat
6368 entry:
6469 %cmpLow = icmp slt i32 %x, -8388608
6570 %cmpUp = icmp slt i32 %x, 8388607
7176 ; x > -k ? (x > k ? k : x) : -k
7277 define i32 @sat_lower_upper_2(i32 %x) #0 {
7378 ; CHECK-LABEL: sat_lower_upper_2:
74 ; CHECK: ssat r0, #24, r0
79 ; V6T2: ssat r0, #24, r0
80 ; V4T-NOT: ssat
7581 entry:
7682 %cmpLow = icmp sgt i32 %x, -8388608
7783 %cmpUp = icmp sgt i32 %x, 8388607
8389 ; x < k ? (x < -k ? -k : x) : k
8490 define i32 @sat_upper_lower_1(i32 %x) #0 {
8591 ; CHECK-LABEL: sat_upper_lower_1:
86 ; CHECK: ssat r0, #24, r0
92 ; V6T2: ssat r0, #24, r0
93 ; V4T-NOT: ssat
8794 entry:
8895 %cmpUp = icmp slt i32 %x, 8388607
8996 %cmpLow = icmp slt i32 %x, -8388608
95102 ; x > k ? k : (x < -k ? -k : x)
96103 define i32 @sat_upper_lower_2(i32 %x) #0 {
97104 ; CHECK-LABEL: sat_upper_lower_2:
98 ; CHECK: ssat r0, #24, r0
105 ; V6T2: ssat r0, #24, r0
106 ; V4T-NOT: ssat
99107 entry:
100108 %cmpUp = icmp sgt i32 %x, 8388607
101109 %cmpLow = icmp slt i32 %x, -8388608
107115 ; k < x ? k : (x > -k ? x : -k)
108116 define i32 @sat_upper_lower_3(i32 %x) #0 {
109117 ; CHECK-LABEL: sat_upper_lower_3:
110 ; CHECK: ssat r0, #24, r0
118 ; V6T2: ssat r0, #24, r0
119 ; V4T-NOT: ssat
111120 entry:
112121 %cmpUp = icmp slt i32 8388607, %x
113122 %cmpLow = icmp sgt i32 %x, -8388608
124133 ; k <= x ? k : (x >= -k ? x : -k)
125134 define i32 @sat_le_ge(i32 %x) #0 {
126135 ; CHECK-LABEL: sat_le_ge:
127 ; CHECK: ssat r0, #24, r0
136 ; V6T2: ssat r0, #24, r0
137 ; V4T-NOT: ssat
128138 entry:
129139 %cmpUp = icmp sle i32 8388607, %x
130140 %cmpLow = icmp sge i32 %x, -8388608
0 ; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s
1
2 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
3 define i32 @usat1() nounwind {
4 %tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
5 ret i32 %tmp
6 }
7
8 declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s
0 # RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 2>&1 | FileCheck %s
11
22 # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
33 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0