llvm.org GIT mirror llvm / 356e72c
Fix PR1390 in a better way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8 Lauro Ramos Venancio 13 years ago
1 changed file(s) with 41 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
10541054 if (!STI.isTargetDarwin()) {
10551055 if (Reg == ARM::LR)
10561056 LRSpilled = true;
1057 else
1058 CS1Spilled = true;
1057 CS1Spilled = true;
10591058 continue;
10601059 }
10611060
11281127 if (STI.isTargetDarwin() || hasFP(MF)) {
11291128 MF.setPhysRegUsed(FramePtr);
11301129 NumGPRSpills++;
1130 }
1131
1132 // If stack and double are 8-byte aligned and we are spilling an odd number
1133 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1134 // the integer and double callee save areas.
1135 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1136 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1137 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1138 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1139 unsigned Reg = UnspilledCS1GPRs[i];
1140 // Don't spiil high register if the function is thumb
1141 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1142 MF.setPhysRegUsed(Reg);
1143 AFI->setCSRegisterIsSpilled(Reg);
1144 if (!isReservedReg(MF, Reg))
1145 ExtraCSSpill = true;
1146 break;
1147 }
1148 }
1149 } else if (!UnspilledCS2GPRs.empty() &&
1150 !AFI->isThumbFunction()) {
1151 unsigned Reg = UnspilledCS2GPRs.front();
1152 MF.setPhysRegUsed(Reg);
1153 AFI->setCSRegisterIsSpilled(Reg);
1154 if (!isReservedReg(MF, Reg))
1155 ExtraCSSpill = true;
1156 }
11311157 }
11321158
11331159 // Estimate if we might need to scavenge a register at some point in order
11591185 if (Size >= Limit) {
11601186 // If any non-reserved CS register isn't spilled, just spill one or two
11611187 // extra. That should take care of it!
1162 unsigned Extra;
1163 while (!ExtraCSSpill && !UnspilledCS1GPRs.empty()) {
1188 unsigned NumExtras = TargetAlign / 4;
1189 SmallVector Extras;
1190 while (NumExtras && !UnspilledCS1GPRs.empty()) {
11641191 unsigned Reg = UnspilledCS1GPRs.back();
11651192 UnspilledCS1GPRs.pop_back();
11661193 if (!isReservedReg(MF, Reg)) {
1167 Extra = Reg;
1168 ExtraCSSpill = true;
1194 Extras.push_back(Reg);
1195 NumExtras--;
11691196 }
11701197 }
1171 while (!ExtraCSSpill && !UnspilledCS2GPRs.empty()) {
1198 while (NumExtras && !UnspilledCS2GPRs.empty()) {
11721199 unsigned Reg = UnspilledCS2GPRs.back();
11731200 UnspilledCS2GPRs.pop_back();
11741201 if (!isReservedReg(MF, Reg)) {
1175 Extra = Reg;
1176 ExtraCSSpill = true;
1202 Extras.push_back(Reg);
1203 NumExtras--;
11771204 }
11781205 }
1179 if (ExtraCSSpill) {
1180 MF.setPhysRegUsed(Extra);
1181 AFI->setCSRegisterIsSpilled(Extra);
1206 if (Extras.size() && NumExtras == 0) {
1207 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1208 MF.setPhysRegUsed(Extras[i]);
1209 AFI->setCSRegisterIsSpilled(Extras[i]);
1210 }
11821211 } else {
11831212 // Reserve a slot closest to SP or frame pointer.
11841213 const TargetRegisterClass *RC = &ARM::GPRRegClass;