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Merging r359883: ------------------------------------------------------------------------ r359883 | arsenm | 2019-05-03 06:42:56 -0700 (Fri, 03 May 2019) | 6 lines AMDGPU: Fix incorrect commute with sub when folding immediates When a fold of an immediate into a sub/subrev required shrinking the instruction, the wrong VOP2 opcode was used. This was using the VOP2 equivalent of the original instruction, not the commuted instruction with the inverted opcode. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@360752 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 months ago
2 changed file(s) with 42 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
356356
357357 assert(MI->getOperand(1).isDef());
358358
359 int Op32 = AMDGPU::getVOPe32(Opc);
359 // Make sure to get the 32-bit version of the commuted opcode.
360 unsigned MaybeCommutedOpc = MI->getOpcode();
361 int Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
362
360363 FoldList.push_back(FoldCandidate(MI, CommuteOpNo, OpToFold, true,
361364 Op32));
362365 return true;
249249 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
250250 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
251251 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
252 ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
253 ; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
254 %0:sreg_32_xm0 = S_MOV_B32 12345
255 %1:vgpr_32 = IMPLICIT_DEF
256 %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
257 S_ENDPGM implicit %2
258
259 ...
260
261 ---
262
263 name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
264 tracksRegLiveness: true
265
266 body: |
267 bb.0:
268 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
269 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
270 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
252271 ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
253272 ; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
254 %0:sreg_32_xm0 = S_MOV_B32 12345
255 %1:vgpr_32 = IMPLICIT_DEF
256 %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
257 S_ENDPGM implicit %2
258
259 ...
260
261 ---
262
263 name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
264 tracksRegLiveness: true
265
266 body: |
267 bb.0:
268 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
269 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
270 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
271 ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
272 ; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
273273 %0:vgpr_32 = IMPLICIT_DEF
274274 %1:sreg_32_xm0 = S_MOV_B32 12345
275275 %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
287287 ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
288288 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
289289 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
290 ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
291 ; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
292 %0:sreg_32_xm0 = S_MOV_B32 12345
293 %1:vgpr_32 = IMPLICIT_DEF
294 %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
295 S_ENDPGM implicit %2
296
297 ...
298
299 ---
300
301 name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
302 tracksRegLiveness: true
303
304 body: |
305 bb.0:
306 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
307 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
308 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
290309 ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
291310 ; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
292 %0:sreg_32_xm0 = S_MOV_B32 12345
293 %1:vgpr_32 = IMPLICIT_DEF
294 %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
295 S_ENDPGM implicit %2
296
297 ...
298
299 ---
300
301 name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
302 tracksRegLiveness: true
303
304 body: |
305 bb.0:
306 ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
307 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
308 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
309 ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
310 ; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
311311 %0:vgpr_32 = IMPLICIT_DEF
312312 %1:sreg_32_xm0 = S_MOV_B32 12345
313313 %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec