llvm.org GIT mirror llvm / 351cca4
Revert "[GlobalISel] Refactor the artifact combiner a bit by using MIPatternMatch" This reverts r346166 as it breaks test-suite-verify-machineinstrs-aarch64-globalisel-O0-g. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346175 91177308-0d34-0410-b5e6-96231b3b80d8 Volkan Keles 11 months ago
1 changed file(s) with 36 addition(s) and 54 deletion(s). Raw diff Collapse all Expand all
1313
1414 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
1515 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
16 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
1716 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
1817 #include "llvm/CodeGen/GlobalISel/Utils.h"
1918 #include "llvm/CodeGen/MachineRegisterInfo.h"
2019 #include "llvm/Support/Debug.h"
2120
2221 #define DEBUG_TYPE "legalizer"
23 using namespace llvm::MIPatternMatch;
2422
2523 namespace llvm {
2624 class LegalizationArtifactCombiner {
3735 SmallVectorImpl &DeadInsts) {
3836 if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
3937 return false;
40
41 Builder.setInstr(MI);
42 unsigned DstReg = MI.getOperand(0).getReg();
43 unsigned SrcReg = MI.getOperand(1).getReg();
44
45 // Look through copy instructions.
46 while (mi_match(SrcReg, MRI, m_Copy(m_Reg(SrcReg))))
47 ;
48
49 // aext(trunc x) - > aext/copy/trunc x
50 unsigned TruncSrc;
51 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
38 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
39 MI.getOperand(1).getReg(), MRI)) {
5240 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
53 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
54 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
41 unsigned DstReg = MI.getOperand(0).getReg();
42 unsigned SrcReg = DefMI->getOperand(1).getReg();
43 Builder.setInstr(MI);
44 // We get a copy/trunc/extend depending on the sizes
45 Builder.buildAnyExtOrTrunc(DstReg, SrcReg);
46 markInstAndDefDead(MI, *DefMI, DeadInsts);
5547 return true;
5648 }
5749 return tryFoldImplicitDef(MI, DeadInsts);
6254
6355 if (MI.getOpcode() != TargetOpcode::G_ZEXT)
6456 return false;
65
66 Builder.setInstr(MI);
67 unsigned DstReg = MI.getOperand(0).getReg();
68 unsigned SrcReg = MI.getOperand(1).getReg();
69
70 // Look through copy instructions.
71 while (mi_match(SrcReg, MRI, m_Copy(m_Reg(SrcReg))))
72 ;
73
74 // zext(trunc x) - > and (aext/copy/trunc x), mask
75 unsigned TruncSrc;
76 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
57 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
58 MI.getOperand(1).getReg(), MRI)) {
59 unsigned DstReg = MI.getOperand(0).getReg();
7760 LLT DstTy = MRI.getType(DstReg);
7861 if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
7962 isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
8063 return false;
8164 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
82 LLT SrcTy = MRI.getType(SrcReg);
83 APInt Mask = APInt::getAllOnesValue(SrcTy.getSizeInBits());
84 auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue());
85 Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
86 MIBMask);
87 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
65 Builder.setInstr(MI);
66 unsigned ZExtSrc = MI.getOperand(1).getReg();
67 LLT ZExtSrcTy = MRI.getType(ZExtSrc);
68 APInt Mask = APInt::getAllOnesValue(ZExtSrcTy.getSizeInBits());
69 auto MaskCstMIB = Builder.buildConstant(DstTy, Mask.getZExtValue());
70 unsigned TruncSrc = DefMI->getOperand(1).getReg();
71 // We get a copy/trunc/extend depending on the sizes
72 auto SrcCopyOrTrunc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc);
73 Builder.buildAnd(DstReg, SrcCopyOrTrunc, MaskCstMIB);
74 markInstAndDefDead(MI, *DefMI, DeadInsts);
8875 return true;
8976 }
9077 return tryFoldImplicitDef(MI, DeadInsts);
9582
9683 if (MI.getOpcode() != TargetOpcode::G_SEXT)
9784 return false;
98
99 Builder.setInstr(MI);
100 unsigned DstReg = MI.getOperand(0).getReg();
101 unsigned SrcReg = MI.getOperand(1).getReg();
102
103 // Look through copy instructions.
104 while (mi_match(SrcReg, MRI, m_Copy(m_Reg(SrcReg))))
105 ;
106
107 // sext(trunc x) - > ashr (shl (aext/copy/trunc x), c), c
108 unsigned TruncSrc;
109 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
85 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
86 MI.getOperand(1).getReg(), MRI)) {
87 unsigned DstReg = MI.getOperand(0).getReg();
11088 LLT DstTy = MRI.getType(DstReg);
11189 if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy}}) ||
11290 isInstUnsupported({TargetOpcode::G_ASHR, {DstTy}}) ||
11391 isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
11492 return false;
11593 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
116 LLT SrcTy = MRI.getType(SrcReg);
117 unsigned ShAmt = DstTy.getSizeInBits() - SrcTy.getSizeInBits();
118 auto MIBShAmt = Builder.buildConstant(DstTy, ShAmt);
119 auto MIBShl = Builder.buildInstr(
120 TargetOpcode::G_SHL, DstTy,
121 Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), MIBShAmt);
122 Builder.buildInstr(TargetOpcode::G_ASHR, DstReg, MIBShl, MIBShAmt);
123 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
94 Builder.setInstr(MI);
95 unsigned SExtSrc = MI.getOperand(1).getReg();
96 LLT SExtSrcTy = MRI.getType(SExtSrc);
97 unsigned SizeDiff = DstTy.getSizeInBits() - SExtSrcTy.getSizeInBits();
98 auto SizeDiffMIB = Builder.buildConstant(DstTy, SizeDiff);
99 unsigned TruncSrcReg = DefMI->getOperand(1).getReg();
100 // We get a copy/trunc/extend depending on the sizes
101 auto SrcCopyExtOrTrunc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrcReg);
102 auto ShlMIB = Builder.buildInstr(TargetOpcode::G_SHL, DstTy,
103 SrcCopyExtOrTrunc, SizeDiffMIB);
104 Builder.buildInstr(TargetOpcode::G_ASHR, DstReg, ShlMIB, SizeDiffMIB);
105 markInstAndDefDead(MI, *DefMI, DeadInsts);
124106 return true;
125107 }
126108 return tryFoldImplicitDef(MI, DeadInsts);