llvm.org GIT mirror llvm / 34e6588
[mips] Try to fix the test/ExecutionEngine tests on a MIPS host. Fix a dangerous default case that caused MipsCodeEmitter to discard pseudo instructions it didn't recognize. It will now call llvm_unreachable() for unrecognized pseudo's and explicitly handles PseudoReturn, PseudoReturn64, PseudoIndirectBranch, PseudoIndirectBranch64, CFI_INSTRUCTION, IMPLICIT_DEF, and KILL. There may be other pseudos that need handling but this was enough for the ExecutionEngine tests to pass on my test system. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213513 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 5 years ago
1 changed file(s) with 49 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
129129 void expandACCInstr(MachineBasicBlock::instr_iterator MI,
130130 MachineBasicBlock &MBB, unsigned Opc) const;
131131
132 void expandPseudoIndirectBranch(MachineBasicBlock::instr_iterator MI,
133 MachineBasicBlock &MBB) const;
134
132135 /// \brief Expand pseudo instruction. Return true if MI was expanded.
133136 bool expandPseudos(MachineBasicBlock::instr_iterator &MI,
134137 MachineBasicBlock &MBB) const;
372375 .addReg(MI->getOperand(1).getReg()).addReg(MI->getOperand(2).getReg());
373376 }
374377
378 void MipsCodeEmitter::expandPseudoIndirectBranch(
379 MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB) const {
380 // This logic is duplicated from MipsAsmPrinter::emitPseudoIndirectBranch()
381 bool HasLinkReg = false;
382 unsigned Opcode = 0;
383
384 if (Subtarget->hasMips64r6()) {
385 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
386 Opcode = Mips::JALR64;
387 HasLinkReg = true;
388 } else if (Subtarget->hasMips32r6()) {
389 // MIPS32r6 should use (JALR ZERO, $rs)
390 Opcode = Mips::JALR;
391 HasLinkReg = true;
392 } else if (Subtarget->inMicroMipsMode())
393 // microMIPS should use (JR_MM $rs)
394 Opcode = Mips::JR_MM;
395 else {
396 // Everything else should use (JR $rs)
397 Opcode = Mips::JR;
398 }
399
400 auto MIB = BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opcode));
401
402 if (HasLinkReg) {
403 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
404 MIB.addReg(ZeroReg);
405 }
406
407 MIB.addReg(MI->getOperand(0).getReg());
408 }
409
375410 bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI,
376411 MachineBasicBlock &MBB) const {
377412 switch (MI->getOpcode()) {
413 default:
414 llvm_unreachable("Unhandled pseudo");
415 return false;
378416 case Mips::NOP:
379417 BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
380418 .addReg(Mips::ZERO).addImm(0);
415453 case Mips::PseudoMSUBU:
416454 expandACCInstr(MI, MBB, Mips::MSUBU);
417455 break;
418 default:
419 return false;
456 case Mips::PseudoReturn:
457 case Mips::PseudoReturn64:
458 case Mips::PseudoIndirectBranch:
459 case Mips::PseudoIndirectBranch64:
460 expandPseudoIndirectBranch(MI, MBB);
461 break;
462 case TargetOpcode::CFI_INSTRUCTION:
463 case TargetOpcode::IMPLICIT_DEF:
464 case TargetOpcode::KILL:
465 // Do nothing
466 return false;
420467 }
421468
422469 (MI--)->eraseFromBundle();