llvm.org GIT mirror llvm / 34dcc6f
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
47 changed file(s) with 142 addition(s) and 124 deletion(s). Raw diff Collapse all Expand all
314314 MachineBasicBlock::iterator MI,
315315 unsigned DestReg, unsigned SrcReg,
316316 const TargetRegisterClass *DestRC,
317 const TargetRegisterClass *SrcRC) const {
317 const TargetRegisterClass *SrcRC,
318 DebugLoc DL) const {
318319 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
319320 return false;
320321 }
139139 // Insert copy
140140 const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
141141 const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
142 bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
142 bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS,
143 MI->getDebugLoc());
143144 (void)Emitted;
144145 assert(Emitted && "Subreg and Dst must be of compatible register class");
145146 // Transfer the kill/dead flags, if needed.
192193 // Insert sub-register copy
193194 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
194195 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
195 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
196 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
197 MI->getDebugLoc());
196198 (void)Emitted;
197199 assert(Emitted && "Subreg and Dst must be of compatible register class");
198200 // Transfer the kill/dead flags, if needed.
261263 BuildMI(*MBB, MI, MI->getDebugLoc(),
262264 TII->get(TargetOpcode::KILL), DstSubReg);
263265 else {
264 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
266 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
267 MI->getDebugLoc());
265268 (void)Emitted;
266269 assert(Emitted && "Subreg and Dst must be of compatible register class");
267270 }
217217 --Pos;
218218 }
219219
220 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
220 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC,
221 DebugLoc());
221222 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
222223 (void) Emitted;
223224
252253 if (LI->second) {
253254 const TargetRegisterClass *RC = getRegClass(LI->second);
254255 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
255 LI->second, LI->first, RC, RC);
256 LI->second, LI->first, RC, RC,
257 DebugLoc());
256258 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
257259 (void) Emitted;
258260 }
209209 } else {
210210 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
211211 }
212 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
212 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC,
213 MPhi->getDebugLoc());
213214 }
214215
215216 // Update live variable information if there is any.
291292
292293 // Insert the copy.
293294 if (!reusedIncoming && IncomingReg)
294 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
295 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC,
296 MPhi->getDebugLoc());
295297
296298 // Now update live variable information if we have it. Otherwise we're done
297299 if (!LV) continue;
5050 }
5151 }
5252 bool Success = TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second,
53 SU->CopyDstRC, SU->CopySrcRC);
53 SU->CopyDstRC, SU->CopySrcRC,
54 DebugLoc());
5455 (void)Success;
5556 assert(Success && "copyRegToReg failed!");
5657 } else {
6162 isNew = isNew; // Silence compiler warning.
6263 assert(isNew && "Node emitted out of order - early");
6364 bool Success = TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(),
64 SU->CopyDstRC, SU->CopySrcRC);
65 SU->CopyDstRC, SU->CopySrcRC,
66 DebugLoc());
6567 (void)Success;
6668 assert(Success && "copyRegToReg failed!");
6769 }
184184 else if (Reg != AssignedReg) {
185185 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
186186 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
187 Reg, RegClass, RegClass);
187 Reg, RegClass, RegClass, DL);
188188 }
189189 return AssignedReg;
190190 }
412412 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
413413 unsigned ResultReg = createResultReg(RC);
414414 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
415 Reg, RC, RC);
415 Reg, RC, RC, DL);
416416 assert(InsertedCopy && "Can't copy address registers!");
417417 InsertedCopy = InsertedCopy;
418418 UpdateValueMap(I, ResultReg);
442442 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
443443 unsigned ResultReg = createResultReg(RC);
444444 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
445 RC, RC);
445 RC, RC, DL);
446446 assert(InsertedCopy && "Can't copy address registers!");
447447 InsertedCopy = InsertedCopy;
448448
555555 ResultReg = createResultReg(DstClass);
556556
557557 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
558 Op0, DstClass, SrcClass);
558 Op0, DstClass, SrcClass, DL);
559559 if (!InsertedCopy)
560560 ResultReg = 0;
561561 }
928928 else {
929929 BuildMI(MBB, DL, II).addReg(Op0);
930930 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
931 II.ImplicitDefs[0], RC, RC);
931 II.ImplicitDefs[0], RC, RC, DL);
932932 if (!InsertedCopy)
933933 ResultReg = 0;
934934 }
947947 else {
948948 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
949949 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
950 II.ImplicitDefs[0], RC, RC);
950 II.ImplicitDefs[0], RC, RC, DL);
951951 if (!InsertedCopy)
952952 ResultReg = 0;
953953 }
965965 else {
966966 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
967967 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
968 II.ImplicitDefs[0], RC, RC);
968 II.ImplicitDefs[0], RC, RC, DL);
969969 if (!InsertedCopy)
970970 ResultReg = 0;
971971 }
983983 else {
984984 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
985985 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
986 II.ImplicitDefs[0], RC, RC);
986 II.ImplicitDefs[0], RC, RC, DL);
987987 if (!InsertedCopy)
988988 ResultReg = 0;
989989 }
10011001 else {
10021002 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
10031003 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1004 II.ImplicitDefs[0], RC, RC);
1004 II.ImplicitDefs[0], RC, RC, DL);
10051005 if (!InsertedCopy)
10061006 ResultReg = 0;
10071007 }
10191019 else {
10201020 BuildMI(MBB, DL, II).addImm(Imm);
10211021 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1022 II.ImplicitDefs[0], RC, RC);
1022 II.ImplicitDefs[0], RC, RC, DL);
10231023 if (!InsertedCopy)
10241024 ResultReg = 0;
10251025 }
10381038 else {
10391039 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
10401040 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1041 II.ImplicitDefs[0], RC, RC);
1041 II.ImplicitDefs[0], RC, RC, DL);
10421042 if (!InsertedCopy)
10431043 ResultReg = 0;
10441044 }
142142 // Create the reg, emit the copy.
143143 VRBase = MRI->createVirtualRegister(DstRC);
144144 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
145 DstRC, SrcRC);
145 DstRC, SrcRC, Node->getDebugLoc());
146146
147147 assert(Emitted && "Unable to issue a copy instruction!\n");
148148 (void) Emitted;
288288 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
289289 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
290290 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
291 DstRC, SrcRC);
291 DstRC, SrcRC, Op.getNode()->getDebugLoc());
292292 assert(Emitted && "Unable to issue a copy instruction!\n");
293293 (void) Emitted;
294294 VReg = NewVReg;
502502 // Create the new VReg in the destination class and emit a copy.
503503 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
504504 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
505 DstRC, SrcRC);
505 DstRC, SrcRC, Node->getDebugLoc());
506506 assert(Emitted &&
507507 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
508508 (void) Emitted;
748748 Node->getOperand(1).getValueType());
749749
750750 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
751 DstTRC, SrcTRC);
751 DstTRC, SrcTRC, Node->getDebugLoc());
752752 assert(Emitted && "Unable to issue a copy instruction!\n");
753753 (void) Emitted;
754754 break;
335335 // Insert a copy at the start of the MBB. The range proceeding the
336336 // copy will be attached to the original LiveInterval.
337337 MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def);
338 tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc);
338 tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc,
339 DebugLoc());
339340 MachineInstr *copyMI = defMBB->begin();
340341 copyMI->addRegisterKilled(li->reg, tri);
341342 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
388389
389390 if (isTwoAddr && !twoAddrUseIsUndef) {
390391 MachineBasicBlock *defMBB = defInst->getParent();
391 tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc);
392 tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc,
393 DebugLoc());
392394 MachineInstr *copyMI = prior(MachineBasicBlock::iterator(defInst));
393395 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
394396 copyMI->addRegisterKilled(li->reg, tri);
448450 // reg.
449451 MachineBasicBlock *useMBB = useInst->getParent();
450452 MachineBasicBlock::iterator useItr(useInst);
451 tii->copyRegToReg(*useMBB, next(useItr), li->reg, newVReg, trc, trc);
453 tii->copyRegToReg(*useMBB, next(useItr), li->reg, newVReg, trc, trc,
454 DebugLoc());
452455 MachineInstr *copyMI = next(useItr);
453456 copyMI->addRegisterKilled(newVReg, tri);
454457 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
485488 assert(oldKillRange != 0 && "No kill range?");
486489
487490 tii->copyRegToReg(*killMBB, killMBB->getFirstTerminator(),
488 li->reg, newVReg, trc, trc);
491 li->reg, newVReg, trc, trc,
492 DebugLoc());
489493 MachineInstr *copyMI = prior(killMBB->getFirstTerminator());
490494 copyMI->addRegisterKilled(newVReg, tri);
491495 SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
606606 DEBUG(MI->dump());
607607 ++NumLoadElim;
608608 } else {
609 TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
609 TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC,
610 MI->getDebugLoc());
610611 ++NumRegRepl;
611612 }
612613
622623 DEBUG(MI->dump());
623624 ++NumStoreElim;
624625 } else {
625 TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);
626 TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC,
627 MI->getDebugLoc());
626628 ++NumRegRepl;
627629 }
628630
695695 // the Phi defining curr.second
696696 MachineBasicBlock::iterator PI = MRI.getVRegDef(curr.second);
697697 TII->copyRegToReg(*PI->getParent(), PI, t,
698 curr.second, RC, RC);
698 curr.second, RC, RC, DebugLoc());
699699
700700 DEBUG(dbgs() << "Inserted copy from " << curr.second << " to " << t
701701 << "\n");
712712
713713 // Insert copy from map[curr.first] to curr.second
714714 TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), curr.second,
715 map[curr.first], RC, RC);
715 map[curr.first], RC, RC, DebugLoc());
716716 map[curr.first] = curr.second;
717717 DEBUG(dbgs() << "Inserted copy from " << curr.first << " to "
718718 << curr.second << "\n");
761761 // Insert a copy from dest to a new temporary t at the end of b
762762 unsigned t = MF->getRegInfo().createVirtualRegister(RC);
763763 TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), t,
764 curr.second, RC, RC);
764 curr.second, RC, RC, DebugLoc());
765765 map[curr.second] = t;
766766
767767 MachineBasicBlock::iterator TI = MBB->getFirstTerminator();
960960 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
961961 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(I->first);
962962 TII->copyRegToReg(*SI->second, SI->second->getFirstTerminator(),
963 I->first, SI->first, RC, RC);
963 I->first, SI->first, RC, RC, DebugLoc());
964964
965965 LI.renumber();
966966
560560 for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
561561 const TargetRegisterClass *RC = MRI->getRegClass(CopyInfos[i].first);
562562 TII->copyRegToReg(*PredBB, Loc, CopyInfos[i].first,
563 CopyInfos[i].second, RC,RC);
563 CopyInfos[i].second, RC,RC, DebugLoc());
564564 MachineInstr *CopyMI = prior(Loc);
565565 Copies.push_back(CopyMI);
566566 }
619619 for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
620620 const TargetRegisterClass *RC = MRI->getRegClass(CopyInfos[i].first);
621621 TII->copyRegToReg(*PrevBB, Loc, CopyInfos[i].first,
622 CopyInfos[i].second, RC, RC);
622 CopyInfos[i].second, RC, RC, DebugLoc());
623623 MachineInstr *CopyMI = prior(Loc);
624624 Copies.push_back(CopyMI);
625625 }
10471047 ReMatRegs.set(regB);
10481048 ++NumReMats;
10491049 } else {
1050 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
1050 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc,
1051 mi->getDebugLoc());
10511052 (void)Emitted;
10521053 assert(Emitted && "Unable to issue a copy instruction!\n");
10531054 }
17931793 ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat, SSorRMId, TII,
17941794 *MBB->getParent());
17951795
1796 TII->copyRegToReg(*MBB, InsertLoc, Phys, InReg, RC, RC);
1796 TII->copyRegToReg(*MBB, InsertLoc, Phys, InReg, RC, RC,
1797 MI->getDebugLoc());
17971798
17981799 // This invalidates Phys.
17991800 Spills.ClobberPhysReg(Phys);
21382139 ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
21392140 SSorRMId, TII, MF);
21402141
2141 TII->copyRegToReg(*MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
2142 TII->copyRegToReg(*MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC,
2143 MI.getDebugLoc());
21422144
21432145 MachineInstr *CopyMI = prior(InsertLoc);
21442146 CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
22622264 DEBUG(dbgs() << "Promoted Load To Copy: " << MI);
22632265 if (DestReg != InReg) {
22642266 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
2265 TII->copyRegToReg(*MBB, &MI, DestReg, InReg, RC, RC);
2267 TII->copyRegToReg(*MBB, &MI, DestReg, InReg, RC, RC,
2268 MI.getDebugLoc());
22662269 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
22672270 unsigned SubIdx = DefMO->getSubReg();
22682271 // Revisit the copy so we make sure to notice the effects of the
656656 MachineBasicBlock::iterator I,
657657 unsigned DestReg, unsigned SrcReg,
658658 const TargetRegisterClass *DestRC,
659 const TargetRegisterClass *SrcRC) const {
660 DebugLoc DL;
661 if (I != MBB.end()) DL = I->getDebugLoc();
662
659 const TargetRegisterClass *SrcRC,
660 DebugLoc DL) const {
663661 // tGPR is used sometimes in ARM instructions that need to avoid using
664662 // certain registers. Just treat it as GPR here.
665663 if (DestRC == ARM::tGPRRegisterClass)
256256 MachineBasicBlock::iterator I,
257257 unsigned DestReg, unsigned SrcReg,
258258 const TargetRegisterClass *DestRC,
259 const TargetRegisterClass *SrcRC) const;
259 const TargetRegisterClass *SrcRC,
260 DebugLoc DL) const;
260261
261262 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
262263 MachineBasicBlock::iterator MBBI,
409409 if (MO.isUse()) {
410410 // Insert a copy from VirtReg.
411411 TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
412 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
412 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
413 DebugLoc());
413414 if (MO.isKill()) {
414415 MachineInstr *CopyMI = prior(MBBI);
415416 CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
418419 } else if (MO.isDef() && !MO.isDead()) {
419420 // Add a copy to VirtReg.
420421 TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
421 ARM::DPRRegisterClass, ARM::DPRRegisterClass);
422 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
423 DebugLoc());
422424 }
423425 }
424426 }
3535 MachineBasicBlock::iterator I,
3636 unsigned DestReg, unsigned SrcReg,
3737 const TargetRegisterClass *DestRC,
38 const TargetRegisterClass *SrcRC) const {
39 DebugLoc DL;
40 if (I != MBB.end()) DL = I->getDebugLoc();
41
38 const TargetRegisterClass *SrcRC,
39 DebugLoc DL) const {
4240 if (DestRC == ARM::GPRRegisterClass) {
4341 if (SrcRC == ARM::GPRRegisterClass) {
4442 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
4747 MachineBasicBlock::iterator I,
4848 unsigned DestReg, unsigned SrcReg,
4949 const TargetRegisterClass *DestRC,
50 const TargetRegisterClass *SrcRC) const;
50 const TargetRegisterClass *SrcRC,
51 DebugLoc DL) const;
5152 void storeRegToStackSlot(MachineBasicBlock &MBB,
5253 MachineBasicBlock::iterator MBBI,
5354 unsigned SrcReg, bool isKill, int FrameIndex,
3939 MachineBasicBlock::iterator I,
4040 unsigned DestReg, unsigned SrcReg,
4141 const TargetRegisterClass *DestRC,
42 const TargetRegisterClass *SrcRC) const {
43 DebugLoc DL;
44 if (I != MBB.end()) DL = I->getDebugLoc();
45
42 const TargetRegisterClass *SrcRC,
43 DebugLoc DL) const {
4644 if (DestRC == ARM::GPRRegisterClass) {
4745 if (SrcRC == ARM::GPRRegisterClass) {
4846 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
6260 }
6361
6462 // Handle SPR, DPR, and QPR copies.
65 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
63 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC, DL);
6664 }
6765
6866 void Thumb2InstrInfo::
3434 MachineBasicBlock::iterator I,
3535 unsigned DestReg, unsigned SrcReg,
3636 const TargetRegisterClass *DestRC,
37 const TargetRegisterClass *SrcRC) const;
37 const TargetRegisterClass *SrcRC,
38 DebugLoc DL) const;
3839
3940 void storeRegToStackSlot(MachineBasicBlock &MBB,
4041 MachineBasicBlock::iterator MBBI,
145145 MachineBasicBlock::iterator MI,
146146 unsigned DestReg, unsigned SrcReg,
147147 const TargetRegisterClass *DestRC,
148 const TargetRegisterClass *SrcRC) const {
148 const TargetRegisterClass *SrcRC,
149 DebugLoc DL) const {
149150 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
150151 if (DestRC != SrcRC) {
151152 // Not yet supported!
152153 return false;
153154 }
154
155 DebugLoc DL;
156 if (MI != MBB.end()) DL = MI->getDebugLoc();
157155
158156 if (DestRC == Alpha::GPRCRegisterClass) {
159157 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
430428
431429 GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
432430 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
433 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
431 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
432 DebugLoc());
434433 assert(Ok && "Couldn't assign to global base register!");
435434 Ok = Ok; // Silence warning when assertions are turned off.
436435 RegInfo.addLiveIn(Alpha::R29);
457456
458457 GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
459458 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
460 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass);
459 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
460 DebugLoc());
461461 assert(Ok && "Couldn't assign to global return address register!");
462462 Ok = Ok; // Silence warning when assertions are turned off.
463463 RegInfo.addLiveIn(Alpha::R26);
4747 MachineBasicBlock::iterator MI,
4848 unsigned DestReg, unsigned SrcReg,
4949 const TargetRegisterClass *DestRC,
50 const TargetRegisterClass *SrcRC) const;
50 const TargetRegisterClass *SrcRC,
51 DebugLoc DL) const;
5152 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
5253 MachineBasicBlock::iterator MBBI,
5354 unsigned SrcReg, bool isKill, int FrameIndex,
137137 unsigned DestReg,
138138 unsigned SrcReg,
139139 const TargetRegisterClass *DestRC,
140 const TargetRegisterClass *SrcRC) const {
141 DebugLoc DL;
142
140 const TargetRegisterClass *SrcRC,
141 DebugLoc DL) const {
143142 if (inClass(BF::ALLRegClass, DestReg, DestRC) &&
144143 inClass(BF::ALLRegClass, SrcReg, SrcRC)) {
145144 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg).addReg(SrcReg);
4949 MachineBasicBlock::iterator I,
5050 unsigned DestReg, unsigned SrcReg,
5151 const TargetRegisterClass *DestRC,
52 const TargetRegisterClass *SrcRC) const;
52 const TargetRegisterClass *SrcRC,
53 DebugLoc DL) const;
5354
5455 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
5556 MachineBasicBlock::iterator MBBI,
254254 MachineBasicBlock::iterator MI,
255255 unsigned DestReg, unsigned SrcReg,
256256 const TargetRegisterClass *DestRC,
257 const TargetRegisterClass *SrcRC) const
257 const TargetRegisterClass *SrcRC,
258 DebugLoc DL) const
258259 {
259260 // We support cross register class moves for our aliases, such as R3 in any
260261 // reg class to any other reg class containing R3. This is required because
261262 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
262263 // types have no specific meaning.
263
264 DebugLoc DL;
265 if (MI != MBB.end()) DL = MI->getDebugLoc();
266264
267265 if (DestRC == SPU::R8CRegisterClass) {
268266 BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
5959 MachineBasicBlock::iterator MI,
6060 unsigned DestReg, unsigned SrcReg,
6161 const TargetRegisterClass *DestRC,
62 const TargetRegisterClass *SrcRC) const;
62 const TargetRegisterClass *SrcRC,
63 DebugLoc DL) const;
6364
6465 //! Store a register to a stack slot, based on its register class.
6566 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
113113 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114114 unsigned DestReg, unsigned SrcReg,
115115 const TargetRegisterClass *DestRC,
116 const TargetRegisterClass *SrcRC) const {
117 DebugLoc DL;
116 const TargetRegisterClass *SrcRC,
117 DebugLoc DL) const {
118118 llvm::BuildMI(MBB, I, DL, get(MBlaze::ADD), DestReg)
119119 .addReg(SrcReg).addReg(MBlaze::R0);
120120 return true;
210210 GlobalBaseReg = RegInfo.createVirtualRegister(MBlaze::CPURegsRegisterClass);
211211 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, MBlaze::R20,
212212 MBlaze::CPURegsRegisterClass,
213 MBlaze::CPURegsRegisterClass);
213 MBlaze::CPURegsRegisterClass,
214 DebugLoc());
214215 assert(Ok && "Couldn't assign to global base register!");
215216 Ok = Ok; // Silence warning when assertions are turned off.
216217 RegInfo.addLiveIn(MBlaze::R20);
202202 MachineBasicBlock::iterator I,
203203 unsigned DestReg, unsigned SrcReg,
204204 const TargetRegisterClass *DestRC,
205 const TargetRegisterClass *SrcRC) const;
205 const TargetRegisterClass *SrcRC,
206 DebugLoc DL) const;
206207 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
207208 MachineBasicBlock::iterator MBBI,
208209 unsigned SrcReg, bool isKill, int FrameIndex,
8686 MachineBasicBlock::iterator I,
8787 unsigned DestReg, unsigned SrcReg,
8888 const TargetRegisterClass *DestRC,
89 const TargetRegisterClass *SrcRC) const {
90 DebugLoc DL;
91 if (I != MBB.end()) DL = I->getDebugLoc();
92
89 const TargetRegisterClass *SrcRC,
90 DebugLoc DL) const {
9391 if (DestRC == SrcRC) {
9492 unsigned Opc;
9593 if (DestRC == &MSP430::GR16RegClass) {
5151 bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
5252 unsigned DestReg, unsigned SrcReg,
5353 const TargetRegisterClass *DestRC,
54 const TargetRegisterClass *SrcRC) const;
54 const TargetRegisterClass *SrcRC,
55 DebugLoc DL) const;
5556
5657 bool isMoveInstr(const MachineInstr& MI,
5758 unsigned &SrcReg, unsigned &DstReg,
130130 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
131131 unsigned DestReg, unsigned SrcReg,
132132 const TargetRegisterClass *DestRC,
133 const TargetRegisterClass *SrcRC) const {
134 DebugLoc DL;
135
136 if (I != MBB.end()) DL = I->getDebugLoc();
133 const TargetRegisterClass *SrcRC,
134 DebugLoc DL) const {
137135
138136 if (DestRC != SrcRC) {
139137
624622 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
625623 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
626624 Mips::CPURegsRegisterClass,
627 Mips::CPURegsRegisterClass);
625 Mips::CPURegsRegisterClass,
626 DebugLoc());
628627 assert(Ok && "Couldn't assign to global base register!");
629628 Ok = Ok; // Silence warning when assertions are turned off.
630629 RegInfo.addLiveIn(Mips::GP);
208208 MachineBasicBlock::iterator I,
209209 unsigned DestReg, unsigned SrcReg,
210210 const TargetRegisterClass *DestRC,
211 const TargetRegisterClass *SrcRC) const;
211 const TargetRegisterClass *SrcRC,
212 DebugLoc DL) const;
212213 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
213214 MachineBasicBlock::iterator MBBI,
214215 unsigned SrcReg, bool isKill, int FrameIndex,
154154 MachineBasicBlock::iterator I,
155155 unsigned DestReg, unsigned SrcReg,
156156 const TargetRegisterClass *DestRC,
157 const TargetRegisterClass *SrcRC) const {
158 DebugLoc DL;
159 if (I != MBB.end()) DL = I->getDebugLoc();
157 const TargetRegisterClass *SrcRC,
158 DebugLoc DL) const {
160159
161160 if (DestRC == PIC16::FSR16RegisterClass) {
162161 BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
6060 MachineBasicBlock::iterator MBBI,
6161 unsigned DestReg, unsigned SrcReg,
6262 const TargetRegisterClass *DestRC,
63 const TargetRegisterClass *SrcRC) const;
63 const TargetRegisterClass *SrcRC,
64 DebugLoc DL) const;
6465 virtual bool isMoveInstr(const MachineInstr &MI,
6566 unsigned &SrcReg, unsigned &DstReg,
6667 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
344344 MachineBasicBlock::iterator MI,
345345 unsigned DestReg, unsigned SrcReg,
346346 const TargetRegisterClass *DestRC,
347 const TargetRegisterClass *SrcRC) const {
347 const TargetRegisterClass *SrcRC,
348 DebugLoc DL) const {
348349 if (DestRC != SrcRC) {
349350 // Not yet supported!
350351 return false;
351352 }
352
353 DebugLoc DL;
354 if (MI != MBB.end()) DL = MI->getDebugLoc();
355353
356354 if (DestRC == PPC::GPRCRegisterClass) {
357355 BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
113113 MachineBasicBlock::iterator MI,
114114 unsigned DestReg, unsigned SrcReg,
115115 const TargetRegisterClass *DestRC,
116 const TargetRegisterClass *SrcRC) const;
116 const TargetRegisterClass *SrcRC,
117 DebugLoc DL) const;
117118
118119 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
119120 MachineBasicBlock::iterator MBBI,
121121 MachineBasicBlock::iterator I,
122122 unsigned DestReg, unsigned SrcReg,
123123 const TargetRegisterClass *DestRC,
124 const TargetRegisterClass *SrcRC) const {
124 const TargetRegisterClass *SrcRC,
125 DebugLoc DL) const {
125126 if (DestRC != SrcRC) {
126127 // Not yet supported!
127128 return false;
128129 }
129
130 DebugLoc DL;
131 if (I != MBB.end()) DL = I->getDebugLoc();
132130
133131 if (DestRC == SP::IntRegsRegisterClass)
134132 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
7373 MachineBasicBlock::iterator I,
7474 unsigned DestReg, unsigned SrcReg,
7575 const TargetRegisterClass *DestRC,
76 const TargetRegisterClass *SrcRC) const;
76 const TargetRegisterClass *SrcRC,
77 DebugLoc DL) const;
7778
7879 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
7980 MachineBasicBlock::iterator MBBI,
120120 MachineBasicBlock::iterator I,
121121 unsigned DestReg, unsigned SrcReg,
122122 const TargetRegisterClass *DestRC,
123 const TargetRegisterClass *SrcRC) const {
124 DebugLoc DL;
125 if (I != MBB.end()) DL = I->getDebugLoc();
123 const TargetRegisterClass *SrcRC,
124 DebugLoc DL) const {
126125
127126 // Determine if DstRC and SrcRC have a common superclass.
128127 const TargetRegisterClass *CommonRC = DestRC;
6262 bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6363 unsigned DestReg, unsigned SrcReg,
6464 const TargetRegisterClass *DestRC,
65 const TargetRegisterClass *SrcRC) const;
65 const TargetRegisterClass *SrcRC,
66 DebugLoc DL) const;
6667
6768 bool isMoveInstr(const MachineInstr& MI,
6869 unsigned &SrcReg, unsigned &DstReg,
10181018
10191019 unsigned Op1Reg = getRegForValue(I->getOperand(1));
10201020 if (Op1Reg == 0) return false;
1021 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
1021 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
10221022
10231023 // The shift instruction uses X86::CL. If we defined a super-register
10241024 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
14461446 if (VA.isRegLoc()) {
14471447 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
14481448 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1449 Arg, RC, RC);
1449 Arg, RC, RC, DL);
14501450 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
14511451 Emitted = true;
14521452 RegArgs.push_back(VA.getLocReg());
14721472 if (Subtarget->isPICStyleGOT()) {
14731473 TargetRegisterClass *RC = X86::GR32RegisterClass;
14741474 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1475 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1475 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1476 DL);
14761477 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
14771478 Emitted = true;
14781479 }
15511552
15521553 unsigned ResultReg = createResultReg(DstRC);
15531554 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1554 RVLocs[0].getLocReg(), DstRC, SrcRC);
1555 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
15551556 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
15561557 Emitted = true;
15571558 if (CopyVT != RVLocs[0].getValVT()) {
19001900 MachineBasicBlock::iterator MI,
19011901 unsigned DestReg, unsigned SrcReg,
19021902 const TargetRegisterClass *DestRC,
1903 const TargetRegisterClass *SrcRC) const {
1904 DebugLoc DL = MBB.findDebugLoc(MI);
1903 const TargetRegisterClass *SrcRC,
1904 DebugLoc DL) const {
19051905
19061906 // Determine if DstRC and SrcRC have a common superclass in common.
19071907 const TargetRegisterClass *CommonRC = DestRC;
589589 MachineBasicBlock::iterator MI,
590590 unsigned DestReg, unsigned SrcReg,
591591 const TargetRegisterClass *DestRC,
592 const TargetRegisterClass *SrcRC) const;
592 const TargetRegisterClass *SrcRC,
593 DebugLoc DL) const;
593594 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
594595 MachineBasicBlock::iterator MI,
595596 unsigned SrcReg, bool isKill, int FrameIndex,
360360 MachineBasicBlock::iterator I,
361361 unsigned DestReg, unsigned SrcReg,
362362 const TargetRegisterClass *DestRC,
363 const TargetRegisterClass *SrcRC) const {
364 DebugLoc DL;
365 if (I != MBB.end()) DL = I->getDebugLoc();
363 const TargetRegisterClass *SrcRC,
364 DebugLoc DL) const {
366365
367366 if (DestRC == SrcRC) {
368367 if (DestRC == XCore::GRRegsRegisterClass) {
6666 MachineBasicBlock::iterator I,
6767 unsigned DestReg, unsigned SrcReg,
6868 const TargetRegisterClass *DestRC,
69 const TargetRegisterClass *SrcRC) const;
69 const TargetRegisterClass *SrcRC,
70 DebugLoc DL) const;
7071
7172 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
7273 MachineBasicBlock::iterator MI,
55 ; which indicates that the add's location doesn't spill over unto the
66 ; divide.
77
8 ; CHECK: Ltmp
9 ; CHECK: movl %edx, %r8d
10 ; CHECK-NEXT: leal (%rdi,%rsi), %eax
8 ; CHECK: leal (%rdi,%rsi), %eax
119 ; CHECK-NEXT: Ltmp
1210 ; CHECK-NEXT: cltd
1311 ; CHECK-NEXT: idivl %r8d
432432 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
433433 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
434434 << (*Memo.PhysRegs)[i] << "), "
435 << "MRI.getRegClass(Op" << i << "));\n";
435 << "MRI.getRegClass(Op" << i << "), DL);\n";
436436 }
437437
438438 OS << " return FastEmitInst_";
526526 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
527527 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
528528 << (*Memo.PhysRegs)[i] << "), "
529 << "MRI.getRegClass(Op" << i << "));\n";
529 << "MRI.getRegClass(Op" << i << "), DL);\n";
530530 }
531531
532532 OS << " return FastEmitInst_";