llvm.org GIT mirror llvm / 33dd96a
This patch completely replaces the scheduling information for the SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target. The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information. Please note that the patch extensively affects the X86 MC instr scheduling for SNB. Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX. The updated and extended information about each instruction includes the following details: •static latency of the instruction •number of uOps from which the instruction consists of •all ports used by the instruction's' uOPs For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5: def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { let Latency = 9; let NumMicroOps = 6; let ResourceCycles = [1,2,2,1]; } def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>; Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script. Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb Differential Revision: https://reviews.llvm.org/D35019#inline-304691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307529 91177308-0d34-0410-b5e6-96231b3b80d8 Gadi Haber 2 years ago
13 changed file(s) with 3342 addition(s) and 930 deletion(s). Raw diff Collapse all Expand all
2323 // Based on the LSD (loop-stream detector) queue size.
2424 let LoopMicroOpBufferSize = 28;
2525
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
26 // This flag is set to allow the scheduler to assign
27 // a default model to unrecognized opcodes.
2828 let CompleteModel = 0;
2929 }
3030
4747 def SBPort4 : ProcResource<1>;
4848
4949 // Many micro-ops are capable of issuing on multiple ports.
50 def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
5051 def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>;
5152 def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
5253 def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
114115 // Scalar and vector floating point.
115116 defm : SBWriteResPair;
116117 defm : SBWriteResPair;
117 defm : SBWriteResPair12>; // 10-14 cycles.
118 defm : SBWriteResPair24>;
118119 defm : SBWriteResPair;
119120 defm : SBWriteResPair;
120 defm : SBWriteResPair5>;
121 defm : SBWriteResPair4>;
121122 defm : SBWriteResPair;
122123 defm : SBWriteResPair;
123124 defm : SBWriteResPair;
133134 }
134135
135136 // Vector integer operations.
136 defm : SBWriteResPair;
137 defm : SBWriteResPair;
138 defm : SBWriteResPairALU, SBPort15, 1>;
137 defm : SBWriteResPairShift, SBPort5, 1>;
138 defm : SBWriteResPair;
139 defm : SBWriteResPair;
139140 defm : SBWriteResPair;
140 defm : SBWriteResPair15, 1>;
141 defm : SBWriteResPair5, 1>;
141142 defm : SBWriteResPair;
142143 def : WriteRes {
143144 let Latency = 2;
147148 let Latency = 6;
148149 let ResourceCycles = [1, 1, 1];
149150 }
150 def : WriteRes {
151 let Latency = 6;
152 let ResourceCycles = [1, 1, 1];
153 }
154 def : WriteRes {
155 let Latency = 6;
156 let ResourceCycles = [1, 1, 1, 1];
151 def : WriteRes {
152 let Latency = 5;
153 let NumMicroOps = 3;
154 let ResourceCycles = [1,2];
155 }
156 def : WriteRes {
157 let Latency = 11;
158 let NumMicroOps = 4;
159 let ResourceCycles = [1,1,2];
157160 }
158161
159162 ////////////////////////////////////////////////////////////////////////////////
203206 }
204207
205208 // Packed Compare Implicit Length Strings, Return Index
206 def : WriteRes {
207 let Latency = 3;
209 def : WriteRes {
210 let Latency = 11;
211 let NumMicroOps = 3;
208212 let ResourceCycles = [3];
209213 }
210 def : WriteRes {
211 let Latency = 3;
212 let ResourceCycles = [3, 1];
214 def : WriteRes {
215 let Latency = 17;
216 let NumMicroOps = 4;
217 let ResourceCycles = [3,1];
213218 }
214219
215220 // Packed Compare Explicit Length Strings, Return Index
223228 }
224229
225230 // AES Instructions.
226 def : WriteRes {
227 let Latency = 8;
231 def : WriteRes {
232 let Latency = 7;
233 let NumMicroOps = 2;
234 let ResourceCycles = [1,1];
235 }
236 def : WriteRes {
237 let Latency = 13;
238 let NumMicroOps = 3;
239 let ResourceCycles = [1,1,1];
240 }
241
242 def : WriteRes {
243 let Latency = 12;
244 let NumMicroOps = 2;
228245 let ResourceCycles = [2];
229246 }
230 def : WriteRes {
231 let Latency = 8;
232 let ResourceCycles = [2, 1];
233 }
234
235 def : WriteRes {
236 let Latency = 8;
237 let ResourceCycles = [2];
238 }
239 def : WriteRes {
240 let Latency = 8;
241 let ResourceCycles = [2, 1];
247 def : WriteRes {
248 let Latency = 18;
249 let NumMicroOps = 3;
250 let ResourceCycles = [2,1];
242251 }
243252
244253 def : WriteRes {
271280 defm : SBWriteResPair;
272281 defm : SBWriteResPair;
273282 defm : SBWriteResPair;
283
284 // Remaining SNB instrs.
285
286 def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
287 let Latency = 1;
288 let NumMicroOps = 1;
289 let ResourceCycles = [1];
290 }
291 def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>;
292 def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>;
293 def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>;
294 def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>;
295 def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>;
296 def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>;
297 def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>;
298 def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>;
299 def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>;
300 def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>;
301 def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>;
302 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>;
303 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>;
304 def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>;
305 def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>;
306 def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>;
307 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>;
308 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>;
309 def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>;
310 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>;
311 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>;
312 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>;
313 def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>;
314
315 def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
316 let Latency = 1;
317 let NumMicroOps = 1;
318 let ResourceCycles = [1];
319 }
320 def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r")>;
321 def: InstRW<[SBWriteResGroup1], (instregex "COM_FST0r")>;
322 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_FPr")>;
323 def: InstRW<[SBWriteResGroup1], (instregex "UCOM_Fr")>;
324
325 def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
326 let Latency = 1;
327 let NumMicroOps = 1;
328 let ResourceCycles = [1];
329 }
330 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>;
331 def: InstRW<[SBWriteResGroup2], (instregex "ANDNPSrr")>;
332 def: InstRW<[SBWriteResGroup2], (instregex "ANDPDrr")>;
333 def: InstRW<[SBWriteResGroup2], (instregex "ANDPSrr")>;
334 def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP")>;
335 def: InstRW<[SBWriteResGroup2], (instregex "FFREE")>;
336 def: InstRW<[SBWriteResGroup2], (instregex "FINCSTP")>;
337 def: InstRW<[SBWriteResGroup2], (instregex "FNOP")>;
338 def: InstRW<[SBWriteResGroup2], (instregex "INSERTPSrr")>;
339 def: InstRW<[SBWriteResGroup2], (instregex "JMP64r")>;
340 def: InstRW<[SBWriteResGroup2], (instregex "LD_Frr")>;
341 def: InstRW<[SBWriteResGroup2], (instregex "MOV64toPQIrr")>;
342 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPDrr")>;
343 def: InstRW<[SBWriteResGroup2], (instregex "MOVAPSrr")>;
344 def: InstRW<[SBWriteResGroup2], (instregex "MOVDDUPrr")>;
345 def: InstRW<[SBWriteResGroup2], (instregex "MOVDI2PDIrr")>;
346 def: InstRW<[SBWriteResGroup2], (instregex "MOVHLPSrr")>;
347 def: InstRW<[SBWriteResGroup2], (instregex "MOVLHPSrr")>;
348 def: InstRW<[SBWriteResGroup2], (instregex "MOVSDrr")>;
349 def: InstRW<[SBWriteResGroup2], (instregex "MOVSHDUPrr")>;
350 def: InstRW<[SBWriteResGroup2], (instregex "MOVSLDUPrr")>;
351 def: InstRW<[SBWriteResGroup2], (instregex "MOVSSrr")>;
352 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPDrr")>;
353 def: InstRW<[SBWriteResGroup2], (instregex "MOVUPSrr")>;
354 def: InstRW<[SBWriteResGroup2], (instregex "ORPDrr")>;
355 def: InstRW<[SBWriteResGroup2], (instregex "ORPSrr")>;
356 def: InstRW<[SBWriteResGroup2], (instregex "RETQ")>;
357 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPDrri")>;
358 def: InstRW<[SBWriteResGroup2], (instregex "SHUFPSrri")>;
359 def: InstRW<[SBWriteResGroup2], (instregex "ST_FPrr")>;
360 def: InstRW<[SBWriteResGroup2], (instregex "ST_Frr")>;
361 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPDrr")>;
362 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPSrr")>;
363 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPDrr")>;
364 def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPSrr")>;
365 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDYrr")>;
366 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDrr")>;
367 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSYrr")>;
368 def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSrr")>;
369 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>;
370 def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>;
371 def: InstRW<[SBWriteResGroup2], (instregex "VANDPSrr")>;
372 def: InstRW<[SBWriteResGroup2], (instregex "VEXTRACTF128rr")>;
373 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTF128rr")>;
374 def: InstRW<[SBWriteResGroup2], (instregex "VINSERTPSrr")>;
375 def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>;
376 def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>;
377 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDYrr")>;
378 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDrr")>;
379 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSYrr")>;
380 def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSrr")>;
381 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPYrr")>;
382 def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPrr")>;
383 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
384 def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>;
385 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSDrr")>;
386 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPYrr")>;
387 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPrr")>;
388 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPYrr")>;
389 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPrr")>;
390 def: InstRW<[SBWriteResGroup2], (instregex "VMOVSSrr")>;
391 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDYrr")>;
392 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDrr")>;
393 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSYrr")>;
394 def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSrr")>;
395 def: InstRW<[SBWriteResGroup2], (instregex "VORPDYrr")>;
396 def: InstRW<[SBWriteResGroup2], (instregex "VORPDrr")>;
397 def: InstRW<[SBWriteResGroup2], (instregex "VORPSYrr")>;
398 def: InstRW<[SBWriteResGroup2], (instregex "VORPSrr")>;
399 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDri")>;
400 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrm")>;
401 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrr")>;
402 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSri")>;
403 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrm")>;
404 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>;
405 def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>;
406 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDYrri")>;
407 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDrri")>;
408 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSYrri")>;
409 def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSrri")>;
410 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDrr")>;
411 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSrr")>;
412 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDYrr")>;
413 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDrr")>;
414 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSYrr")>;
415 def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSrr")>;
416 def: InstRW<[SBWriteResGroup2], (instregex "VXORPDrr")>;
417 def: InstRW<[SBWriteResGroup2], (instregex "VXORPSrr")>;
418 def: InstRW<[SBWriteResGroup2], (instregex "XORPDrr")>;
419 def: InstRW<[SBWriteResGroup2], (instregex "XORPSrr")>;
420
421 def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
422 let Latency = 1;
423 let NumMicroOps = 1;
424 let ResourceCycles = [1];
425 }
426 def: InstRW<[SBWriteResGroup3], (instregex "LEA64_32r")>;
427
428 def SBWriteResGroup4 : SchedWriteRes<[SBPort0]> {
429 let Latency = 1;
430 let NumMicroOps = 1;
431 let ResourceCycles = [1];
432 }
433 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri")>;
434 def: InstRW<[SBWriteResGroup4], (instregex "BLENDPSrri")>;
435 def: InstRW<[SBWriteResGroup4], (instregex "BT32ri8")>;
436 def: InstRW<[SBWriteResGroup4], (instregex "BT32rr")>;
437 def: InstRW<[SBWriteResGroup4], (instregex "BTC32ri8")>;
438 def: InstRW<[SBWriteResGroup4], (instregex "BTC32rr")>;
439 def: InstRW<[SBWriteResGroup4], (instregex "BTR32ri8")>;
440 def: InstRW<[SBWriteResGroup4], (instregex "BTR32rr")>;
441 def: InstRW<[SBWriteResGroup4], (instregex "BTS32ri8")>;
442 def: InstRW<[SBWriteResGroup4], (instregex "BTS32rr")>;
443 def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>;
444 def: InstRW<[SBWriteResGroup4], (instregex "CQO")>;
445 def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>;
446 def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>;
447 def: InstRW<[SBWriteResGroup4], (instregex "SAR32ri")>;
448 def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>;
449 def: InstRW<[SBWriteResGroup4], (instregex "SETAEr")>;
450 def: InstRW<[SBWriteResGroup4], (instregex "SETBr")>;
451 def: InstRW<[SBWriteResGroup4], (instregex "SETEr")>;
452 def: InstRW<[SBWriteResGroup4], (instregex "SETGEr")>;
453 def: InstRW<[SBWriteResGroup4], (instregex "SETGr")>;
454 def: InstRW<[SBWriteResGroup4], (instregex "SETLEr")>;
455 def: InstRW<[SBWriteResGroup4], (instregex "SETLr")>;
456 def: InstRW<[SBWriteResGroup4], (instregex "SETNEr")>;
457 def: InstRW<[SBWriteResGroup4], (instregex "SETNOr")>;
458 def: InstRW<[SBWriteResGroup4], (instregex "SETNPr")>;
459 def: InstRW<[SBWriteResGroup4], (instregex "SETNSr")>;
460 def: InstRW<[SBWriteResGroup4], (instregex "SETOr")>;
461 def: InstRW<[SBWriteResGroup4], (instregex "SETPr")>;
462 def: InstRW<[SBWriteResGroup4], (instregex "SETSr")>;
463 def: InstRW<[SBWriteResGroup4], (instregex "SHL32ri")>;
464 def: InstRW<[SBWriteResGroup4], (instregex "SHL64r1")>;
465 def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>;
466 def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>;
467 def: InstRW<[SBWriteResGroup4], (instregex "SHR32ri")>;
468 def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>;
469 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>;
470 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>;
471 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>;
472 def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSrri")>;
473 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQAYrr")>;
474 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQArr")>;
475 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUYrr")>;
476 def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUrr")>;
477
478 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
479 let Latency = 1;
480 let NumMicroOps = 1;
481 let ResourceCycles = [1];
482 }
483 def: InstRW<[SBWriteResGroup5], (instregex "KORTESTBrr")>;
484 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>;
485 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>;
486 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>;
487 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>;
488 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>;
489 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>;
490 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>;
491 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>;
492 def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>;
493 def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>;
494 def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>;
495 def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>;
496 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSDWrr")>;
497 def: InstRW<[SBWriteResGroup5], (instregex "PACKSSWBrr")>;
498 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSDWrr")>;
499 def: InstRW<[SBWriteResGroup5], (instregex "PACKUSWBrr")>;
500 def: InstRW<[SBWriteResGroup5], (instregex "PADDBrr")>;
501 def: InstRW<[SBWriteResGroup5], (instregex "PADDDrr")>;
502 def: InstRW<[SBWriteResGroup5], (instregex "PADDQrr")>;
503 def: InstRW<[SBWriteResGroup5], (instregex "PADDSBrr")>;
504 def: InstRW<[SBWriteResGroup5], (instregex "PADDSWrr")>;
505 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSBrr")>;
506 def: InstRW<[SBWriteResGroup5], (instregex "PADDUSWrr")>;
507 def: InstRW<[SBWriteResGroup5], (instregex "PADDWrr")>;
508 def: InstRW<[SBWriteResGroup5], (instregex "PALIGNRrri")>;
509 def: InstRW<[SBWriteResGroup5], (instregex "PAVGBrr")>;
510 def: InstRW<[SBWriteResGroup5], (instregex "PAVGWrr")>;
511 def: InstRW<[SBWriteResGroup5], (instregex "PBLENDWrri")>;
512 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQBrr")>;
513 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQDrr")>;
514 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQQrr")>;
515 def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQWrr")>;
516 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTBrr")>;
517 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTDrr")>;
518 def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTWrr")>;
519 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSBrr")>;
520 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSDrr")>;
521 def: InstRW<[SBWriteResGroup5], (instregex "PMAXSWrr")>;
522 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUBrr")>;
523 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUDrr")>;
524 def: InstRW<[SBWriteResGroup5], (instregex "PMAXUWrr")>;
525 def: InstRW<[SBWriteResGroup5], (instregex "PMINSBrr")>;
526 def: InstRW<[SBWriteResGroup5], (instregex "PMINSDrr")>;
527 def: InstRW<[SBWriteResGroup5], (instregex "PMINSWrr")>;
528 def: InstRW<[SBWriteResGroup5], (instregex "PMINUBrr")>;
529 def: InstRW<[SBWriteResGroup5], (instregex "PMINUDrr")>;
530 def: InstRW<[SBWriteResGroup5], (instregex "PMINUWrr")>;
531 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBDrr")>;
532 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBQrr")>;
533 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBWrr")>;
534 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXDQrr")>;
535 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWDrr")>;
536 def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWQrr")>;
537 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBDrr")>;
538 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBQrr")>;
539 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBWrr")>;
540 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXDQrr")>;
541 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWDrr")>;
542 def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWQrr")>;
543 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFBrr")>;
544 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>;
545 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>;
546 def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>;
547 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>;
548 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>;
549 def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>;
550 def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>;
551 def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>;
552 def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>;
553 def: InstRW<[SBWriteResGroup5], (instregex "PSUBDrr")>;
554 def: InstRW<[SBWriteResGroup5], (instregex "PSUBQrr")>;
555 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSBrr")>;
556 def: InstRW<[SBWriteResGroup5], (instregex "PSUBSWrr")>;
557 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSBrr")>;
558 def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSWrr")>;
559 def: InstRW<[SBWriteResGroup5], (instregex "PSUBWrr")>;
560 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHBWrr")>;
561 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHDQrr")>;
562 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHQDQrr")>;
563 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHWDrr")>;
564 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLBWrr")>;
565 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLDQrr")>;
566 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLQDQrr")>;
567 def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLWDrr")>;
568 def: InstRW<[SBWriteResGroup5], (instregex "VMASKMOVPSYrm")>;
569 def: InstRW<[SBWriteResGroup5], (instregex "VPABSBrr")>;
570 def: InstRW<[SBWriteResGroup5], (instregex "VPABSDrr")>;
571 def: InstRW<[SBWriteResGroup5], (instregex "VPABSWrr")>;
572 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSDWrr")>;
573 def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSWBrr")>;
574 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSDWrr")>;
575 def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSWBrr")>;
576 def: InstRW<[SBWriteResGroup5], (instregex "VPADDBrr")>;
577 def: InstRW<[SBWriteResGroup5], (instregex "VPADDDrr")>;
578 def: InstRW<[SBWriteResGroup5], (instregex "VPADDQrr")>;
579 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSBrr")>;
580 def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSWrr")>;
581 def: InstRW<[SBWriteResGroup5], (instregex "VPALIGNRrri")>;
582 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGBrr")>;
583 def: InstRW<[SBWriteResGroup5], (instregex "VPAVGWrr")>;
584 def: InstRW<[SBWriteResGroup5], (instregex "VPBLENDWrri")>;
585 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQBrr")>;
586 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQDrr")>;
587 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQWrr")>;
588 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTBrr")>;
589 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTDrr")>;
590 def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTWrr")>;
591 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSBrr")>;
592 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSDrr")>;
593 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSWrr")>;
594 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUBrr")>;
595 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUDrr")>;
596 def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUWrr")>;
597 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSBrr")>;
598 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSDrr")>;
599 def: InstRW<[SBWriteResGroup5], (instregex "VPMINSWrr")>;
600 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUBrr")>;
601 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUDrr")>;
602 def: InstRW<[SBWriteResGroup5], (instregex "VPMINUWrr")>;
603 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBDrr")>;
604 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBQrr")>;
605 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBWrr")>;
606 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXDQrr")>;
607 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWDrr")>;
608 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWQrr")>;
609 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBDrr")>;
610 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBQrr")>;
611 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBWrr")>;
612 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXDQrr")>;
613 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWDrr")>;
614 def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWQrr")>;
615 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFBrr")>;
616 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>;
617 def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>;
618 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>;
619 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>;
620 def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>;
621 def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>;
622 def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>;
623 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>;
624 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBDrr")>;
625 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBQrr")>;
626 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSBrr")>;
627 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSWrr")>;
628 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSBrr")>;
629 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSWrr")>;
630 def: InstRW<[SBWriteResGroup5], (instregex "VPSUBWrr")>;
631 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHBWrr")>;
632 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHDQrr")>;
633 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHWDrr")>;
634 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLDQrr")>;
635 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLQDQrr")>;
636 def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLWDrr")>;
637
638 def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
639 let Latency = 1;
640 let NumMicroOps = 1;
641 let ResourceCycles = [1];
642 }
643 def: InstRW<[SBWriteResGroup6], (instregex "ADD32ri8")>;
644 def: InstRW<[SBWriteResGroup6], (instregex "ADD32rr")>;
645 def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
646 def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
647 def: InstRW<[SBWriteResGroup6], (instregex "AND32ri")>;
648 def: InstRW<[SBWriteResGroup6], (instregex "AND64ri8")>;
649 def: InstRW<[SBWriteResGroup6], (instregex "AND64rr")>;
650 def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
651 def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
652 def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
653 def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
654 def: InstRW<[SBWriteResGroup6], (instregex "CMP16ri8")>;
655 def: InstRW<[SBWriteResGroup6], (instregex "CMP32i32")>;
656 def: InstRW<[SBWriteResGroup6], (instregex "CMP64rr")>;
657 def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
658 def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>;
659 def: InstRW<[SBWriteResGroup6], (instregex "CWDE")>;
660 def: InstRW<[SBWriteResGroup6], (instregex "DEC64r")>;
661 def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>;
662 def: InstRW<[SBWriteResGroup6], (instregex "INC64r")>;
663 def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>;
664 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
665 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
666 def: InstRW<[SBWriteResGroup6], (instregex "MOV32rr")>;
667 def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
668 def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>;
669 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
670 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
671 def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;
672 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr16")>;
673 def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr8")>;
674 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr16")>;
675 def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr8")>;
676 def: InstRW<[SBWriteResGroup6], (instregex "NEG64r")>;
677 def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
678 def: InstRW<[SBWriteResGroup6], (instregex "NOT64r")>;
679 def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
680 def: InstRW<[SBWriteResGroup6], (instregex "OR64ri8")>;
681 def: InstRW<[SBWriteResGroup6], (instregex "OR64rr")>;
682 def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
683 def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>;
684 def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>;
685 def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
686 def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
687 def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
688 def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
689 def: InstRW<[SBWriteResGroup6], (instregex "SUB64ri8")>;
690 def: InstRW<[SBWriteResGroup6], (instregex "SUB64rr")>;
691 def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
692 def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>;
693 def: InstRW<[SBWriteResGroup6], (instregex "TEST64rr")>;
694 def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
695 def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>;
696 def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
697 def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
698 def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
699 def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
700 def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
701 def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
702 def: InstRW<[SBWriteResGroup6], (instregex "XOR32rr")>;
703 def: InstRW<[SBWriteResGroup6], (instregex "XOR64ri8")>;
704 def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
705 def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>;
706
707 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
708 let Latency = 2;
709 let NumMicroOps = 1;
710 let ResourceCycles = [1];
711 }
712 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr")>;
713 def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPSrr")>;
714 def: InstRW<[SBWriteResGroup7], (instregex "MOVPDI2DIrr")>;
715 def: InstRW<[SBWriteResGroup7], (instregex "MOVPQIto64rr")>;
716 def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr")>;
717 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDYrr")>;
718 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDrr")>;
719 def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSrr")>;
720 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPDI2DIrr")>;
721 def: InstRW<[SBWriteResGroup7], (instregex "VMOVPQIto64rr")>;
722
723 def SBWriteResGroup9 : SchedWriteRes<[SBPort0]> {
724 let Latency = 2;
725 let NumMicroOps = 2;
726 let ResourceCycles = [2];
727 }
728 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>;
729 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>;
730 def: InstRW<[SBWriteResGroup9], (instregex "ROL32ri")>;
731 def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>;
732 def: InstRW<[SBWriteResGroup9], (instregex "ROR32ri")>;
733 def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>;
734 def: InstRW<[SBWriteResGroup9], (instregex "SETAr")>;
735 def: InstRW<[SBWriteResGroup9], (instregex "SETBEr")>;
736 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>;
737 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>;
738 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSYrr")>;
739 def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSrr")>;
740
741 def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> {
742 let Latency = 2;
743 let NumMicroOps = 2;
744 let ResourceCycles = [2];
745 }
746 def: InstRW<[SBWriteResGroup10], (instregex "VPBLENDVBrr")>;
747
748 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
749 let Latency = 2;
750 let NumMicroOps = 2;
751 let ResourceCycles = [2];
752 }
753 def: InstRW<[SBWriteResGroup11], (instregex "SCASB")>;
754 def: InstRW<[SBWriteResGroup11], (instregex "SCASL")>;
755 def: InstRW<[SBWriteResGroup11], (instregex "SCASQ")>;
756 def: InstRW<[SBWriteResGroup11], (instregex "SCASW")>;
757
758 def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
759 let Latency = 2;
760 let NumMicroOps = 2;
761 let ResourceCycles = [1,1];
762 }
763 def: InstRW<[SBWriteResGroup12], (instregex "COMISDrr")>;
764 def: InstRW<[SBWriteResGroup12], (instregex "COMISSrr")>;
765 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISDrr")>;
766 def: InstRW<[SBWriteResGroup12], (instregex "UCOMISSrr")>;
767 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISDrr")>;
768 def: InstRW<[SBWriteResGroup12], (instregex "VCOMISSrr")>;
769 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISDrr")>;
770 def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISSrr")>;
771
772 def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort5]> {
773 let Latency = 2;
774 let NumMicroOps = 2;
775 let ResourceCycles = [1,1];
776 }
777 def: InstRW<[SBWriteResGroup13], (instregex "CVTPS2PDrr")>;
778 def: InstRW<[SBWriteResGroup13], (instregex "PTESTrr")>;
779 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDYrr")>;
780 def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDrr")>;
781 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTYrr")>;
782 def: InstRW<[SBWriteResGroup13], (instregex "VPTESTrr")>;
783
784 def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> {
785 let Latency = 2;
786 let NumMicroOps = 2;
787 let ResourceCycles = [1,1];
788 }
789 def: InstRW<[SBWriteResGroup14], (instregex "PSLLDrr")>;
790 def: InstRW<[SBWriteResGroup14], (instregex "PSLLQrr")>;
791 def: InstRW<[SBWriteResGroup14], (instregex "PSLLWrr")>;
792 def: InstRW<[SBWriteResGroup14], (instregex "PSRADrr")>;
793 def: InstRW<[SBWriteResGroup14], (instregex "PSRAWrr")>;
794 def: InstRW<[SBWriteResGroup14], (instregex "PSRLDrr")>;
795 def: InstRW<[SBWriteResGroup14], (instregex "PSRLQrr")>;
796 def: InstRW<[SBWriteResGroup14], (instregex "PSRLWrr")>;
797 def: InstRW<[SBWriteResGroup14], (instregex "VPSRADrr")>;
798 def: InstRW<[SBWriteResGroup14], (instregex "VPSRAWrr")>;
799 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLDrr")>;
800 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLQrr")>;
801 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLWrr")>;
802
803 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
804 let Latency = 2;
805 let NumMicroOps = 2;
806 let ResourceCycles = [1,1];
807 }
808 def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
809
810 def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort0]> {
811 let Latency = 2;
812 let NumMicroOps = 2;
813 let ResourceCycles = [1,1];
814 }
815 def: InstRW<[SBWriteResGroup16], (instregex "BSWAP32r")>;
816
817 def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> {
818 let Latency = 2;
819 let NumMicroOps = 2;
820 let ResourceCycles = [1,1];
821 }
822 def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr")>;
823 def: InstRW<[SBWriteResGroup17], (instregex "PINSRDrr")>;
824 def: InstRW<[SBWriteResGroup17], (instregex "PINSRQrr")>;
825 def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrri")>;
826 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRBrr")>;
827 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRDrr")>;
828 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRQrr")>;
829 def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrri")>;
830
831 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
832 let Latency = 2;
833 let NumMicroOps = 2;
834 let ResourceCycles = [1,1];
835 }
836 def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
837
838 def SBWriteResGroup19 : SchedWriteRes<[SBPort0,SBPort015]> {
839 let Latency = 2;
840 let NumMicroOps = 2;
841 let ResourceCycles = [1,1];
842 }
843 def: InstRW<[SBWriteResGroup19], (instregex "ADC64ri8")>;
844 def: InstRW<[SBWriteResGroup19], (instregex "ADC64rr")>;
845 def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
846 def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
847 def: InstRW<[SBWriteResGroup19], (instregex "CMOVAE32rr")>;
848 def: InstRW<[SBWriteResGroup19], (instregex "CMOVB32rr")>;
849 def: InstRW<[SBWriteResGroup19], (instregex "CMOVE32rr")>;
850 def: InstRW<[SBWriteResGroup19], (instregex "CMOVG32rr")>;
851 def: InstRW<[SBWriteResGroup19], (instregex "CMOVGE32rr")>;
852 def: InstRW<[SBWriteResGroup19], (instregex "CMOVL32rr")>;
853 def: InstRW<[SBWriteResGroup19], (instregex "CMOVLE32rr")>;
854 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNE32rr")>;
855 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNO32rr")>;
856 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNP32rr")>;
857 def: InstRW<[SBWriteResGroup19], (instregex "CMOVNS32rr")>;
858 def: InstRW<[SBWriteResGroup19], (instregex "CMOVO32rr")>;
859 def: InstRW<[SBWriteResGroup19], (instregex "CMOVP32rr")>;
860 def: InstRW<[SBWriteResGroup19], (instregex "CMOVS32rr")>;
861 def: InstRW<[SBWriteResGroup19], (instregex "SBB32rr")>;
862 def: InstRW<[SBWriteResGroup19], (instregex "SBB64ri8")>;
863 def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
864 def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
865 def: InstRW<[SBWriteResGroup19], (instregex "SHLD32rri8")>;
866 def: InstRW<[SBWriteResGroup19], (instregex "SHRD32rri8")>;
867
868 def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
869 let Latency = 3;
870 let NumMicroOps = 1;
871 let ResourceCycles = [1];
872 }
873 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr64")>;
874 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr64")>;
875 def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULUDQirr")>;
876 def: InstRW<[SBWriteResGroup20], (instregex "PMADDUBSWrr")>;
877 def: InstRW<[SBWriteResGroup20], (instregex "PMADDWDrr")>;
878 def: InstRW<[SBWriteResGroup20], (instregex "PMULDQrr")>;
879 def: InstRW<[SBWriteResGroup20], (instregex "PMULHRSWrr")>;
880 def: InstRW<[SBWriteResGroup20], (instregex "PMULHUWrr")>;
881 def: InstRW<[SBWriteResGroup20], (instregex "PMULHWrr")>;
882 def: InstRW<[SBWriteResGroup20], (instregex "PMULLDrr")>;
883 def: InstRW<[SBWriteResGroup20], (instregex "PMULLWrr")>;
884 def: InstRW<[SBWriteResGroup20], (instregex "PMULUDQrr")>;
885 def: InstRW<[SBWriteResGroup20], (instregex "PSADBWrr")>;
886 def: InstRW<[SBWriteResGroup20], (instregex "VMOVMSKPSYrr")>;
887 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDUBSWrr")>;
888 def: InstRW<[SBWriteResGroup20], (instregex "VPMADDWDrr")>;
889 def: InstRW<[SBWriteResGroup20], (instregex "VPMULDQrr")>;
890 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHRSWrr")>;
891 def: InstRW<[SBWriteResGroup20], (instregex "VPMULHWrr")>;
892 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLDrr")>;
893 def: InstRW<[SBWriteResGroup20], (instregex "VPMULLWrr")>;
894 def: InstRW<[SBWriteResGroup20], (instregex "VPSADBWrr")>;
895
896 def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
897 let Latency = 3;
898 let NumMicroOps = 1;
899 let ResourceCycles = [1];
900 }
901 def: InstRW<[SBWriteResGroup21], (instregex "ADDPDrr")>;
902 def: InstRW<[SBWriteResGroup21], (instregex "ADDPSrr")>;
903 def: InstRW<[SBWriteResGroup21], (instregex "ADDSDrr")>;
904 def: InstRW<[SBWriteResGroup21], (instregex "ADDSSrr")>;
905 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPDrr")>;
906 def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPSrr")>;
907 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0")>;
908 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FST0r")>;
909 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FrST0")>;
910 def: InstRW<[SBWriteResGroup21], (instregex "BSF32rr")>;
911 def: InstRW<[SBWriteResGroup21], (instregex "BSR32rr")>;
912 def: InstRW<[SBWriteResGroup21], (instregex "CMPPDrri")>;
913 def: InstRW<[SBWriteResGroup21], (instregex "CMPPSrri")>;
914 def: InstRW<[SBWriteResGroup21], (instregex "CMPSDrr")>;
915 def: InstRW<[SBWriteResGroup21], (instregex "CMPSSrr")>;
916 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r32")>;
917 def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r8")>;
918 def: InstRW<[SBWriteResGroup21], (instregex "CVTDQ2PSrr")>;
919 def: InstRW<[SBWriteResGroup21], (instregex "CVTPS2DQrr")>;
920 def: InstRW<[SBWriteResGroup21], (instregex "CVTTPS2DQrr")>;
921 def: InstRW<[SBWriteResGroup21], (instregex "MAXPDrr")>;
922 def: InstRW<[SBWriteResGroup21], (instregex "MAXPSrr")>;
923 def: InstRW<[SBWriteResGroup21], (instregex "MAXSDrr")>;
924 def: InstRW<[SBWriteResGroup21], (instregex "MAXSSrr")>;
925 def: InstRW<[SBWriteResGroup21], (instregex "MINPDrr")>;
926 def: InstRW<[SBWriteResGroup21], (instregex "MINPSrr")>;
927 def: InstRW<[SBWriteResGroup21], (instregex "MINSDrr")>;
928 def: InstRW<[SBWriteResGroup21], (instregex "MINSSrr")>;
929 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr")>;
930 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPS2PIirr")>;
931 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTTPS2PIirr")>;
932 def: InstRW<[SBWriteResGroup21], (instregex "MUL8r")>;
933 def: InstRW<[SBWriteResGroup21], (instregex "POPCNT32rr")>;
934 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPDr")>;
935 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPSr")>;
936 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSDr")>;
937 def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSSr")>;
938 def: InstRW<[SBWriteResGroup21], (instregex "SUBPDrr")>;
939 def: InstRW<[SBWriteResGroup21], (instregex "SUBPSrr")>;
940 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FPrST0")>;
941 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FST0r")>;
942 def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FrST0")>;
943 def: InstRW<[SBWriteResGroup21], (instregex "SUBSDrr")>;
944 def: InstRW<[SBWriteResGroup21], (instregex "SUBSSrr")>;
945 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FPrST0")>;
946 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FST0r")>;
947 def: InstRW<[SBWriteResGroup21], (instregex "SUB_FrST0")>;
948 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDYrr")>;
949 def: InstRW<[SBWriteResGroup21], (instregex "VADDPDrr")>;
950 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSYrr")>;
951 def: InstRW<[SBWriteResGroup21], (instregex "VADDPSrr")>;
952 def: InstRW<[SBWriteResGroup21], (instregex "VADDSDrr")>;
953 def: InstRW<[SBWriteResGroup21], (instregex "VADDSSrr")>;
954 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDYrr")>;
955 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDrr")>;
956 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSYrr")>;
957 def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSrr")>;
958 def: InstRW<[SBWriteResGroup21], (instregex "VBROADCASTF128")>;
959 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDYrri")>;
960 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDrri")>;
961 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSYrri")>;
962 def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSrri")>;
963 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSDrr")>;
964 def: InstRW<[SBWriteResGroup21], (instregex "VCMPSSrr")>;
965 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSYrr")>;
966 def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSrr")>;
967 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQYrr")>;
968 def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQrr")>;
969 def: InstRW<[SBWriteResGroup21], (instregex "VCVTTPS2DQrr")>;
970 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDYrr")>;
971 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDrr")>;
972 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSYrr")>;
973 def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSrr")>;
974 def: InstRW<[SBWriteResGroup21], (instregex "VMAXSDrr")>;
975 def: InstRW<[SBWriteResGroup21], (instregex "VMAXSSrr")>;
976 def: InstRW<[SBWriteResGroup21], (instregex "VMINPDrr")>;
977 def: InstRW<[SBWriteResGroup21], (instregex "VMINPSrr")>;
978 def: InstRW<[SBWriteResGroup21], (instregex "VMINSDrr")>;
979 def: InstRW<[SBWriteResGroup21], (instregex "VMINSSrr")>;
980 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPDr")>;
981 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPSr")>;
982 def: InstRW<[SBWriteResGroup21], (instregex "VROUNDSDr")>;
983 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDYrr")>;
984 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDrr")>;
985 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSYrr")>;
986 def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSrr")>;
987
988 def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
989 let Latency = 3;
990 let NumMicroOps = 2;
991 let ResourceCycles = [1,1];
992 }
993 def: InstRW<[SBWriteResGroup22], (instregex "EXTRACTPSrr")>;
994 def: InstRW<[SBWriteResGroup22], (instregex "VEXTRACTPSrr")>;
995
996 def SBWriteResGroup23 : SchedWriteRes<[SBPort0,SBPort15]> {
997 let Latency = 3;
998 let NumMicroOps = 2;
999 let ResourceCycles = [1,1];
1000 }
1001 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr")>;
1002 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRDrr")>;
1003 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRQrr")>;
1004 def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWri")>;
1005 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRBrr")>;
1006 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRDrr")>;
1007 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRQrr")>;
1008 def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWri")>;
1009 def: InstRW<[SBWriteResGroup23], (instregex "SHL64rCL")>;
1010 def: InstRW<[SBWriteResGroup23], (instregex "SHL8rCL")>;
1011
1012 def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
1013 let Latency = 3;
1014 let NumMicroOps = 3;
1015 let ResourceCycles = [3];
1016 }
1017 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr64")>;
1018 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr64")>;
1019 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr64")>;
1020 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr64")>;
1021 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr64")>;
1022 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr64")>;
1023 def: InstRW<[SBWriteResGroup24], (instregex "PHADDDrr")>;
1024 def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr128")>;
1025 def: InstRW<[SBWriteResGroup24], (instregex "PHADDWrr")>;
1026 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBDrr")>;
1027 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr128")>;
1028 def: InstRW<[SBWriteResGroup24], (instregex "PHSUBWrr")>;
1029 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDDrr")>;
1030 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr128")>;
1031 def: InstRW<[SBWriteResGroup24], (instregex "VPHADDWrr")>;
1032 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBDrr")>;
1033 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr128")>;
1034 def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBWrr")>;
1035
1036 def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> {
1037 let Latency = 3;
1038 let NumMicroOps = 3;
1039 let ResourceCycles = [3];
1040 }
1041 def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>;
1042 def: InstRW<[SBWriteResGroup25], (instregex "XADD32rr")>;
1043 def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>;
1044
1045 def SBWriteResGroup26 : SchedWriteRes<[SBPort0,SBPort015]> {
1046 let Latency = 3;
1047 let NumMicroOps = 3;
1048 let ResourceCycles = [2,1];
1049 }
1050 def: InstRW<[SBWriteResGroup26], (instregex "CMOVA32rr")>;
1051 def: InstRW<[SBWriteResGroup26], (instregex "CMOVBE32rr")>;
1052
1053 def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
1054 let Latency = 4;
1055 let NumMicroOps = 2;
1056 let ResourceCycles = [1,1];
1057 }
1058 def: InstRW<[SBWriteResGroup27], (instregex "MUL64r")>;
1059
1060 def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> {
1061 let Latency = 4;
1062 let NumMicroOps = 2;
1063 let ResourceCycles = [1,1];
1064 }
1065 def: InstRW<[SBWriteResGroup28], (instregex "CVTDQ2PDrr")>;
1066 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2DQrr")>;
1067 def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2PSrr")>;
1068 def: InstRW<[SBWriteResGroup28], (instregex "CVTSD2SSrr")>;
1069 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SD64rr")>;
1070 def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SDrr")>;
1071 def: InstRW<[SBWriteResGroup28], (instregex "CVTTPD2DQrr")>;
1072 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr")>;
1073 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr")>;
1074 def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTTPD2PIirr")>;
1075 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDYrr")>;
1076 def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDrr")>;
1077 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQYrr")>;
1078 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQrr")>;
1079 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSYrr")>;
1080 def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSrr")>;
1081 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SD64rr")>;
1082 def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SDrr")>;
1083 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQYrr")>;
1084 def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQrr")>;
1085
1086 def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
1087 let Latency = 4;
1088 let NumMicroOps = 2;
1089 let ResourceCycles = [1,1];
1090 }
1091 def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
1092 def: InstRW<[SBWriteResGroup29], (instregex "PAUSE")>;
1093
1094 def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> {
1095 let Latency = 5;
1096 let NumMicroOps = 1;
1097 let ResourceCycles = [1];
1098 }
1099 def: InstRW<[SBWriteResGroup30], (instregex "MULPDrr")>;
1100 def: InstRW<[SBWriteResGroup30], (instregex "MULPSrr")>;
1101 def: InstRW<[SBWriteResGroup30], (instregex "MULSDrr")>;
1102 def: InstRW<[SBWriteResGroup30], (instregex "MULSSrr")>;
1103 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0")>;
1104 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FST0r")>;
1105 def: InstRW<[SBWriteResGroup30], (instregex "MUL_FrST0")>;
1106 def: InstRW<[SBWriteResGroup30], (instregex "PCMPGTQrr")>;
1107 def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr128")>;
1108 def: InstRW<[SBWriteResGroup30], (instregex "RCPPSr")>;
1109 def: InstRW<[SBWriteResGroup30], (instregex "RCPSSr")>;
1110 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTPSr")>;
1111 def: InstRW<[SBWriteResGroup30], (instregex "RSQRTSSr")>;
1112 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDYrr")>;
1113 def: InstRW<[SBWriteResGroup30], (instregex "VMULPDrr")>;
1114 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSYrr")>;
1115 def: InstRW<[SBWriteResGroup30], (instregex "VMULPSrr")>;
1116 def: InstRW<[SBWriteResGroup30], (instregex "VMULSDrr")>;
1117 def: InstRW<[SBWriteResGroup30], (instregex "VMULSSrr")>;
1118 def: InstRW<[SBWriteResGroup30], (instregex "VPCMPGTQrr")>;
1119 def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr128")>;
1120 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTPSr")>;
1121 def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTSSr")>;
1122
1123 def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
1124 let Latency = 5;
1125 let NumMicroOps = 1;
1126 let ResourceCycles = [1];
1127 }
1128 def: InstRW<[SBWriteResGroup31], (instregex "MOV32rm")>;
1129 def: InstRW<[SBWriteResGroup31], (instregex "MOV8rm")>;
1130 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm16")>;
1131 def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm8")>;
1132 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm16")>;
1133 def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm8")>;
1134 def: InstRW<[SBWriteResGroup31], (instregex "PREFETCH")>;
1135
1136 def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
1137 let Latency = 5;
1138 let NumMicroOps = 2;
1139 let ResourceCycles = [1,1];
1140 }
1141 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SI64rr")>;
1142 def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SIrr")>;
1143 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SI64rr")>;
1144 def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SIrr")>;
1145 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SI64rr")>;
1146 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SIrr")>;
1147 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SI64rr")>;
1148 def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SIrr")>;
1149 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSD2SI64rr")>;
1150 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SI64rr")>;
1151 def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SIrr")>;
1152 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SI64rr")>;
1153 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SIrr")>;
1154 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SI64rr")>;
1155 def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SIrr")>;
1156
1157 def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
1158 let Latency = 5;
1159 let NumMicroOps = 2;
1160 let ResourceCycles = [1,1];
1161 }
1162 def: InstRW<[SBWriteResGroup33], (instregex "MOV64mr")>;
1163 def: InstRW<[SBWriteResGroup33], (instregex "MOV8mr")>;
1164 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPDmr")>;
1165 def: InstRW<[SBWriteResGroup33], (instregex "MOVAPSmr")>;
1166 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQAmr")>;
1167 def: InstRW<[SBWriteResGroup33], (instregex "MOVDQUmr")>;
1168 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPDmr")>;
1169 def: InstRW<[SBWriteResGroup33], (instregex "MOVHPSmr")>;
1170 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPDmr")>;
1171 def: InstRW<[SBWriteResGroup33], (instregex "MOVLPSmr")>;
1172 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTDQmr")>;
1173 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTI_64mr")>;
1174 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTImr")>;
1175 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPDmr")>;
1176 def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPSmr")>;
1177 def: InstRW<[SBWriteResGroup33], (instregex "MOVPDI2DImr")>;
1178 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQI2QImr")>;
1179 def: InstRW<[SBWriteResGroup33], (instregex "MOVPQIto64mr")>;
1180 def: InstRW<[SBWriteResGroup33], (instregex "MOVSSmr")>;
1181 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPDmr")>;
1182 def: InstRW<[SBWriteResGroup33], (instregex "MOVUPSmr")>;
1183 def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8")>;
1184 def: InstRW<[SBWriteResGroup33], (instregex "PUSH64r")>;
1185 def: InstRW<[SBWriteResGroup33], (instregex "VEXTRACTF128mr")>;
1186 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDYmr")>;
1187 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDmr")>;
1188 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSYmr")>;
1189 def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSmr")>;
1190 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAYmr")>;
1191 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAmr")>;
1192 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUYmr")>;
1193 def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUmr")>;
1194 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPDmr")>;
1195 def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPSmr")>;
1196 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPDmr")>;
1197 def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPSmr")>;
1198 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQYmr")>;
1199 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQmr")>;
1200 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDYmr")>;
1201 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDmr")>;
1202 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSYmr")>;
1203 def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSmr")>;
1204 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPDI2DImr")>;
1205 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQI2QImr")>;
1206 def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQIto64mr")>;
1207 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSDmr")>;
1208 def: InstRW<[SBWriteResGroup33], (instregex "VMOVSSmr")>;
1209 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDYmr")>;
1210 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDmr")>;
1211 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSYmr")>;
1212 def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSmr")>;
1213
1214 def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> {
1215 let Latency = 5;
1216 let NumMicroOps = 3;
1217 let ResourceCycles = [1,2];
1218 }
1219 def: InstRW<[SBWriteResGroup34], (instregex "MPSADBWrri")>;
1220 def: InstRW<[SBWriteResGroup34], (instregex "VMPSADBWrri")>;
1221
1222 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
1223 let Latency = 5;
1224 let NumMicroOps = 3;
1225 let ResourceCycles = [1,2];
1226 }
1227 def: InstRW<[SBWriteResGroup35], (instregex "CLI")>;
1228 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SS64rr")>;
1229 def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SSrr")>;
1230 def: InstRW<[SBWriteResGroup35], (instregex "HADDPDrr")>;
1231 def: InstRW<[SBWriteResGroup35], (instregex "HADDPSrr")>;
1232 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPDrr")>;
1233 def: InstRW<[SBWriteResGroup35], (instregex "HSUBPSrr")>;
1234 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SS64rr")>;
1235 def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SSrr")>;
1236 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPDrr")>;
1237 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSYrr")>;
1238 def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSrr")>;
1239 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDYrr")>;
1240 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDrr")>;
1241 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSYrr")>;
1242 def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSrr")>;
1243
1244 def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1245 let Latency = 5;
1246 let NumMicroOps = 3;
1247 let ResourceCycles = [1,1,1];
1248 }
1249 def: InstRW<[SBWriteResGroup36], (instregex "CALL64r")>;
1250 def: InstRW<[SBWriteResGroup36], (instregex "EXTRACTPSmr")>;
1251 def: InstRW<[SBWriteResGroup36], (instregex "VEXTRACTPSmr")>;
1252
1253 def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> {
1254 let Latency = 5;
1255 let NumMicroOps = 3;
1256 let ResourceCycles = [1,1,1];
1257 }
1258 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDYrm")>;
1259 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDmr")>;
1260 def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPSmr")>;
1261
1262 def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1263 let Latency = 5;
1264 let NumMicroOps = 3;
1265 let ResourceCycles = [1,1,1];
1266 }
1267 def: InstRW<[SBWriteResGroup38], (instregex "SETAEm")>;
1268 def: InstRW<[SBWriteResGroup38], (instregex "SETBm")>;
1269 def: InstRW<[SBWriteResGroup38], (instregex "SETEm")>;
1270 def: InstRW<[SBWriteResGroup38], (instregex "SETGEm")>;
1271 def: InstRW<[SBWriteResGroup38], (instregex "SETGm")>;
1272 def: InstRW<[SBWriteResGroup38], (instregex "SETLEm")>;
1273 def: InstRW<[SBWriteResGroup38], (instregex "SETLm")>;
1274 def: InstRW<[SBWriteResGroup38], (instregex "SETNEm")>;
1275 def: InstRW<[SBWriteResGroup38], (instregex "SETNOm")>;
1276 def: InstRW<[SBWriteResGroup38], (instregex "SETNPm")>;
1277 def: InstRW<[SBWriteResGroup38], (instregex "SETNSm")>;
1278 def: InstRW<[SBWriteResGroup38], (instregex "SETOm")>;
1279 def: InstRW<[SBWriteResGroup38], (instregex "SETPm")>;
1280 def: InstRW<[SBWriteResGroup38], (instregex "SETSm")>;
1281
1282 def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> {
1283 let Latency = 5;
1284 let NumMicroOps = 3;
1285 let ResourceCycles = [1,1,1];
1286 }
1287 def: InstRW<[SBWriteResGroup39], (instregex "PEXTRBmr")>;
1288 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRBmr")>;
1289 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRDmr")>;
1290 def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRWmr")>;
1291
1292 def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1293 let Latency = 5;
1294 let NumMicroOps = 3;
1295 let ResourceCycles = [1,1,1];
1296 }
1297 def: InstRW<[SBWriteResGroup40], (instregex "MOV8mi")>;
1298 def: InstRW<[SBWriteResGroup40], (instregex "STOSB")>;
1299 def: InstRW<[SBWriteResGroup40], (instregex "STOSL")>;
1300 def: InstRW<[SBWriteResGroup40], (instregex "STOSQ")>;
1301 def: InstRW<[SBWriteResGroup40], (instregex "STOSW")>;
1302
1303 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
1304 let Latency = 5;
1305 let NumMicroOps = 4;
1306 let ResourceCycles = [1,3];
1307 }
1308 def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>;
1309
1310 def SBWriteResGroup42 : SchedWriteRes<[SBPort0,SBPort015]> {
1311 let Latency = 5;
1312 let NumMicroOps = 4;
1313 let ResourceCycles = [1,3];
1314 }
1315 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG32rr")>;
1316 def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG8rr")>;
1317
1318 def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1319 let Latency = 5;
1320 let NumMicroOps = 4;
1321 let ResourceCycles = [1,1,2];
1322 }
1323 def: InstRW<[SBWriteResGroup43], (instregex "SETAm")>;
1324 def: InstRW<[SBWriteResGroup43], (instregex "SETBEm")>;
1325
1326 def SBWriteResGroup44 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> {
1327 let Latency = 5;
1328 let NumMicroOps = 4;
1329 let ResourceCycles = [1,1,1,1];
1330 }
1331 def: InstRW<[SBWriteResGroup44], (instregex "LDMXCSR")>;
1332 def: InstRW<[SBWriteResGroup44], (instregex "STMXCSR")>;
1333 def: InstRW<[SBWriteResGroup44], (instregex "VLDMXCSR")>;
1334 def: InstRW<[SBWriteResGroup44], (instregex "VSTMXCSR")>;
1335
1336 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
1337 let Latency = 5;
1338 let NumMicroOps = 4;
1339 let ResourceCycles = [1,1,1,1];
1340 }
1341 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRDmr")>;
1342 def: InstRW<[SBWriteResGroup45], (instregex "PEXTRQmr")>;
1343 def: InstRW<[SBWriteResGroup45], (instregex "VPEXTRQmr")>;
1344 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF16")>;
1345 def: InstRW<[SBWriteResGroup45], (instregex "PUSHF64")>;
1346
1347 def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1348 let Latency = 5;
1349 let NumMicroOps = 4;
1350 let ResourceCycles = [1,1,1,1];
1351 }
1352 def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
1353
1354 def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
1355 let Latency = 5;
1356 let NumMicroOps = 5;
1357 let ResourceCycles = [1,2,1,1];
1358 }
1359 def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
1360
1361 def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
1362 let Latency = 6;
1363 let NumMicroOps = 1;
1364 let ResourceCycles = [1];
1365 }
1366 def: InstRW<[SBWriteResGroup48], (instregex "LDDQUrm")>;
1367 def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm")>;
1368 def: InstRW<[SBWriteResGroup48], (instregex "MOV64toPQIrm")>;
1369 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPDrm")>;
1370 def: InstRW<[SBWriteResGroup48], (instregex "MOVAPSrm")>;
1371 def: InstRW<[SBWriteResGroup48], (instregex "MOVDDUPrm")>;
1372 def: InstRW<[SBWriteResGroup48], (instregex "MOVDI2PDIrm")>;
1373 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQArm")>;
1374 def: InstRW<[SBWriteResGroup48], (instregex "MOVDQUrm")>;
1375 def: InstRW<[SBWriteResGroup48], (instregex "MOVNTDQArm")>;
1376 def: InstRW<[SBWriteResGroup48], (instregex "MOVSHDUPrm")>;
1377 def: InstRW<[SBWriteResGroup48], (instregex "MOVSLDUPrm")>;
1378 def: InstRW<[SBWriteResGroup48], (instregex "MOVSSrm")>;
1379 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPDrm")>;
1380 def: InstRW<[SBWriteResGroup48], (instregex "MOVUPSrm")>;
1381 def: InstRW<[SBWriteResGroup48], (instregex "POP64r")>;
1382 def: InstRW<[SBWriteResGroup48], (instregex "VBROADCASTSSrm")>;
1383 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUYrm")>;
1384 def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUrm")>;
1385 def: InstRW<[SBWriteResGroup48], (instregex "VMOV64toPQIrm")>;
1386 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPDrm")>;
1387 def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPSrm")>;
1388 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDDUPrm")>;
1389 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDI2PDIrm")>;
1390 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQArm")>;
1391 def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQUrm")>;
1392 def: InstRW<[SBWriteResGroup48], (instregex "VMOVNTDQArm")>;
1393 def: InstRW<[SBWriteResGroup48], (instregex "VMOVQI2PQIrm")>;
1394 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSDrm")>;
1395 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSHDUPrm")>;
1396 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSLDUPrm")>;
1397 def: InstRW<[SBWriteResGroup48], (instregex "VMOVSSrm")>;
1398 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPDrm")>;
1399 def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPSrm")>;
1400
1401 def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
1402 let Latency = 6;
1403 let NumMicroOps = 2;
1404 let ResourceCycles = [1,1];
1405 }
1406 def: InstRW<[SBWriteResGroup49], (instregex "JMP64m")>;
1407 def: InstRW<[SBWriteResGroup49], (instregex "MOV64sm")>;
1408
1409 def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort0]> {
1410 let Latency = 6;
1411 let NumMicroOps = 2;
1412 let ResourceCycles = [1,1];
1413 }
1414 def: InstRW<[SBWriteResGroup50], (instregex "BT64mi8")>;
1415
1416 def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
1417 let Latency = 6;
1418 let NumMicroOps = 2;
1419 let ResourceCycles = [1,1];
1420 }
1421 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm64")>;
1422 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm64")>;
1423 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm64")>;
1424 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNR64irm")>;
1425 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm64")>;
1426 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm64")>;
1427 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm64")>;
1428 def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm64")>;
1429
1430 def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
1431 let Latency = 6;
1432 let NumMicroOps = 2;
1433 let ResourceCycles = [1,1];
1434 }
1435 def: InstRW<[SBWriteResGroup52], (instregex "ADD64rm")>;
1436 def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
1437 def: InstRW<[SBWriteResGroup52], (instregex "AND64rm")>;
1438 def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
1439 def: InstRW<[SBWriteResGroup52], (instregex "CMP64mi8")>;
1440 def: InstRW<[SBWriteResGroup52], (instregex "CMP64mr")>;
1441 def: InstRW<[SBWriteResGroup52], (instregex "CMP64rm")>;
1442 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
1443 def: InstRW<[SBWriteResGroup52], (instregex "CMP8mr")>;
1444 def: InstRW<[SBWriteResGroup52], (instregex "CMP8rm")>;
1445 def: InstRW<[SBWriteResGroup52], (instregex "LODSL")>;
1446 def: InstRW<[SBWriteResGroup52], (instregex "LODSQ")>;
1447 def: InstRW<[SBWriteResGroup52], (instregex "OR64rm")>;
1448 def: InstRW<[SBWriteResGroup52], (instregex "OR8rm")>;
1449 def: InstRW<[SBWriteResGroup52], (instregex "SUB64rm")>;
1450 def: InstRW<[SBWriteResGroup52], (instregex "SUB8rm")>;
1451 def: InstRW<[SBWriteResGroup52], (instregex "XOR64rm")>;
1452 def: InstRW<[SBWriteResGroup52], (instregex "XOR8rm")>;
1453
1454 def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
1455 let Latency = 6;
1456 let NumMicroOps = 3;
1457 let ResourceCycles = [1,2];
1458 }
1459 def: InstRW<[SBWriteResGroup53], (instregex "POP64rmm")>;
1460 def: InstRW<[SBWriteResGroup53], (instregex "PUSH64rmm")>;
1461 def: InstRW<[SBWriteResGroup53], (instregex "ST_F32m")>;
1462 def: InstRW<[SBWriteResGroup53], (instregex "ST_F64m")>;
1463 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP32m")>;
1464 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP64m")>;
1465 def: InstRW<[SBWriteResGroup53], (instregex "ST_FP80m")>;
1466
1467 def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
1468 let Latency = 7;
1469 let NumMicroOps = 1;
1470 let ResourceCycles = [1];
1471 }
1472 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm")>;
1473 def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSSrm")>;
1474 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPDYrm")>;
1475 def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPSYrm")>;
1476 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDDUPYrm")>;
1477 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQAYrm")>;
1478 def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQUYrm")>;
1479 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSHDUPYrm")>;
1480 def: InstRW<[SBWriteResGroup54], (instregex "VMOVSLDUPYrm")>;
1481 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPDYrm")>;
1482 def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPSYrm")>;
1483
1484 def SBWriteResGroup55 : SchedWriteRes<[SBPort0,SBPort23]> {
1485 let Latency = 7;
1486 let NumMicroOps = 2;
1487 let ResourceCycles = [1,1];
1488 }
1489 def: InstRW<[SBWriteResGroup55], (instregex "CVTPS2PDrm")>;
1490 def: InstRW<[SBWriteResGroup55], (instregex "CVTSS2SDrm")>;
1491 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDYrm")>;
1492 def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDrm")>;
1493 def: InstRW<[SBWriteResGroup55], (instregex "VCVTSS2SDrm")>;
1494 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPDrm")>;
1495 def: InstRW<[SBWriteResGroup55], (instregex "VTESTPSrm")>;
1496
1497 def SBWriteResGroup56 : SchedWriteRes<[SBPort5,SBPort23]> {
1498 let Latency = 7;
1499 let NumMicroOps = 2;
1500 let ResourceCycles = [1,1];
1501 }
1502 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPDrm")>;
1503 def: InstRW<[SBWriteResGroup56], (instregex "ANDNPSrm")>;
1504 def: InstRW<[SBWriteResGroup56], (instregex "ANDPDrm")>;
1505 def: InstRW<[SBWriteResGroup56], (instregex "ANDPSrm")>;
1506 def: InstRW<[SBWriteResGroup56], (instregex "INSERTPSrm")>;
1507 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPDrm")>;
1508 def: InstRW<[SBWriteResGroup56], (instregex "MOVHPSrm")>;
1509 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPDrm")>;
1510 def: InstRW<[SBWriteResGroup56], (instregex "MOVLPSrm")>;
1511 def: InstRW<[SBWriteResGroup56], (instregex "ORPDrm")>;
1512 def: InstRW<[SBWriteResGroup56], (instregex "ORPSrm")>;
1513 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPDrmi")>;
1514 def: InstRW<[SBWriteResGroup56], (instregex "SHUFPSrmi")>;
1515 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPDrm")>;
1516 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPSrm")>;
1517 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPDrm")>;
1518 def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPSrm")>;
1519 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPDrm")>;
1520 def: InstRW<[SBWriteResGroup56], (instregex "VANDNPSrm")>;
1521 def: InstRW<[SBWriteResGroup56], (instregex "VANDPDrm")>;
1522 def: InstRW<[SBWriteResGroup56], (instregex "VANDPSrm")>;
1523 def: InstRW<[SBWriteResGroup56], (instregex "VBROADCASTF128")>;
1524 def: InstRW<[SBWriteResGroup56], (instregex "VINSERTPSrm")>;
1525 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPDrm")>;
1526 def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPSrm")>;
1527 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPDrm")>;
1528 def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPSrm")>;
1529 def: InstRW<[SBWriteResGroup56], (instregex "VORPDrm")>;
1530 def: InstRW<[SBWriteResGroup56], (instregex "VORPSrm")>;
1531 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDmi")>;
1532 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDri")>;
1533 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSmi")>;
1534 def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSri")>;
1535 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPDrmi")>;
1536 def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPSrmi")>;
1537 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPDrm")>;
1538 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPSrm")>;
1539 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPDrm")>;
1540 def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPSrm")>;
1541 def: InstRW<[SBWriteResGroup56], (instregex "VXORPDrm")>;
1542 def: InstRW<[SBWriteResGroup56], (instregex "VXORPSrm")>;
1543 def: InstRW<[SBWriteResGroup56], (instregex "XORPDrm")>;
1544 def: InstRW<[SBWriteResGroup56], (instregex "XORPSrm")>;
1545
1546 def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> {
1547 let Latency = 7;
1548 let NumMicroOps = 2;
1549 let ResourceCycles = [1,1];
1550 }
1551 def: InstRW<[SBWriteResGroup57], (instregex "AESDECLASTrr")>;
1552 def: InstRW<[SBWriteResGroup57], (instregex "AESDECrr")>;
1553 def: InstRW<[SBWriteResGroup57], (instregex "AESENCLASTrr")>;
1554 def: InstRW<[SBWriteResGroup57], (instregex "AESENCrr")>;
1555 def: InstRW<[SBWriteResGroup57], (instregex "KANDQrr")>;
1556 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECLASTrr")>;
1557 def: InstRW<[SBWriteResGroup57], (instregex "VAESDECrr")>;
1558 def: InstRW<[SBWriteResGroup57], (instregex "VAESENCrr")>;
1559
1560 def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort0]> {
1561 let Latency = 7;
1562 let NumMicroOps = 2;
1563 let ResourceCycles = [1,1];
1564 }
1565 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPDrmi")>;
1566 def: InstRW<[SBWriteResGroup58], (instregex "BLENDPSrmi")>;
1567 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPDrmi")>;
1568 def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPSrmi")>;
1569 def: InstRW<[SBWriteResGroup58], (instregex "VINSERTF128rm")>;
1570
1571 def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
1572 let Latency = 7;
1573 let NumMicroOps = 2;
1574 let ResourceCycles = [1,1];
1575 }
1576 def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>;
1577 def: InstRW<[SBWriteResGroup59], (instregex "PABSBrm")>;
1578 def: InstRW<[SBWriteResGroup59], (instregex "PABSDrm")>;
1579 def: InstRW<[SBWriteResGroup59], (instregex "PABSWrm")>;
1580 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSDWrm")>;
1581 def: InstRW<[SBWriteResGroup59], (instregex "PACKSSWBrm")>;
1582 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSDWrm")>;
1583 def: InstRW<[SBWriteResGroup59], (instregex "PACKUSWBrm")>;
1584 def: InstRW<[SBWriteResGroup59], (instregex "PADDBrm")>;
1585 def: InstRW<[SBWriteResGroup59], (instregex "PADDDrm")>;
1586 def: InstRW<[SBWriteResGroup59], (instregex "PADDQrm")>;
1587 def: InstRW<[SBWriteResGroup59], (instregex "PADDSBrm")>;
1588 def: InstRW<[SBWriteResGroup59], (instregex "PADDSWrm")>;
1589 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSBrm")>;
1590 def: InstRW<[SBWriteResGroup59], (instregex "PADDUSWrm")>;
1591 def: InstRW<[SBWriteResGroup59], (instregex "PADDWrm")>;
1592 def: InstRW<[SBWriteResGroup59], (instregex "PALIGNRrmi")>;
1593 def: InstRW<[SBWriteResGroup59], (instregex "PAVGBrm")>;
1594 def: InstRW<[SBWriteResGroup59], (instregex "PAVGWrm")>;
1595 def: InstRW<[SBWriteResGroup59], (instregex "PBLENDWrmi")>;
1596 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQBrm")>;
1597 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQDrm")>;
1598 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQQrm")>;
1599 def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQWrm")>;
1600 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTBrm")>;
1601 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTDrm")>;
1602 def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTWrm")>;
1603 def: InstRW<[SBWriteResGroup59], (instregex "PINSRBrm")>;
1604 def: InstRW<[SBWriteResGroup59], (instregex "PINSRDrm")>;
1605 def: InstRW<[SBWriteResGroup59], (instregex "PINSRQrm")>;
1606 def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrmi")>;
1607 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSBrm")>;
1608 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSDrm")>;
1609 def: InstRW<[SBWriteResGroup59], (instregex "PMAXSWrm")>;
1610 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUBrm")>;
1611 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUDrm")>;
1612 def: InstRW<[SBWriteResGroup59], (instregex "PMAXUWrm")>;
1613 def: InstRW<[SBWriteResGroup59], (instregex "PMINSBrm")>;
1614 def: InstRW<[SBWriteResGroup59], (instregex "PMINSDrm")>;
1615 def: InstRW<[SBWriteResGroup59], (instregex "PMINSWrm")>;
1616 def: InstRW<[SBWriteResGroup59], (instregex "PMINUBrm")>;
1617 def: InstRW<[SBWriteResGroup59], (instregex "PMINUDrm")>;
1618 def: InstRW<[SBWriteResGroup59], (instregex "PMINUWrm")>;
1619 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBDrm")>;
1620 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBQrm")>;
1621 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBWrm")>;
1622 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXDQrm")>;
1623 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWDrm")>;
1624 def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWQrm")>;
1625 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBDrm")>;
1626 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBQrm")>;
1627 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBWrm")>;
1628 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXDQrm")>;
1629 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWDrm")>;
1630 def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWQrm")>;
1631 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFBrm")>;
1632 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFDmi")>;
1633 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFHWmi")>;
1634 def: InstRW<[SBWriteResGroup59], (instregex "PSHUFLWmi")>;
1635 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm128")>;
1636 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm128")>;
1637 def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm128")>;
1638 def: InstRW<[SBWriteResGroup59], (instregex "PSUBBrm")>;
1639 def: InstRW<[SBWriteResGroup59], (instregex "PSUBDrm")>;
1640 def: InstRW<[SBWriteResGroup59], (instregex "PSUBQrm")>;
1641 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSBrm")>;
1642 def: InstRW<[SBWriteResGroup59], (instregex "PSUBSWrm")>;
1643 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSBrm")>;
1644 def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSWrm")>;
1645 def: InstRW<[SBWriteResGroup59], (instregex "PSUBWrm")>;
1646 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHBWrm")>;
1647 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHDQrm")>;
1648 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHQDQrm")>;
1649 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHWDrm")>;
1650 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLBWrm")>;
1651 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLDQrm")>;
1652 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLQDQrm")>;
1653 def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLWDrm")>;
1654 def: InstRW<[SBWriteResGroup59], (instregex "VPABSBrm")>;
1655 def: InstRW<[SBWriteResGroup59], (instregex "VPABSDrm")>;
1656 def: InstRW<[SBWriteResGroup59], (instregex "VPABSWrm")>;
1657 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSDWrm")>;
1658 def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSWBrm")>;
1659 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSDWrm")>;
1660 def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSWBrm")>;
1661 def: InstRW<[SBWriteResGroup59], (instregex "VPADDBrm")>;
1662 def: InstRW<[SBWriteResGroup59], (instregex "VPADDDrm")>;
1663 def: InstRW<[SBWriteResGroup59], (instregex "VPADDQrm")>;
1664 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSBrm")>;
1665 def: InstRW<[SBWriteResGroup59], (instregex "VPADDSWrm")>;
1666 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSBrm")>;
1667 def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSWrm")>;
1668 def: InstRW<[SBWriteResGroup59], (instregex "VPADDWrm")>;
1669 def: InstRW<[SBWriteResGroup59], (instregex "VPALIGNRrmi")>;
1670 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGBrm")>;
1671 def: InstRW<[SBWriteResGroup59], (instregex "VPAVGWrm")>;
1672 def: InstRW<[SBWriteResGroup59], (instregex "VPBLENDWrmi")>;
1673 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQBrm")>;
1674 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQDrm")>;
1675 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQQrm")>;
1676 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQWrm")>;
1677 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTBrm")>;
1678 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTDrm")>;
1679 def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTWrm")>;
1680 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRBrm")>;
1681 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRDrm")>;
1682 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRQrm")>;
1683 def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrmi")>;
1684 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSBrm")>;
1685 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSDrm")>;
1686 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSWrm")>;
1687 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUBrm")>;
1688 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUDrm")>;
1689 def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUWrm")>;
1690 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSBrm")>;
1691 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSDrm")>;
1692 def: InstRW<[SBWriteResGroup59], (instregex "VPMINSWrm")>;
1693 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUBrm")>;
1694 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUDrm")>;
1695 def: InstRW<[SBWriteResGroup59], (instregex "VPMINUWrm")>;
1696 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBDrm")>;
1697 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBQrm")>;
1698 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBWrm")>;
1699 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXDQrm")>;
1700 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWDrm")>;
1701 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWQrm")>;
1702 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBDrm")>;
1703 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBQrm")>;
1704 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBWrm")>;
1705 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXDQrm")>;
1706 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWDrm")>;
1707 def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWQrm")>;
1708 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFBrm")>;
1709 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFDmi")>;
1710 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFHWmi")>;
1711 def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFLWmi")>;
1712 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm128")>;
1713 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm128")>;
1714 def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm128")>;
1715 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBBrm")>;
1716 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBDrm")>;
1717 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBQrm")>;
1718 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSBrm")>;
1719 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSWrm")>;
1720 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSBrm")>;
1721 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSWrm")>;
1722 def: InstRW<[SBWriteResGroup59], (instregex "VPSUBWrm")>;
1723 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHBWrm")>;
1724 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHDQrm")>;
1725 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHQDQrm")>;
1726 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHWDrm")>;
1727 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLBWrm")>;
1728 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLDQrm")>;
1729 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLQDQrm")>;
1730 def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLWDrm")>;
1731
1732 def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> {
1733 let Latency = 7;
1734 let NumMicroOps = 2;
1735 let ResourceCycles = [1,1];
1736 }
1737 def: InstRW<[SBWriteResGroup60], (instregex "PANDNrm")>;
1738 def: InstRW<[SBWriteResGroup60], (instregex "PANDrm")>;
1739 def: InstRW<[SBWriteResGroup60], (instregex "PORrm")>;
1740 def: InstRW<[SBWriteResGroup60], (instregex "PXORrm")>;
1741 def: InstRW<[SBWriteResGroup60], (instregex "VPANDNrm")>;
1742 def: InstRW<[SBWriteResGroup60], (instregex "VPANDrm")>;
1743 def: InstRW<[SBWriteResGroup60], (instregex "VPORrm")>;
1744 def: InstRW<[SBWriteResGroup60], (instregex "VPXORrm")>;
1745
1746 def SBWriteResGroup61 : SchedWriteRes<[SBPort0,SBPort0]> {
1747 let Latency = 7;
1748 let NumMicroOps = 3;
1749 let ResourceCycles = [2,1];
1750 }
1751 def: InstRW<[SBWriteResGroup61], (instregex "VRCPPSr")>;
1752 def: InstRW<[SBWriteResGroup61], (instregex "VRSQRTPSYr")>;
1753
1754 def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
1755 let Latency = 7;
1756 let NumMicroOps = 3;
1757 let ResourceCycles = [2,1];
1758 }
1759 def: InstRW<[SBWriteResGroup62], (instregex "VERRm")>;
1760 def: InstRW<[SBWriteResGroup62], (instregex "VERWm")>;
1761
1762 def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
1763 let Latency = 7;
1764 let NumMicroOps = 3;
1765 let ResourceCycles = [1,2];
1766 }
1767 def: InstRW<[SBWriteResGroup63], (instregex "LODSB")>;
1768 def: InstRW<[SBWriteResGroup63], (instregex "LODSW")>;
1769
1770 def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
1771 let Latency = 7;
1772 let NumMicroOps = 3;
1773 let ResourceCycles = [1,1,1];
1774 }
1775 def: InstRW<[SBWriteResGroup64], (instregex "FARJMP64")>;
1776
1777 def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> {
1778 let Latency = 7;
1779 let NumMicroOps = 3;
1780 let ResourceCycles = [1,1,1];
1781 }
1782 def: InstRW<[SBWriteResGroup65], (instregex "ADC64rm")>;
1783 def: InstRW<[SBWriteResGroup65], (instregex "ADC8rm")>;
1784 def: InstRW<[SBWriteResGroup65], (instregex "CMOVAE64rm")>;
1785 def: InstRW<[SBWriteResGroup65], (instregex "CMOVB64rm")>;
1786 def: InstRW<[SBWriteResGroup65], (instregex "CMOVE64rm")>;
1787 def: InstRW<[SBWriteResGroup65], (instregex "CMOVG64rm")>;
1788 def: InstRW<[SBWriteResGroup65], (instregex "CMOVGE64rm")>;
1789 def: InstRW<[SBWriteResGroup65], (instregex "CMOVL64rm")>;
1790 def: InstRW<[SBWriteResGroup65], (instregex "CMOVLE64rm")>;
1791 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNE64rm")>;
1792 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNO64rm")>;
1793 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNP64rm")>;
1794 def: InstRW<[SBWriteResGroup65], (instregex "CMOVNS64rm")>;
1795 def: InstRW<[SBWriteResGroup65], (instregex "CMOVO64rm")>;
1796 def: InstRW<[SBWriteResGroup65], (instregex "CMOVP64rm")>;
1797 def: InstRW<[SBWriteResGroup65], (instregex "CMOVS64rm")>;
1798 def: InstRW<[SBWriteResGroup65], (instregex "SBB64rm")>;
1799 def: InstRW<[SBWriteResGroup65], (instregex "SBB8rm")>;
1800
1801 def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
1802 let Latency = 7;
1803 let NumMicroOps = 4;
1804 let ResourceCycles = [1,1,2];
1805 }
1806 def: InstRW<[SBWriteResGroup66], (instregex "FNSTSWm")>;
1807
1808 def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
1809 let Latency = 7;
1810 let NumMicroOps = 4;
1811 let ResourceCycles = [1,2,1];
1812 }
1813 def: InstRW<[SBWriteResGroup67], (instregex "SLDT32r")>;
1814 def: InstRW<[SBWriteResGroup67], (instregex "STR32r")>;
1815
1816 def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
1817 let Latency = 7;
1818 let NumMicroOps = 4;
1819 let ResourceCycles = [1,1,2];
1820 }
1821 def: InstRW<[SBWriteResGroup68], (instregex "CALL64m")>;
1822 def: InstRW<[SBWriteResGroup68], (instregex "FNSTCW16m")>;
1823
1824 def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
1825 let Latency = 7;
1826 let NumMicroOps = 4;
1827 let ResourceCycles = [1,2,1];
1828 }
1829 def: InstRW<[SBWriteResGroup69], (instregex "BTC64mi8")>;
1830 def: InstRW<[SBWriteResGroup69], (instregex "BTR64mi8")>;
1831 def: InstRW<[SBWriteResGroup69], (instregex "BTS64mi8")>;
1832 def: InstRW<[SBWriteResGroup69], (instregex "SAR64mi")>;
1833 def: InstRW<[SBWriteResGroup69], (instregex "SAR8mi")>;
1834 def: InstRW<[SBWriteResGroup69], (instregex "SHL64m1")>;
1835 def: InstRW<[SBWriteResGroup69], (instregex "SHL64mi")>;
1836 def: InstRW<[SBWriteResGroup69], (instregex "SHL8m1")>;
1837 def: InstRW<[SBWriteResGroup69], (instregex "SHL8mi")>;
1838 def: InstRW<[SBWriteResGroup69], (instregex "SHR64mi")>;
1839 def: InstRW<[SBWriteResGroup69], (instregex "SHR8mi")>;
1840
1841 def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1842 let Latency = 7;
1843 let NumMicroOps = 4;
1844 let ResourceCycles = [1,2,1];
1845 }
1846 def: InstRW<[SBWriteResGroup70], (instregex "ADD64mi8")>;
1847 def: InstRW<[SBWriteResGroup70], (instregex "ADD64mr")>;
1848 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
1849 def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
1850 def: InstRW<[SBWriteResGroup70], (instregex "AND64mi8")>;
1851 def: InstRW<[SBWriteResGroup70], (instregex "AND64mr")>;
1852 def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
1853 def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
1854 def: InstRW<[SBWriteResGroup70], (instregex "DEC64m")>;
1855 def: InstRW<[SBWriteResGroup70], (instregex "DEC8m")>;
1856 def: InstRW<[SBWriteResGroup70], (instregex "INC64m")>;
1857 def: InstRW<[SBWriteResGroup70], (instregex "INC8m")>;
1858 def: InstRW<[SBWriteResGroup70], (instregex "NEG64m")>;
1859 def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
1860 def: InstRW<[SBWriteResGroup70], (instregex "NOT64m")>;
1861 def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
1862 def: InstRW<[SBWriteResGroup70], (instregex "OR64mi8")>;
1863 def: InstRW<[SBWriteResGroup70], (instregex "OR64mr")>;
1864 def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
1865 def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
1866 def: InstRW<[SBWriteResGroup70], (instregex "SUB64mi8")>;
1867 def: InstRW<[SBWriteResGroup70], (instregex "SUB64mr")>;
1868 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
1869 def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
1870 def: InstRW<[SBWriteResGroup70], (instregex "TEST64rm")>;
1871 def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
1872 def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>;
1873 def: InstRW<[SBWriteResGroup70], (instregex "XOR64mi8")>;
1874 def: InstRW<[SBWriteResGroup70], (instregex "XOR64mr")>;
1875 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
1876 def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
1877
1878 def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
1879 let Latency = 8;
1880 let NumMicroOps = 2;
1881 let ResourceCycles = [1,1];
1882 }
1883 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm64")>;
1884 def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm64")>;
1885 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm")>;
1886 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPSYrm")>;
1887
1888 def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
1889 let Latency = 8;
1890 let NumMicroOps = 2;
1891 let ResourceCycles = [1,1];
1892 }
1893 def: InstRW<[SBWriteResGroup72], (instregex "BSF64rm")>;
1894 def: InstRW<[SBWriteResGroup72], (instregex "BSR64rm")>;
1895 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m16")>;
1896 def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m8")>;
1897 def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m")>;
1898 def: InstRW<[SBWriteResGroup72], (instregex "FCOM64m")>;
1899 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP32m")>;
1900 def: InstRW<[SBWriteResGroup72], (instregex "FCOMP64m")>;
1901 def: InstRW<[SBWriteResGroup72], (instregex "MUL8m")>;
1902
1903 def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> {
1904 let Latency = 8;
1905 let NumMicroOps = 2;
1906 let ResourceCycles = [1,1];
1907 }
1908 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPDYrm")>;
1909 def: InstRW<[SBWriteResGroup73], (instregex "VANDNPSYrm")>;
1910 def: InstRW<[SBWriteResGroup73], (instregex "VANDPDrm")>;
1911 def: InstRW<[SBWriteResGroup73], (instregex "VANDPSrm")>;
1912 def: InstRW<[SBWriteResGroup73], (instregex "VORPDYrm")>;
1913 def: InstRW<[SBWriteResGroup73], (instregex "VORPSYrm")>;
1914 def: InstRW<[SBWriteResGroup73], (instregex "VPERM2F128rm")>;
1915 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDYri")>;
1916 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDmi")>;
1917 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSYri")>;
1918 def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSmi")>;
1919 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPDYrmi")>;
1920 def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPSYrmi")>;
1921 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPDrm")>;
1922 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPSrm")>;
1923 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPDYrm")>;
1924 def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPSYrm")>;
1925 def: InstRW<[SBWriteResGroup73], (instregex "VXORPDrm")>;
1926 def: InstRW<[SBWriteResGroup73], (instregex "VXORPSrm")>;
1927
1928 def SBWriteResGroup74 : SchedWriteRes<[SBPort23,SBPort0]> {
1929 let Latency = 8;
1930 let NumMicroOps = 2;
1931 let ResourceCycles = [1,1];
1932 }
1933 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPDYrmi")>;
1934 def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPSYrmi")>;
1935
1936 def SBWriteResGroup75 : SchedWriteRes<[SBPort23,SBPort0]> {
1937 let Latency = 8;
1938 let NumMicroOps = 3;
1939 let ResourceCycles = [1,2];
1940 }
1941 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPDrm0")>;
1942 def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPSrm0")>;
1943 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPDrm")>;
1944 def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPSrm")>;
1945 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPDrm")>;
1946 def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPSrm")>;
1947
1948 def SBWriteResGroup76 : SchedWriteRes<[SBPort23,SBPort15]> {
1949 let Latency = 8;
1950 let NumMicroOps = 3;
1951 let ResourceCycles = [1,2];
1952 }
1953 def: InstRW<[SBWriteResGroup76], (instregex "PBLENDVBrr0")>;
1954 def: InstRW<[SBWriteResGroup76], (instregex "VPBLENDVBrm")>;
1955
1956 def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1957 let Latency = 8;
1958 let NumMicroOps = 3;
1959 let ResourceCycles = [1,1,1];
1960 }
1961 def: InstRW<[SBWriteResGroup77], (instregex "COMISDrm")>;
1962 def: InstRW<[SBWriteResGroup77], (instregex "COMISSrm")>;
1963 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISDrm")>;
1964 def: InstRW<[SBWriteResGroup77], (instregex "UCOMISSrm")>;
1965 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISDrm")>;
1966 def: InstRW<[SBWriteResGroup77], (instregex "VCOMISSrm")>;
1967 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISDrm")>;
1968 def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISSrm")>;
1969
1970 def SBWriteResGroup78 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
1971 let Latency = 8;
1972 let NumMicroOps = 3;
1973 let ResourceCycles = [1,1,1];
1974 }
1975 def: InstRW<[SBWriteResGroup78], (instregex "PTESTrm")>;
1976 def: InstRW<[SBWriteResGroup78], (instregex "VPTESTrm")>;
1977
1978 def SBWriteResGroup79 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
1979 let Latency = 8;
1980 let NumMicroOps = 3;
1981 let ResourceCycles = [1,1,1];
1982 }
1983 def: InstRW<[SBWriteResGroup79], (instregex "PSLLDrm")>;
1984 def: InstRW<[SBWriteResGroup79], (instregex "PSLLQrm")>;
1985 def: InstRW<[SBWriteResGroup79], (instregex "PSLLWrm")>;
1986 def: InstRW<[SBWriteResGroup79], (instregex "PSRADrm")>;
1987 def: InstRW<[SBWriteResGroup79], (instregex "PSRAWrm")>;
1988 def: InstRW<[SBWriteResGroup79], (instregex "PSRLDrm")>;
1989 def: InstRW<[SBWriteResGroup79], (instregex "PSRLQrm")>;
1990 def: InstRW<[SBWriteResGroup79], (instregex "PSRLWrm")>;
1991 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLDri")>;
1992 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLQri")>;
1993 def: InstRW<[SBWriteResGroup79], (instregex "VPSLLWri")>;
1994 def: InstRW<[SBWriteResGroup79], (instregex "VPSRADrm")>;
1995 def: InstRW<[SBWriteResGroup79], (instregex "VPSRAWrm")>;
1996 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLDrm")>;
1997 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLQrm")>;
1998 def: InstRW<[SBWriteResGroup79], (instregex "VPSRLWrm")>;
1999
2000 def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
2001 let Latency = 8;
2002 let NumMicroOps = 4;
2003 let ResourceCycles = [1,3];
2004 }
2005 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm64")>;
2006 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm64")>;
2007 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm64")>;
2008 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm64")>;
2009 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm64")>;
2010 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm64")>;
2011
2012 def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
2013 let Latency = 8;
2014 let NumMicroOps = 4;
2015 let ResourceCycles = [1,3];
2016 }
2017 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG64rm")>;
2018 def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG8rm")>;
2019
2020 def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> {
2021 let Latency = 8;
2022 let NumMicroOps = 4;
2023 let ResourceCycles = [1,2,1];
2024 }
2025 def: InstRW<[SBWriteResGroup82], (instregex "CMOVA64rm")>;
2026 def: InstRW<[SBWriteResGroup82], (instregex "CMOVBE64rm")>;
2027
2028 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
2029 let Latency = 8;
2030 let NumMicroOps = 5;
2031 let ResourceCycles = [2,3];
2032 }
2033 def: InstRW<[SBWriteResGroup83], (instregex "CMPSB")>;
2034 def: InstRW<[SBWriteResGroup83], (instregex "CMPSL")>;
2035 def: InstRW<[SBWriteResGroup83], (instregex "CMPSQ")>;
2036 def: InstRW<[SBWriteResGroup83], (instregex "CMPSW")>;
2037
2038 def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
2039 let Latency = 8;
2040 let NumMicroOps = 5;
2041 let ResourceCycles = [1,2,2];
2042 }
2043 def: InstRW<[SBWriteResGroup84], (instregex "FLDCW16m")>;
2044
2045 def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> {
2046 let Latency = 8;
2047 let NumMicroOps = 5;
2048 let ResourceCycles = [1,2,2];
2049 }
2050 def: InstRW<[SBWriteResGroup85], (instregex "ROL64mi")>;
2051 def: InstRW<[SBWriteResGroup85], (instregex "ROL8mi")>;
2052 def: InstRW<[SBWriteResGroup85], (instregex "ROR64mi")>;
2053 def: InstRW<[SBWriteResGroup85], (instregex "ROR8mi")>;
2054
2055 def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2056 let Latency = 8;
2057 let NumMicroOps = 5;
2058 let ResourceCycles = [1,2,2];
2059 }
2060 def: InstRW<[SBWriteResGroup86], (instregex "MOVSB")>;
2061 def: InstRW<[SBWriteResGroup86], (instregex "MOVSL")>;
2062 def: InstRW<[SBWriteResGroup86], (instregex "MOVSQ")>;
2063 def: InstRW<[SBWriteResGroup86], (instregex "MOVSW")>;
2064 def: InstRW<[SBWriteResGroup86], (instregex "XADD64rm")>;
2065 def: InstRW<[SBWriteResGroup86], (instregex "XADD8rm")>;
2066
2067 def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
2068 let Latency = 8;
2069 let NumMicroOps = 5;
2070 let ResourceCycles = [1,1,1,2];
2071 }
2072 def: InstRW<[SBWriteResGroup87], (instregex "FARCALL64")>;
2073
2074 def SBWriteResGroup88 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
2075 let Latency = 8;
2076 let NumMicroOps = 5;
2077 let ResourceCycles = [1,2,1,1];
2078 }
2079 def: InstRW<[SBWriteResGroup88], (instregex "SHLD64mri8")>;
2080 def: InstRW<[SBWriteResGroup88], (instregex "SHRD64mri8")>;
2081
2082 def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort23]> {
2083 let Latency = 9;
2084 let NumMicroOps = 2;
2085 let ResourceCycles = [1,1];
2086 }
2087 def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm")>;
2088 def: InstRW<[SBWriteResGroup89], (instregex "PMADDUBSWrm")>;
2089 def: InstRW<[SBWriteResGroup89], (instregex "PMADDWDrm")>;
2090 def: InstRW<[SBWriteResGroup89], (instregex "PMULDQrm")>;
2091 def: InstRW<[SBWriteResGroup89], (instregex "PMULHRSWrm")>;
2092 def: InstRW<[SBWriteResGroup89], (instregex "PMULHUWrm")>;
2093 def: InstRW<[SBWriteResGroup89], (instregex "PMULHWrm")>;
2094 def: InstRW<[SBWriteResGroup89], (instregex "PMULLDrm")>;
2095 def: InstRW<[SBWriteResGroup89], (instregex "PMULLWrm")>;
2096 def: InstRW<[SBWriteResGroup89], (instregex "PMULUDQrm")>;
2097 def: InstRW<[SBWriteResGroup89], (instregex "PSADBWrm")>;
2098 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDUBSWrm")>;
2099 def: InstRW<[SBWriteResGroup89], (instregex "VPMADDWDrm")>;
2100 def: InstRW<[SBWriteResGroup89], (instregex "VPMULDQrm")>;
2101 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHRSWrm")>;
2102 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHUWrm")>;
2103 def: InstRW<[SBWriteResGroup89], (instregex "VPMULHWrm")>;
2104 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLDrm")>;
2105 def: InstRW<[SBWriteResGroup89], (instregex "VPMULLWrm")>;
2106 def: InstRW<[SBWriteResGroup89], (instregex "VPMULUDQrm")>;
2107 def: InstRW<[SBWriteResGroup89], (instregex "VPSADBWrm")>;
2108
2109 def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
2110 let Latency = 9;
2111 let NumMicroOps = 2;
2112 let ResourceCycles = [1,1];
2113 }
2114 def: InstRW<[SBWriteResGroup90], (instregex "ADDPDrm")>;
2115 def: InstRW<[SBWriteResGroup90], (instregex "ADDPSrm")>;
2116 def: InstRW<[SBWriteResGroup90], (instregex "ADDSDrm")>;
2117 def: InstRW<[SBWriteResGroup90], (instregex "ADDSSrm")>;
2118 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPDrm")>;
2119 def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPSrm")>;
2120 def: InstRW<[SBWriteResGroup90], (instregex "CMPPDrmi")>;
2121 def: InstRW<[SBWriteResGroup90], (instregex "CMPPSrmi")>;
2122 def: InstRW<[SBWriteResGroup90], (instregex "CMPSSrm")>;
2123 def: InstRW<[SBWriteResGroup90], (instregex "CVTDQ2PSrm")>;
2124 def: InstRW<[SBWriteResGroup90], (instregex "CVTPS2DQrm")>;
2125 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SD64rm")>;
2126 def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SDrm")>;
2127 def: InstRW<[SBWriteResGroup90], (instregex "CVTTPS2DQrm")>;
2128 def: InstRW<[SBWriteResGroup90], (instregex "MAXPDrm")>;
2129 def: InstRW<[SBWriteResGroup90], (instregex "MAXPSrm")>;
2130 def: InstRW<[SBWriteResGroup90], (instregex "MAXSDrm")>;
2131 def: InstRW<[SBWriteResGroup90], (instregex "MAXSSrm")>;
2132 def: InstRW<[SBWriteResGroup90], (instregex "MINPDrm")>;
2133 def: InstRW<[SBWriteResGroup90], (instregex "MINPSrm")>;
2134 def: InstRW<[SBWriteResGroup90], (instregex "MINSDrm")>;
2135 def: InstRW<[SBWriteResGroup90], (instregex "MINSSrm")>;
2136 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm")>;
2137 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm")>;
2138 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTTPS2PIirm")>;
2139 def: InstRW<[SBWriteResGroup90], (instregex "POPCNT64rm")>;
2140 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPDm")>;
2141 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPSm")>;
2142 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSDm")>;
2143 def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSSm")>;
2144 def: InstRW<[SBWriteResGroup90], (instregex "SUBPDrm")>;
2145 def: InstRW<[SBWriteResGroup90], (instregex "SUBPSrm")>;
2146 def: InstRW<[SBWriteResGroup90], (instregex "SUBSDrm")>;
2147 def: InstRW<[SBWriteResGroup90], (instregex "SUBSSrm")>;
2148 def: InstRW<[SBWriteResGroup90], (instregex "VADDPDrm")>;
2149 def: InstRW<[SBWriteResGroup90], (instregex "VADDPSrm")>;
2150 def: InstRW<[SBWriteResGroup90], (instregex "VADDSDrm")>;
2151 def: InstRW<[SBWriteResGroup90], (instregex "VADDSSrm")>;
2152 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPDrm")>;
2153 def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPSrm")>;
2154 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPDrmi")>;
2155 def: InstRW<[SBWriteResGroup90], (instregex "VCMPPSrmi")>;
2156 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSDrm")>;
2157 def: InstRW<[SBWriteResGroup90], (instregex "VCMPSSrm")>;
2158 def: InstRW<[SBWriteResGroup90], (instregex "VCVTDQ2PSrm")>;
2159 def: InstRW<[SBWriteResGroup90], (instregex "VCVTPS2DQrm")>;
2160 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SD64rm")>;
2161 def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SDrm")>;
2162 def: InstRW<[SBWriteResGroup90], (instregex "VCVTTPS2DQrm")>;
2163 def: InstRW<[SBWriteResGroup90], (instregex "VMAXPDrm")>;
2164 def: InstRW<[SBWriteResGroup90], (instregex "VMAXPSrm")>;
2165 def: InstRW<[SBWriteResGroup90], (instregex "VMAXSDrm")>;
2166 def: InstRW<[SBWriteResGroup90], (instregex "VMAXSSrm")>;
2167 def: InstRW<[SBWriteResGroup90], (instregex "VMINPDrm")>;
2168 def: InstRW<[SBWriteResGroup90], (instregex "VMINPSrm")>;
2169 def: InstRW<[SBWriteResGroup90], (instregex "VMINSDrm")>;
2170 def: InstRW<[SBWriteResGroup90], (instregex "VMINSSrm")>;
2171 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPDm")>;
2172 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPSm")>;
2173 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSDm")>;
2174 def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSSm")>;
2175 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPDrm")>;
2176 def: InstRW<[SBWriteResGroup90], (instregex "VSUBPSrm")>;
2177 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSDrm")>;
2178 def: InstRW<[SBWriteResGroup90], (instregex "VSUBSSrm")>;
2179
2180 def SBWriteResGroup91 : SchedWriteRes<[SBPort23,SBPort0]> {
2181 let Latency = 9;
2182 let NumMicroOps = 3;
2183 let ResourceCycles = [1,2];
2184 }
2185 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPDYrm")>;
2186 def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPSYrm")>;
2187 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPDrm")>;
2188 def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPSrm")>;
2189
2190 def SBWriteResGroup92 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2191 let Latency = 9;
2192 let NumMicroOps = 3;
2193 let ResourceCycles = [1,1,1];
2194 }
2195 def: InstRW<[SBWriteResGroup92], (instregex "DPPDrri")>;
2196 def: InstRW<[SBWriteResGroup92], (instregex "VDPPDrri")>;
2197
2198 def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2199 let Latency = 9;
2200 let NumMicroOps = 3;
2201 let ResourceCycles = [1,1,1];
2202 }
2203 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm")>;
2204 def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SIrm")>;
2205 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SI64rm")>;
2206 def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SIrm")>;
2207 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SI64rm")>;
2208 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SIrm")>;
2209 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SI64rm")>;
2210 def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SIrm")>;
2211 def: InstRW<[SBWriteResGroup93], (instregex "MUL64m")>;
2212
2213 def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
2214 let Latency = 9;
2215 let NumMicroOps = 3;
2216 let ResourceCycles = [1,1,1];
2217 }
2218 def: InstRW<[SBWriteResGroup94], (instregex "VPTESTYrm")>;
2219
2220 def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
2221 let Latency = 9;
2222 let NumMicroOps = 3;
2223 let ResourceCycles = [1,1,1];
2224 }
2225 def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m")>;
2226 def: InstRW<[SBWriteResGroup95], (instregex "LD_F64m")>;
2227 def: InstRW<[SBWriteResGroup95], (instregex "LD_F80m")>;
2228
2229 def SBWriteResGroup96 : SchedWriteRes<[SBPort23,SBPort15]> {
2230 let Latency = 9;
2231 let NumMicroOps = 4;
2232 let ResourceCycles = [1,3];
2233 }
2234 def: InstRW<[SBWriteResGroup96], (instregex "PHADDDrm")>;
2235 def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm128")>;
2236 def: InstRW<[SBWriteResGroup96], (instregex "PHADDWrm")>;
2237 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBDrm")>;
2238 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm128")>;
2239 def: InstRW<[SBWriteResGroup96], (instregex "PHSUBWrm")>;
2240 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDDrm")>;
2241 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm128")>;
2242 def: InstRW<[SBWriteResGroup96], (instregex "VPHADDWrm")>;
2243 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBDrm")>;
2244 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm128")>;
2245 def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBWrm")>;
2246
2247 def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
2248 let Latency = 9;
2249 let NumMicroOps = 4;
2250 let ResourceCycles = [1,1,2];
2251 }
2252 def: InstRW<[SBWriteResGroup97], (instregex "IST_F16m")>;
2253 def: InstRW<[SBWriteResGroup97], (instregex "IST_F32m")>;
2254 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP16m")>;
2255 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP32m")>;
2256 def: InstRW<[SBWriteResGroup97], (instregex "IST_FP64m")>;
2257 def: InstRW<[SBWriteResGroup97], (instregex "SHL64mCL")>;
2258 def: InstRW<[SBWriteResGroup97], (instregex "SHL8mCL")>;
2259
2260 def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
2261 let Latency = 9;
2262 let NumMicroOps = 6;
2263 let ResourceCycles = [1,2,3];
2264 }
2265 def: InstRW<[SBWriteResGroup98], (instregex "ADC64mi8")>;
2266 def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
2267 def: InstRW<[SBWriteResGroup98], (instregex "SBB64mi8")>;
2268 def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
2269
2270 def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
2271 let Latency = 9;
2272 let NumMicroOps = 6;
2273 let ResourceCycles = [1,2,2,1];
2274 }
2275 def: InstRW<[SBWriteResGroup99], (instregex "ADC64mr")>;
2276 def: InstRW<[SBWriteResGroup99], (instregex "ADC8mr")>;
2277 def: InstRW<[SBWriteResGroup99], (instregex "SBB64mr")>;
2278 def: InstRW<[SBWriteResGroup99], (instregex "SBB8mr")>;
2279
2280 def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort0,SBPort015]> {
2281 let Latency = 9;
2282 let NumMicroOps = 6;
2283 let ResourceCycles = [1,1,2,1,1];
2284 }
2285 def: InstRW<[SBWriteResGroup100], (instregex "BT64mr")>;
2286 def: InstRW<[SBWriteResGroup100], (instregex "BTC64mr")>;
2287 def: InstRW<[SBWriteResGroup100], (instregex "BTR64mr")>;
2288 def: InstRW<[SBWriteResGroup100], (instregex "BTS64mr")>;
2289
2290 def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
2291 let Latency = 10;
2292 let NumMicroOps = 2;
2293 let ResourceCycles = [1,1];
2294 }
2295 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m")>;
2296 def: InstRW<[SBWriteResGroup101], (instregex "ADD_F64m")>;
2297 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F16m")>;
2298 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F32m")>;
2299 def: InstRW<[SBWriteResGroup101], (instregex "ILD_F64m")>;
2300 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F32m")>;
2301 def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F64m")>;
2302 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F32m")>;
2303 def: InstRW<[SBWriteResGroup101], (instregex "SUB_F64m")>;
2304 def: InstRW<[SBWriteResGroup101], (instregex "VADDPDYrm")>;
2305 def: InstRW<[SBWriteResGroup101], (instregex "VADDPSYrm")>;
2306 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPDYrm")>;
2307 def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPSYrm")>;
2308 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPDYrmi")>;
2309 def: InstRW<[SBWriteResGroup101], (instregex "VCMPPSYrmi")>;
2310 def: InstRW<[SBWriteResGroup101], (instregex "VCVTDQ2PSYrm")>;
2311 def: InstRW<[SBWriteResGroup101], (instregex "VCVTPS2DQYrm")>;
2312 def: InstRW<[SBWriteResGroup101], (instregex "VCVTTPS2DQrm")>;
2313 def: InstRW<[SBWriteResGroup101], (instregex "VMAXPDYrm")>;
2314 def: InstRW<[SBWriteResGroup101], (instregex "VMAXPSYrm")>;
2315 def: InstRW<[SBWriteResGroup101], (instregex "VMINPDrm")>;
2316 def: InstRW<[SBWriteResGroup101], (instregex "VMINPSrm")>;
2317 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPDm")>;
2318 def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPSm")>;
2319 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPDYrm")>;
2320 def: InstRW<[SBWriteResGroup101], (instregex "VSUBPSYrm")>;
2321
2322 def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2323 let Latency = 10;
2324 let NumMicroOps = 3;
2325 let ResourceCycles = [1,1,1];
2326 }
2327 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm")>;
2328 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rr")>;
2329 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SI64rm")>;
2330 def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SIrm")>;
2331 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rm")>;
2332 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rr")>;
2333 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SI64rm")>;
2334 def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SIrm")>;
2335
2336 def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2337 let Latency = 10;
2338 let NumMicroOps = 3;
2339 let ResourceCycles = [1,1,1];
2340 }
2341 def: InstRW<[SBWriteResGroup103], (instregex "CVTDQ2PDrm")>;
2342 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2DQrm")>;
2343 def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2PSrm")>;
2344 def: InstRW<[SBWriteResGroup103], (instregex "CVTSD2SSrm")>;
2345 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SS64rm")>;
2346 def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SSrm")>;
2347 def: InstRW<[SBWriteResGroup103], (instregex "CVTTPD2DQrm")>;
2348 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm")>;
2349 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm")>;
2350 def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTTPD2PIirm")>;
2351 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDYrm")>;
2352 def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDrm")>;
2353 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2DQrm")>;
2354 def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2PSrm")>;
2355 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSD2SSrm")>;
2356 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SS64rm")>;
2357 def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SSrm")>;
2358 def: InstRW<[SBWriteResGroup103], (instregex "VCVTTPD2DQrm")>;
2359
2360 def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
2361 let Latency = 11;
2362 let NumMicroOps = 2;
2363 let ResourceCycles = [1,1];
2364 }
2365 def: InstRW<[SBWriteResGroup104], (instregex "MULPDrm")>;
2366 def: InstRW<[SBWriteResGroup104], (instregex "MULPSrm")>;
2367 def: InstRW<[SBWriteResGroup104], (instregex "MULSDrm")>;
2368 def: InstRW<[SBWriteResGroup104], (instregex "MULSSrm")>;
2369 def: InstRW<[SBWriteResGroup104], (instregex "PCMPGTQrm")>;
2370 def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm128")>;
2371 def: InstRW<[SBWriteResGroup104], (instregex "RCPPSm")>;
2372 def: InstRW<[SBWriteResGroup104], (instregex "RCPSSm")>;
2373 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTPSm")>;
2374 def: InstRW<[SBWriteResGroup104], (instregex "RSQRTSSm")>;
2375 def: InstRW<[SBWriteResGroup104], (instregex "VMULPDrm")>;
2376 def: InstRW<[SBWriteResGroup104], (instregex "VMULPSrm")>;
2377 def: InstRW<[SBWriteResGroup104], (instregex "VMULSDrm")>;
2378 def: InstRW<[SBWriteResGroup104], (instregex "VMULSSrm")>;
2379 def: InstRW<[SBWriteResGroup104], (instregex "VPCMPGTQrm")>;
2380 def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm128")>;
2381 def: InstRW<[SBWriteResGroup104], (instregex "VRCPPSm")>;
2382 def: InstRW<[SBWriteResGroup104], (instregex "VRCPSSm")>;
2383 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTPSm")>;
2384 def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTSSm")>;
2385
2386 def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> {
2387 let Latency = 11;
2388 let NumMicroOps = 3;
2389 let ResourceCycles = [3];
2390 }
2391 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRIrr")>;
2392 def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRM128rr")>;
2393 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRIrr")>;
2394 def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRM128rr")>;
2395
2396 def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
2397 let Latency = 11;
2398 let NumMicroOps = 3;
2399 let ResourceCycles = [2,1];
2400 }
2401 def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m")>;
2402 def: InstRW<[SBWriteResGroup106], (instregex "FICOM32m")>;
2403 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP16m")>;
2404 def: InstRW<[SBWriteResGroup106], (instregex "FICOMP32m")>;
2405
2406 def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2407 let Latency = 11;
2408 let NumMicroOps = 3;
2409 let ResourceCycles = [1,1,1];
2410 }
2411 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm")>;
2412 def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm")>;
2413 def: InstRW<[SBWriteResGroup107], (instregex "VCVTTPD2DQYrm")>;
2414
2415 def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> {
2416 let Latency = 11;
2417 let NumMicroOps = 4;
2418 let ResourceCycles = [1,1,2];
2419 }
2420 def: InstRW<[SBWriteResGroup108], (instregex "MPSADBWrmi")>;
2421 def: InstRW<[SBWriteResGroup108], (instregex "VMPSADBWrmi")>;
2422
2423 def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2424 let Latency = 11;
2425 let NumMicroOps = 4;
2426 let ResourceCycles = [1,2,1];
2427 }
2428 def: InstRW<[SBWriteResGroup109], (instregex "HADDPDrm")>;
2429 def: InstRW<[SBWriteResGroup109], (instregex "HADDPSrm")>;
2430 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPDrm")>;
2431 def: InstRW<[SBWriteResGroup109], (instregex "HSUBPSrm")>;
2432 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPDrm")>;
2433 def: InstRW<[SBWriteResGroup109], (instregex "VHADDPSrm")>;
2434 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPDrm")>;
2435 def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPSrm")>;
2436
2437 def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> {
2438 let Latency = 12;
2439 let NumMicroOps = 2;
2440 let ResourceCycles = [2];
2441 }
2442 def: InstRW<[SBWriteResGroup110], (instregex "AESIMCrr")>;
2443 def: InstRW<[SBWriteResGroup110], (instregex "VAESIMCrr")>;
2444
2445 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
2446 let Latency = 12;
2447 let NumMicroOps = 2;
2448 let ResourceCycles = [1,1];
2449 }
2450 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F32m")>;
2451 def: InstRW<[SBWriteResGroup111], (instregex "MUL_F64m")>;
2452 def: InstRW<[SBWriteResGroup111], (instregex "VMULPDYrm")>;
2453 def: InstRW<[SBWriteResGroup111], (instregex "VMULPSYrm")>;
2454
2455 def SBWriteResGroup112 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
2456 let Latency = 12;
2457 let NumMicroOps = 4;
2458 let ResourceCycles = [1,2,1];
2459 }
2460 def: InstRW<[SBWriteResGroup112], (instregex "DPPSrri")>;
2461 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSYrri")>;
2462 def: InstRW<[SBWriteResGroup112], (instregex "VDPPSrri")>;
2463
2464 def SBWriteResGroup113 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> {
2465 let Latency = 12;
2466 let NumMicroOps = 4;
2467 let ResourceCycles = [1,2,1];
2468 }
2469 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPDrm")>;
2470 def: InstRW<[SBWriteResGroup113], (instregex "VHADDPSYrm")>;
2471 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPDYrm")>;
2472 def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPSYrm")>;
2473
2474 def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
2475 let Latency = 13;
2476 let NumMicroOps = 3;
2477 let ResourceCycles = [2,1];
2478 }
2479 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m")>;
2480 def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI32m")>;
2481 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI16m")>;
2482 def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI32m")>;
2483 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI16m")>;
2484 def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI32m")>;
2485
2486 def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> {
2487 let Latency = 13;
2488 let NumMicroOps = 3;
2489 let ResourceCycles = [1,1,1];
2490 }
2491 def: InstRW<[SBWriteResGroup115], (instregex "AESDECLASTrm")>;
2492 def: InstRW<[SBWriteResGroup115], (instregex "AESDECrm")>;
2493 def: InstRW<[SBWriteResGroup115], (instregex "AESENCLASTrm")>;
2494 def: InstRW<[SBWriteResGroup115], (instregex "AESENCrm")>;
2495 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECLASTrm")>;
2496 def: InstRW<[SBWriteResGroup115], (instregex "VAESDECrm")>;
2497 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCLASTrm")>;
2498 def: InstRW<[SBWriteResGroup115], (instregex "VAESENCrm")>;
2499
2500 def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
2501 let Latency = 14;
2502 let NumMicroOps = 1;
2503 let ResourceCycles = [1];
2504 }
2505 def: InstRW<[SBWriteResGroup116], (instregex "DIVPSrr")>;
2506 def: InstRW<[SBWriteResGroup116], (instregex "DIVSSrr")>;
2507 def: InstRW<[SBWriteResGroup116], (instregex "SQRTPSr")>;
2508 def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr")>;
2509 def: InstRW<[SBWriteResGroup116], (instregex "VDIVPSrr")>;
2510 def: InstRW<[SBWriteResGroup116], (instregex "VDIVSSrr")>;
2511 def: InstRW<[SBWriteResGroup116], (instregex "VSQRTPSr")>;
2512
2513 def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> {
2514 let Latency = 14;
2515 let NumMicroOps = 2;
2516 let ResourceCycles = [1,1];
2517 }
2518 def: InstRW<[SBWriteResGroup117], (instregex "VSQRTSSm")>;
2519
2520 def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2521 let Latency = 14;
2522 let NumMicroOps = 4;
2523 let ResourceCycles = [2,1,1];
2524 }
2525 def: InstRW<[SBWriteResGroup118], (instregex "VRCPPSm")>;
2526 def: InstRW<[SBWriteResGroup118], (instregex "VRSQRTPSYm")>;
2527
2528 def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2529 let Latency = 15;
2530 let NumMicroOps = 3;
2531 let ResourceCycles = [1,1,1];
2532 }
2533 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI16m")>;
2534 def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI32m")>;
2535
2536 def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
2537 let Latency = 15;
2538 let NumMicroOps = 4;
2539 let ResourceCycles = [1,1,1,1];
2540 }
2541 def: InstRW<[SBWriteResGroup120], (instregex "DPPDrmi")>;
2542 def: InstRW<[SBWriteResGroup120], (instregex "VDPPDrmi")>;
2543
2544 def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> {
2545 let Latency = 17;
2546 let NumMicroOps = 4;
2547 let ResourceCycles = [3,1];
2548 }
2549 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRIrm")>;
2550 def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRM128rm")>;
2551 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRIrm")>;
2552 def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRM128rm")>;
2553
2554 def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> {
2555 let Latency = 18;
2556 let NumMicroOps = 3;
2557 let ResourceCycles = [2,1];
2558 }
2559 def: InstRW<[SBWriteResGroup122], (instregex "AESIMCrm")>;
2560 def: InstRW<[SBWriteResGroup122], (instregex "VAESIMCrm")>;
2561
2562 def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
2563 let Latency = 20;
2564 let NumMicroOps = 2;
2565 let ResourceCycles = [1,1];
2566 }
2567 def: InstRW<[SBWriteResGroup123], (instregex "DIVPSrm")>;
2568 def: InstRW<[SBWriteResGroup123], (instregex "DIVSSrm")>;
2569 def: InstRW<[SBWriteResGroup123], (instregex "SQRTPSm")>;
2570 def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm")>;
2571 def: InstRW<[SBWriteResGroup123], (instregex "VDIVPSrm")>;
2572 def: InstRW<[SBWriteResGroup123], (instregex "VDIVSSrm")>;
2573 def: InstRW<[SBWriteResGroup123], (instregex "VSQRTPSm")>;
2574
2575 def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
2576 let Latency = 21;
2577 let NumMicroOps = 1;
2578 let ResourceCycles = [1];
2579 }
2580 def: InstRW<[SBWriteResGroup124], (instregex "VSQRTSDr")>;
2581
2582 def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> {
2583 let Latency = 21;
2584 let NumMicroOps = 2;
2585 let ResourceCycles = [1,1];
2586 }
2587 def: InstRW<[SBWriteResGroup125], (instregex "VSQRTSDm")>;
2588
2589 def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> {
2590 let Latency = 22;
2591 let NumMicroOps = 1;
2592 let ResourceCycles = [1];
2593 }
2594 def: InstRW<[SBWriteResGroup126], (instregex "DIVPDrr")>;
2595 def: InstRW<[SBWriteResGroup126], (instregex "DIVSDrr")>;
2596 def: InstRW<[SBWriteResGroup126], (instregex "SQRTPDr")>;
2597 def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr")>;
2598 def: InstRW<[SBWriteResGroup126], (instregex "VDIVPDrr")>;
2599 def: InstRW<[SBWriteResGroup126], (instregex "VDIVSDrr")>;
2600 def: InstRW<[SBWriteResGroup126], (instregex "VSQRTPDr")>;
2601
2602 def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
2603 let Latency = 24;
2604 let NumMicroOps = 1;
2605 let ResourceCycles = [1];
2606 }
2607 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0")>;
2608 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FST0r")>;
2609 def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FrST0")>;
2610 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FPrST0")>;
2611 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FST0r")>;
2612 def: InstRW<[SBWriteResGroup127], (instregex "DIV_FrST0")>;
2613
2614 def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> {
2615 let Latency = 28;
2616 let NumMicroOps = 2;
2617 let ResourceCycles = [1,1];
2618 }
2619 def: InstRW<[SBWriteResGroup128], (instregex "DIVPDrm")>;
2620 def: InstRW<[SBWriteResGroup128], (instregex "DIVSDrm")>;
2621 def: InstRW<[SBWriteResGroup128], (instregex "SQRTPDm")>;
2622 def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm")>;
2623 def: InstRW<[SBWriteResGroup128], (instregex "VDIVPDrm")>;
2624 def: InstRW<[SBWriteResGroup128], (instregex "VDIVSDrm")>;
2625 def: InstRW<[SBWriteResGroup128], (instregex "VSQRTPDm")>;
2626
2627 def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort0]> {
2628 let Latency = 29;
2629 let NumMicroOps = 3;
2630 let ResourceCycles = [2,1];
2631 }
2632 def: InstRW<[SBWriteResGroup129], (instregex "VDIVPSYrr")>;
2633 def: InstRW<[SBWriteResGroup129], (instregex "VSQRTPSYr")>;
2634
2635 def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
2636 let Latency = 31;
2637 let NumMicroOps = 2;
2638 let ResourceCycles = [1,1];
2639 }
2640 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F32m")>;
2641 def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F64m")>;
2642 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F32m")>;
2643 def: InstRW<[SBWriteResGroup130], (instregex "DIV_F64m")>;
2644
2645 def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
2646 let Latency = 34;
2647 let NumMicroOps = 3;
2648 let ResourceCycles = [1,1,1];
2649 }
2650 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI16m")>;
2651 def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI32m")>;
2652 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI16m")>;
2653 def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI32m")>;
2654
2655 def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2656 let Latency = 36;
2657 let NumMicroOps = 4;
2658 let ResourceCycles = [2,1,1];
2659 }
2660 def: InstRW<[SBWriteResGroup132], (instregex "VDIVPSYrm")>;
2661 def: InstRW<[SBWriteResGroup132], (instregex "VSQRTPSYm")>;
2662
2663 def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort0]> {
2664 let Latency = 45;
2665 let NumMicroOps = 3;
2666 let ResourceCycles = [2,1];
2667 }
2668 def: InstRW<[SBWriteResGroup133], (instregex "VDIVPDYrr")>;
2669 def: InstRW<[SBWriteResGroup133], (instregex "VSQRTPDYr")>;
2670
2671 def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> {
2672 let Latency = 52;
2673 let NumMicroOps = 4;
2674 let ResourceCycles = [2,1,1];
2675 }
2676 def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm")>;
2677 def: InstRW<[SBWriteResGroup134], (instregex "VSQRTPDYm")>;
2678
2679 def SBWriteResGroup135 : SchedWriteRes<[SBPort0]> {
2680 let Latency = 114;
2681 let NumMicroOps = 1;
2682 let ResourceCycles = [1];
2683 }
2684 def: InstRW<[SBWriteResGroup135], (instregex "VSQRTSSr")>;
2685
2742686 } // SchedModel
99 ; SANDY-LABEL: test_addpd:
1010 ; SANDY: # BB#0:
1111 ; SANDY-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
12 ; SANDY-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
13 ; SANDY-NEXT: retq # sched: [5:1.00]
12 ; SANDY-NEXT: vaddpd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
13 ; SANDY-NEXT: retq # sched: [1:1.00]
1414 ;
1515 ; HASWELL-LABEL: test_addpd:
1616 ; HASWELL: # BB#0:
3939 ; SANDY-LABEL: test_addps:
4040 ; SANDY: # BB#0:
4141 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
42 ; SANDY-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
43 ; SANDY-NEXT: retq # sched: [5:1.00]
42 ; SANDY-NEXT: vaddps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
43 ; SANDY-NEXT: retq # sched: [1:1.00]
4444 ;
4545 ; HASWELL-LABEL: test_addps:
4646 ; HASWELL: # BB#0:
6969 ; SANDY-LABEL: test_addsubpd:
7070 ; SANDY: # BB#0:
7171 ; SANDY-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
72 ; SANDY-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
73 ; SANDY-NEXT: retq # sched: [5:1.00]
72 ; SANDY-NEXT: vaddsubpd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
73 ; SANDY-NEXT: retq # sched: [1:1.00]
7474 ;
7575 ; HASWELL-LABEL: test_addsubpd:
7676 ; HASWELL: # BB#0:
100100 ; SANDY-LABEL: test_addsubps:
101101 ; SANDY: # BB#0:
102102 ; SANDY-NEXT: vaddsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
103 ; SANDY-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
104 ; SANDY-NEXT: retq # sched: [5:1.00]
103 ; SANDY-NEXT: vaddsubps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
104 ; SANDY-NEXT: retq # sched: [1:1.00]
105105 ;
106106 ; HASWELL-LABEL: test_addsubps:
107107 ; HASWELL: # BB#0:
130130 define <4 x double> @test_andnotpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
131131 ; SANDY-LABEL: test_andnotpd:
132132 ; SANDY: # BB#0:
133 ; SANDY-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
134 ; SANDY-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
133 ; SANDY-NEXT: vandnpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
134 ; SANDY-NEXT: vandnpd (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
135135 ; SANDY-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
136 ; SANDY-NEXT: retq # sched: [5:1.00]
136 ; SANDY-NEXT: retq # sched: [1:1.00]
137137 ;
138138 ; HASWELL-LABEL: test_andnotpd:
139139 ; HASWELL: # BB#0:
171171 define <8 x float> @test_andnotps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
172172 ; SANDY-LABEL: test_andnotps:
173173 ; SANDY: # BB#0:
174 ; SANDY-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
175 ; SANDY-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
174 ; SANDY-NEXT: vandnps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
175 ; SANDY-NEXT: vandnps (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
176176 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
177 ; SANDY-NEXT: retq # sched: [5:1.00]
177 ; SANDY-NEXT: retq # sched: [1:1.00]
178178 ;
179179 ; HASWELL-LABEL: test_andnotps:
180180 ; HASWELL: # BB#0:
212212 define <4 x double> @test_andpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
213213 ; SANDY-LABEL: test_andpd:
214214 ; SANDY: # BB#0:
215 ; SANDY-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
216 ; SANDY-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
215 ; SANDY-NEXT: vandpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
216 ; SANDY-NEXT: vandpd (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
217217 ; SANDY-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
218 ; SANDY-NEXT: retq # sched: [5:1.00]
218 ; SANDY-NEXT: retq # sched: [1:1.00]
219219 ;
220220 ; HASWELL-LABEL: test_andpd:
221221 ; HASWELL: # BB#0:
251251 define <8 x float> @test_andps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
252252 ; SANDY-LABEL: test_andps:
253253 ; SANDY: # BB#0:
254 ; SANDY-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
255 ; SANDY-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
254 ; SANDY-NEXT: vandps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
255 ; SANDY-NEXT: vandps (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
256256 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
257 ; SANDY-NEXT: retq # sched: [5:1.00]
257 ; SANDY-NEXT: retq # sched: [1:1.00]
258258 ;
259259 ; HASWELL-LABEL: test_andps:
260260 ; HASWELL: # BB#0:
290290 define <4 x double> @test_blendpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
291291 ; SANDY-LABEL: test_blendpd:
292292 ; SANDY: # BB#0:
293 ; SANDY-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:0.50]
293 ; SANDY-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] sched: [1:1.00]
294294 ; SANDY-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
295 ; SANDY-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [5:0.50]
296 ; SANDY-NEXT: retq # sched: [5:1.00]
295 ; SANDY-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2],ymm0[3] sched: [8:1.00]
296 ; SANDY-NEXT: retq # sched: [1:1.00]
297297 ;
298298 ; HASWELL-LABEL: test_blendpd:
299299 ; HASWELL: # BB#0:
325325 define <8 x float> @test_blendps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
326326 ; SANDY-LABEL: test_blendps:
327327 ; SANDY: # BB#0:
328 ; SANDY-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:0.50]
329 ; SANDY-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [5:0.50]
330 ; SANDY-NEXT: retq # sched: [5:1.00]
328 ; SANDY-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7] sched: [1:1.00]
329 ; SANDY-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2],ymm0[3],mem[4,5,6],ymm0[7] sched: [8:1.00]
330 ; SANDY-NEXT: retq # sched: [1:1.00]
331331 ;
332332 ; HASWELL-LABEL: test_blendps:
333333 ; HASWELL: # BB#0:
355355 define <4 x double> @test_blendvpd(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2, <4 x double> *%a3) {
356356 ; SANDY-LABEL: test_blendvpd:
357357 ; SANDY: # BB#0:
358 ; SANDY-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:1.00]
359 ; SANDY-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [6:1.00]
360 ; SANDY-NEXT: retq # sched: [5:1.00]
358 ; SANDY-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]
359 ; SANDY-NEXT: vblendvpd %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
360 ; SANDY-NEXT: retq # sched: [1:1.00]
361361 ;
362362 ; HASWELL-LABEL: test_blendvpd:
363363 ; HASWELL: # BB#0:
386386 define <8 x float> @test_blendvps(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2, <8 x float> *%a3) {
387387 ; SANDY-LABEL: test_blendvps:
388388 ; SANDY: # BB#0:
389 ; SANDY-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:1.00]
390 ; SANDY-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [6:1.00]
391 ; SANDY-NEXT: retq # sched: [5:1.00]
389 ; SANDY-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # sched: [2:2.00]
390 ; SANDY-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 # sched: [9:2.00]
391 ; SANDY-NEXT: retq # sched: [1:1.00]
392392 ;
393393 ; HASWELL-LABEL: test_blendvps:
394394 ; HASWELL: # BB#0:
417417 define <8 x float> @test_broadcastf128(<4 x float> *%a0) {
418418 ; SANDY-LABEL: test_broadcastf128:
419419 ; SANDY: # BB#0:
420 ; SANDY-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [5:1.00]
421 ; SANDY-NEXT: retq # sched: [5:1.00]
420 ; SANDY-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] sched: [3:1.00]
421 ; SANDY-NEXT: retq # sched: [1:1.00]
422422 ;
423423 ; HASWELL-LABEL: test_broadcastf128:
424424 ; HASWELL: # BB#0:
442442 define <4 x double> @test_broadcastsd_ymm(double *%a0) {
443443 ; SANDY-LABEL: test_broadcastsd_ymm:
444444 ; SANDY: # BB#0:
445 ; SANDY-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [5:1.00]
446 ; SANDY-NEXT: retq # sched: [5:1.00]
445 ; SANDY-NEXT: vbroadcastsd (%rdi), %ymm0 # sched: [7:0.50]
446 ; SANDY-NEXT: retq # sched: [1:1.00]
447447 ;
448448 ; HASWELL-LABEL: test_broadcastsd_ymm:
449449 ; HASWELL: # BB#0:
468468 define <4 x float> @test_broadcastss(float *%a0) {
469469 ; SANDY-LABEL: test_broadcastss:
470470 ; SANDY: # BB#0:
471 ; SANDY-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [4:0.50]
472 ; SANDY-NEXT: retq # sched: [5:1.00]
471 ; SANDY-NEXT: vbroadcastss (%rdi), %xmm0 # sched: [6:0.50]
472 ; SANDY-NEXT: retq # sched: [1:1.00]
473473 ;
474474 ; HASWELL-LABEL: test_broadcastss:
475475 ; HASWELL: # BB#0:
495495 ; SANDY-LABEL: test_broadcastss_ymm:
496496 ; SANDY: # BB#0:
497497 ; SANDY-NEXT: vbroadcastss (%rdi), %ymm0 # sched: [5:1.00]
498 ; SANDY-NEXT: retq # sched: [5:1.00]
498 ; SANDY-NEXT: retq # sched: [1:1.00]
499499 ;
500500 ; HASWELL-LABEL: test_broadcastss_ymm:
501501 ; HASWELL: # BB#0:
521521 ; SANDY-LABEL: test_cmppd:
522522 ; SANDY: # BB#0:
523523 ; SANDY-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
524 ; SANDY-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
525 ; SANDY-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
526 ; SANDY-NEXT: retq # sched: [5:1.00]
524 ; SANDY-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
525 ; SANDY-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:1.00]
526 ; SANDY-NEXT: retq # sched: [1:1.00]
527527 ;
528528 ; HASWELL-LABEL: test_cmppd:
529529 ; HASWELL: # BB#0:
559559 ; SANDY-LABEL: test_cmpps:
560560 ; SANDY: # BB#0:
561561 ; SANDY-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [3:1.00]
562 ; SANDY-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
563 ; SANDY-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
564 ; SANDY-NEXT: retq # sched: [5:1.00]
562 ; SANDY-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
563 ; SANDY-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:1.00]
564 ; SANDY-NEXT: retq # sched: [1:1.00]
565565 ;
566566 ; HASWELL-LABEL: test_cmpps:
567567 ; HASWELL: # BB#0:
597597 ; SANDY-LABEL: test_cvtdq2pd:
598598 ; SANDY: # BB#0:
599599 ; SANDY-NEXT: vcvtdq2pd %xmm0, %ymm0 # sched: [4:1.00]
600 ; SANDY-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [8:1.00]
600 ; SANDY-NEXT: vcvtdq2pd (%rdi), %ymm1 # sched: [10:1.00]
601601 ; SANDY-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
602 ; SANDY-NEXT: retq # sched: [5:1.00]
602 ; SANDY-NEXT: retq # sched: [1:1.00]
603603 ;
604604 ; HASWELL-LABEL: test_cvtdq2pd:
605605 ; HASWELL: # BB#0:
631631 define <8 x float> @test_cvtdq2ps(<8 x i32> %a0, <8 x i32> *%a1) {
632632 ; SANDY-LABEL: test_cvtdq2ps:
633633 ; SANDY: # BB#0:
634 ; SANDY-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [4:1.00]
635 ; SANDY-NEXT: vmovaps (%rdi), %xmm1 # sched: [4:0.50]
636 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm1, %ymm1 # sched: [5:1.00]
637 ; SANDY-NEXT: vcvtdq2ps %ymm1, %ymm1 # sched: [4:1.00]
634 ; SANDY-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [3:1.00]
635 ; SANDY-NEXT: vmovaps (%rdi), %xmm1 # sched: [6:0.50]
636 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm1, %ymm1 # sched: [7:1.00]
637 ; SANDY-NEXT: vcvtdq2ps %ymm1, %ymm1 # sched: [3:1.00]
638638 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
639 ; SANDY-NEXT: retq # sched: [5:1.00]
639 ; SANDY-NEXT: retq # sched: [1:1.00]
640640 ;
641641 ; HASWELL-LABEL: test_cvtdq2ps:
642642 ; HASWELL: # BB#0:
668668 define <8 x i32> @test_cvtpd2dq(<4 x double> %a0, <4 x double> *%a1) {
669669 ; SANDY-LABEL: test_cvtpd2dq:
670670 ; SANDY: # BB#0:
671 ; SANDY-NEXT: vcvttpd2dq %ymm0, %xmm0 # sched: [3:1.00]
672 ; SANDY-NEXT: vcvttpd2dqy (%rdi), %xmm1 # sched: [7:1.00]
671 ; SANDY-NEXT: vcvttpd2dq %ymm0, %xmm0 # sched: [4:1.00]
672 ; SANDY-NEXT: vcvttpd2dqy (%rdi), %xmm1 # sched: [11:1.00]
673673 ; SANDY-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [1:1.00]
674 ; SANDY-NEXT: retq # sched: [5:1.00]
674 ; SANDY-NEXT: retq # sched: [1:1.00]
675675 ;
676676 ; HASWELL-LABEL: test_cvtpd2dq:
677677 ; HASWELL: # BB#0:
703703 define <8 x float> @test_cvtpd2ps(<4 x double> %a0, <4 x double> *%a1) {
704704 ; SANDY-LABEL: test_cvtpd2ps:
705705 ; SANDY: # BB#0:
706 ; SANDY-NEXT: vcvtpd2ps %ymm0, %xmm0 # sched: [3:1.00]
707 ; SANDY-NEXT: vcvtpd2psy (%rdi), %xmm1 # sched: [7:1.00]
706 ; SANDY-NEXT: vcvtpd2ps %ymm0, %xmm0 # sched: [4:1.00]
707 ; SANDY-NEXT: vcvtpd2psy (%rdi), %xmm1 # sched: [11:1.00]
708708 ; SANDY-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 # sched: [1:1.00]
709 ; SANDY-NEXT: retq # sched: [5:1.00]
709 ; SANDY-NEXT: retq # sched: [1:1.00]
710710 ;
711711 ; HASWELL-LABEL: test_cvtpd2ps:
712712 ; HASWELL: # BB#0:
740740 ; SANDY: # BB#0:
741741 ; SANDY-NEXT: vcvttps2dq %ymm0, %ymm0 # sched: [3:1.00]
742742 ; SANDY-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [7:1.00]
743 ; SANDY-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
744 ; SANDY-NEXT: retq # sched: [5:1.00]
743 ; SANDY-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
744 ; SANDY-NEXT: retq # sched: [1:1.00]
745745 ;
746746 ; HASWELL-LABEL: test_cvtps2dq:
747747 ; HASWELL: # BB#0:
773773 define <4 x double> @test_divpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
774774 ; SANDY-LABEL: test_divpd:
775775 ; SANDY: # BB#0:
776 ; SANDY-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [12:1.00]
777 ; SANDY-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [16:1.00]
778 ; SANDY-NEXT: retq # sched: [5:1.00]
776 ; SANDY-NEXT: vdivpd %ymm1, %ymm0, %ymm0 # sched: [45:3.00]
777 ; SANDY-NEXT: vdivpd (%rdi), %ymm0, %ymm0 # sched: [52:3.00]
778 ; SANDY-NEXT: retq # sched: [1:1.00]
779779 ;
780780 ; HASWELL-LABEL: test_divpd:
781781 ; HASWELL: # BB#0:
803803 define <8 x float> @test_divps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
804804 ; SANDY-LABEL: test_divps:
805805 ; SANDY: # BB#0:
806 ; SANDY-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [12:1.00]
807 ; SANDY-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [16:1.00]
808 ; SANDY-NEXT: retq # sched: [5:1.00]
806 ; SANDY-NEXT: vdivps %ymm1, %ymm0, %ymm0 # sched: [29:3.00]
807 ; SANDY-NEXT: vdivps (%rdi), %ymm0, %ymm0 # sched: [36:3.00]
808 ; SANDY-NEXT: retq # sched: [1:1.00]
809809 ;
810810 ; HASWELL-LABEL: test_divps:
811811 ; HASWELL: # BB#0:
833833 define <8 x float> @test_dpps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
834834 ; SANDY-LABEL: test_dpps:
835835 ; SANDY: # BB#0:
836 ; SANDY-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
836 ; SANDY-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:2.00]
837837 ; SANDY-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
838 ; SANDY-NEXT: retq # sched: [5:1.00]
838 ; SANDY-NEXT: retq # sched: [1:1.00]
839839 ;
840840 ; HASWELL-LABEL: test_dpps:
841841 ; HASWELL: # BB#0:
865865 ; SANDY-LABEL: test_extractf128:
866866 ; SANDY: # BB#0:
867867 ; SANDY-NEXT: vextractf128 $1, %ymm0, %xmm0 # sched: [1:1.00]
868 ; SANDY-NEXT: vextractf128 $1, %ymm1, (%rdi) # sched: [1:1.00]
868 ; SANDY-NEXT: vextractf128 $1, %ymm1, (%rdi) # sched: [5:1.00]
869869 ; SANDY-NEXT: vzeroupper # sched: [?:0.000000e+00]
870 ; SANDY-NEXT: retq # sched: [5:1.00]
870 ; SANDY-NEXT: retq # sched: [1:1.00]
871871 ;
872872 ; HASWELL-LABEL: test_extractf128:
873873 ; HASWELL: # BB#0:
899899 ; SANDY: # BB#0:
900900 ; SANDY-NEXT: vhaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
901901 ; SANDY-NEXT: vhaddpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
902 ; SANDY-NEXT: retq # sched: [5:1.00]
902 ; SANDY-NEXT: retq # sched: [1:1.00]
903903 ;
904904 ; HASWELL-LABEL: test_haddpd:
905905 ; HASWELL: # BB#0:
928928 define <8 x float> @test_haddps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
929929 ; SANDY-LABEL: test_haddps:
930930 ; SANDY: # BB#0:
931 ; SANDY-NEXT: vhaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
932 ; SANDY-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
933 ; SANDY-NEXT: retq # sched: [5:1.00]
931 ; SANDY-NEXT: vhaddps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
932 ; SANDY-NEXT: vhaddps (%rdi), %ymm0, %ymm0 # sched: [12:2.00]
933 ; SANDY-NEXT: retq # sched: [1:1.00]
934934 ;
935935 ; HASWELL-LABEL: test_haddps:
936936 ; HASWELL: # BB#0:
959959 define <4 x double> @test_hsubpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
960960 ; SANDY-LABEL: test_hsubpd:
961961 ; SANDY: # BB#0:
962 ; SANDY-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
963 ; SANDY-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
964 ; SANDY-NEXT: retq # sched: [5:1.00]
962 ; SANDY-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
963 ; SANDY-NEXT: vhsubpd (%rdi), %ymm0, %ymm0 # sched: [12:2.00]
964 ; SANDY-NEXT: retq # sched: [1:1.00]
965965 ;
966966 ; HASWELL-LABEL: test_hsubpd:
967967 ; HASWELL: # BB#0:
990990 define <8 x float> @test_hsubps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
991991 ; SANDY-LABEL: test_hsubps:
992992 ; SANDY: # BB#0:
993 ; SANDY-NEXT: vhsubps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
994 ; SANDY-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
995 ; SANDY-NEXT: retq # sched: [5:1.00]
993 ; SANDY-NEXT: vhsubps %ymm1, %ymm0, %ymm0 # sched: [5:2.00]
994 ; SANDY-NEXT: vhsubps (%rdi), %ymm0, %ymm0 # sched: [12:2.00]
995 ; SANDY-NEXT: retq # sched: [1:1.00]
996996 ;
997997 ; HASWELL-LABEL: test_hsubps:
998998 ; HASWELL: # BB#0:
10221022 ; SANDY-LABEL: test_insertf128:
10231023 ; SANDY: # BB#0:
10241024 ; SANDY-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 # sched: [1:1.00]
1025 ; SANDY-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
1025 ; SANDY-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
10261026 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
1027 ; SANDY-NEXT: retq # sched: [5:1.00]
1027 ; SANDY-NEXT: retq # sched: [1:1.00]
10281028 ;
10291029 ; HASWELL-LABEL: test_insertf128:
10301030 ; HASWELL: # BB#0:
10581058 define <32 x i8> @test_lddqu(i8* %a0) {
10591059 ; SANDY-LABEL: test_lddqu:
10601060 ; SANDY: # BB#0:
1061 ; SANDY-NEXT: vlddqu (%rdi), %ymm0 # sched: [4:0.50]
1062 ; SANDY-NEXT: retq # sched: [5:1.00]
1061 ; SANDY-NEXT: vlddqu (%rdi), %ymm0 # sched: [6:0.50]
1062 ; SANDY-NEXT: retq # sched: [1:1.00]
10631063 ;
10641064 ; HASWELL-LABEL: test_lddqu:
10651065 ; HASWELL: # BB#0:
10831083 define <2 x double> @test_maskmovpd(i8* %a0, <2 x i64> %a1, <2 x double> %a2) {
10841084 ; SANDY-LABEL: test_maskmovpd:
10851085 ; SANDY: # BB#0:
1086 ; SANDY-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [?:0.000000e+00]
1087 ; SANDY-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [?:0.000000e+00]
1086 ; SANDY-NEXT: vmaskmovpd (%rdi), %xmm0, %xmm2 # sched: [8:2.00]
1087 ; SANDY-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
10881088 ; SANDY-NEXT: vmovapd %xmm2, %xmm0 # sched: [1:1.00]
1089 ; SANDY-NEXT: retq # sched: [5:1.00]
1089 ; SANDY-NEXT: retq # sched: [1:1.00]
10901090 ;
10911091 ; HASWELL-LABEL: test_maskmovpd:
10921092 ; HASWELL: # BB#0:
11181118 define <4 x double> @test_maskmovpd_ymm(i8* %a0, <4 x i64> %a1, <4 x double> %a2) {
11191119 ; SANDY-LABEL: test_maskmovpd_ymm:
11201120 ; SANDY: # BB#0:
1121 ; SANDY-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [?:0.000000e+00]
1121 ; SANDY-NEXT: vmaskmovpd (%rdi), %ymm0, %ymm2 # sched: [5:1.00]
11221122 ; SANDY-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi) # sched: [?:0.000000e+00]
11231123 ; SANDY-NEXT: vmovapd %ymm2, %ymm0 # sched: [1:1.00]
1124 ; SANDY-NEXT: retq # sched: [5:1.00]
1124 ; SANDY-NEXT: retq # sched: [1:1.00]
11251125 ;
11261126 ; HASWELL-LABEL: test_maskmovpd_ymm:
11271127 ; HASWELL: # BB#0:
11531153 define <4 x float> @test_maskmovps(i8* %a0, <4 x i32> %a1, <4 x float> %a2) {
11541154 ; SANDY-LABEL: test_maskmovps:
11551155 ; SANDY: # BB#0:
1156 ; SANDY-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [?:0.000000e+00]
1157 ; SANDY-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [?:0.000000e+00]
1156 ; SANDY-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2 # sched: [8:2.00]
1157 ; SANDY-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi) # sched: [5:1.00]
11581158 ; SANDY-NEXT: vmovaps %xmm2, %xmm0 # sched: [1:1.00]
1159 ; SANDY-NEXT: retq # sched: [5:1.00]
1159 ; SANDY-NEXT: retq # sched: [1:1.00]
11601160 ;
11611161 ; HASWELL-LABEL: test_maskmovps:
11621162 ; HASWELL: # BB#0:
11881188 define <8 x float> @test_maskmovps_ymm(i8* %a0, <8 x i32> %a1, <8 x float> %a2) {
11891189 ; SANDY-LABEL: test_maskmovps_ymm:
11901190 ; SANDY: # BB#0:
1191 ; SANDY-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [?:0.000000e+00]
1191 ; SANDY-NEXT: vmaskmovps (%rdi), %ymm0, %ymm2 # sched: [1:0.50]
11921192 ; SANDY-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi) # sched: [?:0.000000e+00]
11931193 ; SANDY-NEXT: vmovaps %ymm2, %ymm0 # sched: [1:1.00]
1194 ; SANDY-NEXT: retq # sched: [5:1.00]
1194 ; SANDY-NEXT: retq # sched: [1:1.00]
11951195 ;
11961196 ; HASWELL-LABEL: test_maskmovps_ymm:
11971197 ; HASWELL: # BB#0:
12241224 ; SANDY-LABEL: test_maxpd:
12251225 ; SANDY: # BB#0:
12261226 ; SANDY-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1227 ; SANDY-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
1228 ; SANDY-NEXT: retq # sched: [5:1.00]
1227 ; SANDY-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
1228 ; SANDY-NEXT: retq # sched: [1:1.00]
12291229 ;
12301230 ; HASWELL-LABEL: test_maxpd:
12311231 ; HASWELL: # BB#0:
12551255 ; SANDY-LABEL: test_maxps:
12561256 ; SANDY: # BB#0:
12571257 ; SANDY-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1258 ; SANDY-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
1259 ; SANDY-NEXT: retq # sched: [5:1.00]
1258 ; SANDY-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [10:1.00]
1259 ; SANDY-NEXT: retq # sched: [1:1.00]
12601260 ;
12611261 ; HASWELL-LABEL: test_maxps:
12621262 ; HASWELL: # BB#0:
12871287 ; SANDY: # BB#0:
12881288 ; SANDY-NEXT: vminpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
12891289 ; SANDY-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
1290 ; SANDY-NEXT: retq # sched: [5:1.00]
1290 ; SANDY-NEXT: retq # sched: [1:1.00]
12911291 ;
12921292 ; HASWELL-LABEL: test_minpd:
12931293 ; HASWELL: # BB#0:
13181318 ; SANDY: # BB#0:
13191319 ; SANDY-NEXT: vminps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
13201320 ; SANDY-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
1321 ; SANDY-NEXT: retq # sched: [5:1.00]
1321 ; SANDY-NEXT: retq # sched: [1:1.00]
13221322 ;
13231323 ; HASWELL-LABEL: test_minps:
13241324 ; HASWELL: # BB#0:
13471347 define <4 x double> @test_movapd(<4 x double> *%a0, <4 x double> *%a1) {
13481348 ; SANDY-LABEL: test_movapd:
13491349 ; SANDY: # BB#0:
1350 ; SANDY-NEXT: vmovapd (%rdi), %ymm0 # sched: [4:0.50]
1350 ; SANDY-NEXT: vmovapd (%rdi), %ymm0 # sched: [7:0.50]
13511351 ; SANDY-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1352 ; SANDY-NEXT: vmovapd %ymm0, (%rsi) # sched: [1:1.00]
1353 ; SANDY-NEXT: retq # sched: [5:1.00]
1352 ; SANDY-NEXT: vmovapd %ymm0, (%rsi) # sched: [5:1.00]
1353 ; SANDY-NEXT: retq # sched: [1:1.00]
13541354 ;
13551355 ; HASWELL-LABEL: test_movapd:
13561356 ; HASWELL: # BB#0:
13811381 define <8 x float> @test_movaps(<8 x float> *%a0, <8 x float> *%a1) {
13821382 ; SANDY-LABEL: test_movaps:
13831383 ; SANDY: # BB#0:
1384 ; SANDY-NEXT: vmovaps (%rdi), %ymm0 # sched: [4:0.50]
1384 ; SANDY-NEXT: vmovaps (%rdi), %ymm0 # sched: [7:0.50]
13851385 ; SANDY-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1386 ; SANDY-NEXT: vmovaps %ymm0, (%rsi) # sched: [1:1.00]
1387 ; SANDY-NEXT: retq # sched: [5:1.00]
1386 ; SANDY-NEXT: vmovaps %ymm0, (%rsi) # sched: [5:1.00]
1387 ; SANDY-NEXT: retq # sched: [1:1.00]
13881388 ;
13891389 ; HASWELL-LABEL: test_movaps:
13901390 ; HASWELL: # BB#0:
14161416 ; SANDY-LABEL: test_movddup:
14171417 ; SANDY: # BB#0:
14181418 ; SANDY-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:1.00]
1419 ; SANDY-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [4:0.50]
1419 ; SANDY-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [7:0.50]
14201420 ; SANDY-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1421 ; SANDY-NEXT: retq # sched: [5:1.00]
1421 ; SANDY-NEXT: retq # sched: [1:1.00]
14221422 ;
14231423 ; HASWELL-LABEL: test_movddup:
14241424 ; HASWELL: # BB#0:
14501450 define i32 @test_movmskpd(<4 x double> %a0) {
14511451 ; SANDY-LABEL: test_movmskpd:
14521452 ; SANDY: # BB#0:
1453 ; SANDY-NEXT: vmovmskpd %ymm0, %eax # sched: [1:0.33]
1453 ; SANDY-NEXT: vmovmskpd %ymm0, %eax # sched: [2:1.00]
14541454 ; SANDY-NEXT: vzeroupper # sched: [?:0.000000e+00]
1455 ; SANDY-NEXT: retq # sched: [5:1.00]
1455 ; SANDY-NEXT: retq # sched: [1:1.00]
14561456 ;
14571457 ; HASWELL-LABEL: test_movmskpd:
14581458 ; HASWELL: # BB#0:
14781478 define i32 @test_movmskps(<8 x float> %a0) {
14791479 ; SANDY-LABEL: test_movmskps:
14801480 ; SANDY: # BB#0:
1481 ; SANDY-NEXT: vmovmskps %ymm0, %eax # sched: [1:0.33]
1481 ; SANDY-NEXT: vmovmskps %ymm0, %eax # sched: [3:1.00]
14821482 ; SANDY-NEXT: vzeroupper # sched: [?:0.000000e+00]
1483 ; SANDY-NEXT: retq # sched: [5:1.00]
1483 ; SANDY-NEXT: retq # sched: [1:1.00]
14841484 ;
14851485 ; HASWELL-LABEL: test_movmskps:
14861486 ; HASWELL: # BB#0:
15071507 ; SANDY-LABEL: test_movntpd:
15081508 ; SANDY: # BB#0:
15091509 ; SANDY-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1510 ; SANDY-NEXT: vmovntpd %ymm0, (%rdi) # sched: [1:1.00]
1511 ; SANDY-NEXT: retq # sched: [5:1.00]
1510 ; SANDY-NEXT: vmovntpd %ymm0, (%rdi) # sched: [5:1.00]
1511 ; SANDY-NEXT: retq # sched: [1:1.00]
15121512 ;
15131513 ; HASWELL-LABEL: test_movntpd:
15141514 ; HASWELL: # BB#0:
15361536 ; SANDY-LABEL: test_movntps:
15371537 ; SANDY: # BB#0:
15381538 ; SANDY-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1539 ; SANDY-NEXT: vmovntps %ymm0, (%rdi) # sched: [1:1.00]
1540 ; SANDY-NEXT: retq # sched: [5:1.00]
1539 ; SANDY-NEXT: vmovntps %ymm0, (%rdi) # sched: [5:1.00]
1540 ; SANDY-NEXT: retq # sched: [1:1.00]
15411541 ;
15421542 ; HASWELL-LABEL: test_movntps:
15431543 ; HASWELL: # BB#0:
15651565 ; SANDY-LABEL: test_movshdup:
15661566 ; SANDY: # BB#0:
15671567 ; SANDY-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:1.00]
1568 ; SANDY-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [4:0.50]
1568 ; SANDY-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [7:0.50]
15691569 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1570 ; SANDY-NEXT: retq # sched: [5:1.00]
1570 ; SANDY-NEXT: retq # sched: [1:1.00]
15711571 ;
15721572 ; HASWELL-LABEL: test_movshdup:
15731573 ; HASWELL: # BB#0:
16001600 ; SANDY-LABEL: test_movsldup:
16011601 ; SANDY: # BB#0:
16021602 ; SANDY-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:1.00]
1603 ; SANDY-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [4:0.50]
1603 ; SANDY-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [7:0.50]
16041604 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1605 ; SANDY-NEXT: retq # sched: [5:1.00]
1605 ; SANDY-NEXT: retq # sched: [1:1.00]
16061606 ;
16071607 ; HASWELL-LABEL: test_movsldup:
16081608 ; HASWELL: # BB#0:
16341634 define <4 x double> @test_movupd(<4 x double> *%a0, <4 x double> *%a1) {
16351635 ; SANDY-LABEL: test_movupd:
16361636 ; SANDY: # BB#0:
1637 ; SANDY-NEXT: vmovups (%rdi), %xmm0 # sched: [4:0.50]
1638 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 # sched: [5:1.00]
1637 ; SANDY-NEXT: vmovups (%rdi), %xmm0 # sched: [6:0.50]
1638 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 # sched: [7:1.00]
16391639 ; SANDY-NEXT: vaddpd %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1640 ; SANDY-NEXT: vextractf128 $1, %ymm0, 16(%rsi) # sched: [1:1.00]
1641 ; SANDY-NEXT: vmovupd %xmm0, (%rsi) # sched: [1:1.00]
1642 ; SANDY-NEXT: retq # sched: [5:1.00]
1640 ; SANDY-NEXT: vextractf128 $1, %ymm0, 16(%rsi) # sched: [5:1.00]
1641 ; SANDY-NEXT: vmovupd %xmm0, (%rsi) # sched: [5:1.00]
1642 ; SANDY-NEXT: retq # sched: [1:1.00]
16431643 ;
16441644 ; HASWELL-LABEL: test_movupd:
16451645 ; HASWELL: # BB#0:
16701670 define <8 x float> @test_movups(<8 x float> *%a0, <8 x float> *%a1) {
16711671 ; SANDY-LABEL: test_movups:
16721672 ; SANDY: # BB#0:
1673 ; SANDY-NEXT: vmovups (%rdi), %xmm0 # sched: [4:0.50]
1674 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 # sched: [5:1.00]
1673 ; SANDY-NEXT: vmovups (%rdi), %xmm0 # sched: [6:0.50]
1674 ; SANDY-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 # sched: [7:1.00]
16751675 ; SANDY-NEXT: vaddps %ymm0, %ymm0, %ymm0 # sched: [3:1.00]
1676 ; SANDY-NEXT: vextractf128 $1, %ymm0, 16(%rsi) # sched: [1:1.00]
1677 ; SANDY-NEXT: vmovups %xmm0, (%rsi) # sched: [1:1.00]
1678 ; SANDY-NEXT: retq # sched: [5:1.00]
1676 ; SANDY-NEXT: vextractf128 $1, %ymm0, 16(%rsi) # sched: [5:1.00]
1677 ; SANDY-NEXT: vmovups %xmm0, (%rsi) # sched: [5:1.00]
1678 ; SANDY-NEXT: retq # sched: [1:1.00]
16791679 ;
16801680 ; HASWELL-LABEL: test_movups:
16811681 ; HASWELL: # BB#0:
17071707 ; SANDY-LABEL: test_mulpd:
17081708 ; SANDY: # BB#0:
17091709 ; SANDY-NEXT: vmulpd %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
1710 ; SANDY-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [9:1.00]
1711 ; SANDY-NEXT: retq # sched: [5:1.00]
1710 ; SANDY-NEXT: vmulpd (%rdi), %ymm0, %ymm0 # sched: [12:1.00]
1711 ; SANDY-NEXT: retq # sched: [1:1.00]
17121712 ;
17131713 ; HASWELL-LABEL: test_mulpd:
17141714 ; HASWELL: # BB#0:
17371737 ; SANDY-LABEL: test_mulps:
17381738 ; SANDY: # BB#0:
17391739 ; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0 # sched: [5:1.00]
1740 ; SANDY-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [9:1.00]
1741 ; SANDY-NEXT: retq # sched: [5:1.00]
1740 ; SANDY-NEXT: vmulps (%rdi), %ymm0, %ymm0 # sched: [12:1.00]
1741 ; SANDY-NEXT: retq # sched: [1:1.00]
17421742 ;
17431743 ; HASWELL-LABEL: test_mulps:
17441744 ; HASWELL: # BB#0:
17661766 define <4 x double> @orpd(<4 x double> %a0, <4 x double> %a1, <4 x double> *%a2) {
17671767 ; SANDY-LABEL: orpd:
17681768 ; SANDY: # BB#0:
1769 ; SANDY-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
1770 ; SANDY-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
1769 ; SANDY-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
1770 ; SANDY-NEXT: vorpd (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
17711771 ; SANDY-NEXT: vaddpd %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
1772 ; SANDY-NEXT: retq # sched: [5:1.00]
1772 ; SANDY-NEXT: retq # sched: [1:1.00]
17731773 ;
17741774 ; HASWELL-LABEL: orpd:
17751775 ; HASWELL: # BB#0:
18051805 define <8 x float> @test_orps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2) {
18061806 ; SANDY-LABEL: test_orps:
18071807 ; SANDY: # BB#0:
1808 ; SANDY-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
1809 ; SANDY-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [5:0.50]
1808 ; SANDY-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
1809 ; SANDY-NEXT: vorps (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
18101810 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]
1811 ; SANDY-NEXT: retq # sched: [5:1.00]
1811 ; SANDY-NEXT: retq # sched: [1:1.00]
18121812 ;
18131813 ; HASWELL-LABEL: test_orps:
18141814 ; HASWELL: # BB#0:
18451845 ; SANDY-LABEL: test_permilpd:
18461846 ; SANDY: # BB#0:
18471847 ; SANDY-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] sched: [1:1.00]
1848 ; SANDY-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [5:1.00]
1848 ; SANDY-NEXT: vpermilpd {{.*#+}} xmm1 = mem[1,0] sched: [7:1.00]
18491849 ; SANDY-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
1850 ; SANDY-NEXT: retq # sched: [5:1.00]
1850 ; SANDY-NEXT: retq # sched: [1:1.00]
18511851 ;
18521852 ; HASWELL-LABEL: test_permilpd:
18531853 ; HASWELL: # BB#0:
18791879 define <4 x double> @test_permilpd_ymm(<4 x double> %a0, <4 x double> *%a1) {
18801880 ; SANDY-LABEL: test_permilpd_ymm:
18811881 ; SANDY: # BB#0:
1882 ; SANDY-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [1:1.00]
1882 ; SANDY-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,3] sched: [8:1.00]
18831883 ; SANDY-NEXT: vpermilpd {{.*#+}} ymm1 = mem[1,0,2,3] sched: [5:1.00]
18841884 ; SANDY-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1885 ; SANDY-NEXT: retq # sched: [5:1.00]
1885 ; SANDY-NEXT: retq # sched: [1:1.00]
18861886 ;
18871887 ; HASWELL-LABEL: test_permilpd_ymm:
18881888 ; HASWELL: # BB#0:
19151915 ; SANDY-LABEL: test_permilps:
19161916 ; SANDY: # BB#0:
19171917 ; SANDY-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0] sched: [1:1.00]
1918 ; SANDY-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [5:1.00]
1918 ; SANDY-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,2,1,0] sched: [7:1.00]
19191919 ; SANDY-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
1920 ; SANDY-NEXT: retq # sched: [5:1.00]
1920 ; SANDY-NEXT: retq # sched: [1:1.00]
19211921 ;
19221922 ; HASWELL-LABEL: test_permilps:
19231923 ; HASWELL: # BB#0:
19491949 define <8 x float> @test_permilps_ymm(<8 x float> %a0, <8 x float> *%a1) {
19501950 ; SANDY-LABEL: test_permilps_ymm:
19511951 ; SANDY: # BB#0:
1952 ; SANDY-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [1:1.00]
1952 ; SANDY-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4] sched: [8:1.00]
19531953 ; SANDY-NEXT: vpermilps {{.*#+}} ymm1 = mem[3,2,1,0,7,6,5,4] sched: [5:1.00]
19541954 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
1955 ; SANDY-NEXT: retq # sched: [5:1.00]
1955 ; SANDY-NEXT: retq # sched: [1:1.00]
19561956 ;
19571957 ; HASWELL-LABEL: test_permilps_ymm:
19581958 ; HASWELL: # BB#0:
19851985 ; SANDY-LABEL: test_permilvarpd:
19861986 ; SANDY: # BB#0:
19871987 ; SANDY-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
1988 ; SANDY-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
1989 ; SANDY-NEXT: retq # sched: [5:1.00]
1988 ; SANDY-NEXT: vpermilpd (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
1989 ; SANDY-NEXT: retq # sched: [1:1.00]
19901990 ;
19911991 ; HASWELL-LABEL: test_permilvarpd:
19921992 ; HASWELL: # BB#0:
20172017 ; SANDY: # BB#0:
20182018 ; SANDY-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
20192019 ; SANDY-NEXT: vpermilpd (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
2020 ; SANDY-NEXT: retq # sched: [5:1.00]
2020 ; SANDY-NEXT: retq # sched: [1:1.00]
20212021 ;
20222022 ; HASWELL-LABEL: test_permilvarpd_ymm:
20232023 ; HASWELL: # BB#0:
20472047 ; SANDY-LABEL: test_permilvarps:
20482048 ; SANDY: # BB#0:
20492049 ; SANDY-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
2050 ; SANDY-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [5:1.00]
2051 ; SANDY-NEXT: retq # sched: [5:1.00]
2050 ; SANDY-NEXT: vpermilps (%rdi), %xmm0, %xmm0 # sched: [1:1.00]
2051 ; SANDY-NEXT: retq # sched: [1:1.00]
20522052 ;
20532053 ; HASWELL-LABEL: test_permilvarps:
20542054 ; HASWELL: # BB#0:
20792079 ; SANDY: # BB#0:
20802080 ; SANDY-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # sched: [1:1.00]
20812081 ; SANDY-NEXT: vpermilps (%rdi), %ymm0, %ymm0 # sched: [5:1.00]
2082 ; SANDY-NEXT: retq # sched: [5:1.00]
2082 ; SANDY-NEXT: retq # sched: [1:1.00]
20832083 ;
20842084 ; HASWELL-LABEL: test_permilvarps_ymm:
20852085 ; HASWELL: # BB#0:
21112111 ; SANDY-NEXT: vrcpps %ymm0, %ymm0 # sched: [5:1.00]
21122112 ; SANDY-NEXT: vrcpps (%rdi), %ymm1 # sched: [9:1.00]
21132113 ; SANDY-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
2114 ; SANDY-NEXT: retq # sched: [5:1.00]
2114 ; SANDY-NEXT: retq # sched: [1:1.00]
21152115 ;