llvm.org GIT mirror llvm / 33dd8ea
[ARM] GlobalISel: Use TableGen instruction selector Emit and use the TableGen instruction selector for ARM. At the moment, this allows us to remove the hand-written code for selecting G_SDIV and G_UDIV. Future commits will focus on increasing the code coverage for it and removing more dead code from the current instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301905 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
6 changed file(s) with 69 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
4646 FunctionPass *createThumb2SizeReductionPass(
4747 std::function Ftor = nullptr);
4848 InstructionSelector *
49 createARMInstructionSelector(const ARMSubtarget &STI,
49 createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
5050 const ARMRegisterBankInfo &RBI);
5151
5252 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
316316 "NegativeImmediates">;
317317
318318 // FIXME: Eventually this will be just "hasV6T2Ops".
319 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
320 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
319 let RecomputePerFunction = 1 in {
320 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
321 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
322 }
321323 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
322324 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
323325
344346 def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
345347 "Subtarget->useNEONForSinglePrecisionFP()">;
346348
347 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
348 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
349 let RecomputePerFunction = 1 in {
350 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
351 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
352 }
349353
350354 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
351355
2626 #endif
2727
2828 namespace {
29
30 #define GET_GLOBALISEL_PREDICATE_BITSET
31 #include "ARMGenGlobalISel.inc"
32 #undef GET_GLOBALISEL_PREDICATE_BITSET
33
2934 class ARMInstructionSelector : public InstructionSelector {
3035 public:
31 ARMInstructionSelector(const ARMSubtarget &STI,
36 ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
3237 const ARMRegisterBankInfo &RBI);
3338
3439 bool select(MachineInstr &I) const override;
3540
3641 private:
42 bool selectImpl(MachineInstr &I) const;
43
3744 const ARMBaseInstrInfo &TII;
3845 const ARMBaseRegisterInfo &TRI;
46 const ARMBaseTargetMachine &TM;
3947 const ARMRegisterBankInfo &RBI;
48 const ARMSubtarget &STI;
49
50 #define GET_GLOBALISEL_PREDICATES_DECL
51 #include "ARMGenGlobalISel.inc"
52 #undef GET_GLOBALISEL_PREDICATES_DECL
53
54 // We declare the temporaries used by selectImpl() in the class to minimize the
55 // cost of constructing placeholder values.
56 #define GET_GLOBALISEL_TEMPORARIES_DECL
57 #include "ARMGenGlobalISel.inc"
58 #undef GET_GLOBALISEL_TEMPORARIES_DECL
4059 };
4160 } // end anonymous namespace
4261
4362 namespace llvm {
4463 InstructionSelector *
45 createARMInstructionSelector(const ARMSubtarget &STI,
64 createARMInstructionSelector(const ARMBaseTargetMachine &TM,
65 const ARMSubtarget &STI,
4666 const ARMRegisterBankInfo &RBI) {
47 return new ARMInstructionSelector(STI, RBI);
48 }
49 }
50
51 ARMInstructionSelector::ARMInstructionSelector(const ARMSubtarget &STI,
67 return new ARMInstructionSelector(TM, STI, RBI);
68 }
69 }
70
71 unsigned zero_reg = 0;
72
73 #define GET_GLOBALISEL_IMPL
74 #include "ARMGenGlobalISel.inc"
75 #undef GET_GLOBALISEL_IMPL
76
77 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
78 const ARMSubtarget &STI,
5279 const ARMRegisterBankInfo &RBI)
5380 : InstructionSelector(), TII(*STI.getInstrInfo()),
54 TRI(*STI.getRegisterInfo()), RBI(RBI) {}
81 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
82 #define GET_GLOBALISEL_PREDICATES_INIT
83 #include "ARMGenGlobalISel.inc"
84 #undef GET_GLOBALISEL_PREDICATES_INIT
85 #define GET_GLOBALISEL_TEMPORARIES_INIT
86 #include "ARMGenGlobalISel.inc"
87 #undef GET_GLOBALISEL_TEMPORARIES_INIT
88 {
89 }
5590
5691 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
5792 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
254289 return true;
255290 }
256291
292 if (selectImpl(I))
293 return true;
294
257295 MachineInstrBuilder MIB{MF, I};
258296 bool isSExt = false;
259297
354392 }
355393 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
356394 break;
357 case G_SDIV:
358 assert(TII.getSubtarget().hasDivideInARMMode() && "Unsupported operation");
359 I.setDesc(TII.get(ARM::SDIV));
360 MIB.add(predOps(ARMCC::AL));
361 break;
362 case G_UDIV:
363 assert(TII.getSubtarget().hasDivideInARMMode() && "Unsupported operation");
364 I.setDesc(TII.get(ARM::UDIV));
365 MIB.add(predOps(ARMCC::AL));
366 break;
367395 case G_FADD:
368396 if (!selectFAdd(MIB, TII, MRI))
369397 return false;
337337 // FIXME: At this point, we can't rely on Subtarget having RBI.
338338 // It's awkward to mix passing RBI and the Subtarget; should we pass
339339 // TII/TRI as well?
340 GISel->InstSelector.reset(createARMInstructionSelector(*I, *RBI));
340 GISel->InstSelector.reset(createARMInstructionSelector(*this, *I, *RBI));
341341
342342 GISel->RegBankInfo.reset(RBI);
343343 #endif
0 set(LLVM_TARGET_DEFINITIONS ARM.td)
11
2 tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
2 if(LLVM_BUILD_GLOBAL_ISEL)
3 tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
4 tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
5 endif()
36 tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
47 tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
58 tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
853853 }
854854
855855 void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override {
856 OS << " MIB.addReg(" << RegisterDef->getValueAsString("Namespace")
856 OS << " MIB.addReg(" << (RegisterDef->getValue("Namespace")
857 ? RegisterDef->getValueAsString("Namespace")
858 : "")
857859 << "::" << RegisterDef->getName() << ");\n";
858860 }
859861 };
986988 << ");\n";
987989
988990 for (auto Def : I->ImplicitDefs) {
989 auto Namespace = Def->getValueAsString("Namespace");
991 auto Namespace = Def->getValue("Namespace")
992 ? Def->getValueAsString("Namespace")
993 : "";
990994 OS << " MIB.addDef(" << Namespace << "::" << Def->getName()
991995 << ", RegState::Implicit);\n";
992996 }
993997 for (auto Use : I->ImplicitUses) {
994 auto Namespace = Use->getValueAsString("Namespace");
998 auto Namespace = Use->getValue("Namespace")
999 ? Use->getValueAsString("Namespace")
1000 : "";
9951001 OS << " MIB.addUse(" << Namespace << "::" << Use->getName()
9961002 << ", RegState::Implicit);\n";
9971003 }