llvm.org GIT mirror llvm / 334c264
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 11 years ago
12 changed file(s) with 1426 addition(s) and 1127 deletion(s). Raw diff Collapse all Expand all
0 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMBaseInstrInfo.h"
14 #include "ARM.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/LiveVariables.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/Target/TargetAsmInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 using namespace llvm;
26
27 static cl::opt
28 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
30
31 static inline
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
34 }
35
36 static inline
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
38 return MIB.addReg(0);
39 }
40
41 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
43 }
44
45 MachineInstr *
46 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
47 MachineBasicBlock::iterator &MBBI,
48 LiveVariables *LV) const {
49 if (!EnableARM3Addr)
50 return NULL;
51
52 MachineInstr *MI = MBBI;
53 MachineFunction &MF = *MI->getParent()->getParent();
54 unsigned TSFlags = MI->getDesc().TSFlags;
55 bool isPre = false;
56 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
57 default: return NULL;
58 case ARMII::IndexModePre:
59 isPre = true;
60 break;
61 case ARMII::IndexModePost:
62 break;
63 }
64
65 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
66 // operation.
67 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
68 if (MemOpc == 0)
69 return NULL;
70
71 MachineInstr *UpdateMI = NULL;
72 MachineInstr *MemMI = NULL;
73 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
74 const TargetInstrDesc &TID = MI->getDesc();
75 unsigned NumOps = TID.getNumOperands();
76 bool isLoad = !TID.mayStore();
77 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
78 const MachineOperand &Base = MI->getOperand(2);
79 const MachineOperand &Offset = MI->getOperand(NumOps-3);
80 unsigned WBReg = WB.getReg();
81 unsigned BaseReg = Base.getReg();
82 unsigned OffReg = Offset.getReg();
83 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
84 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
85 switch (AddrMode) {
86 default:
87 assert(false && "Unknown indexed op!");
88 return NULL;
89 case ARMII::AddrMode2: {
90 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
91 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
92 if (OffReg == 0) {
93 int SOImmVal = ARM_AM::getSOImmVal(Amt);
94 if (SOImmVal == -1)
95 // Can't encode it in a so_imm operand. This transformation will
96 // add more than 1 instruction. Abandon!
97 return NULL;
98 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
99 get(isSub ? getOpcode(ARMII::SUBri) :
100 getOpcode(ARMII::ADDri)), WBReg)
101 .addReg(BaseReg).addImm(SOImmVal)
102 .addImm(Pred).addReg(0).addReg(0);
103 } else if (Amt != 0) {
104 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
105 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
106 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
107 get(isSub ? getOpcode(ARMII::SUBrs) :
108 getOpcode(ARMII::ADDrs)), WBReg)
109 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
110 .addImm(Pred).addReg(0).addReg(0);
111 } else
112 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
113 get(isSub ? getOpcode(ARMII::SUBrr) :
114 getOpcode(ARMII::ADDrr)), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
117 break;
118 }
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
122 if (OffReg == 0)
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? getOpcode(ARMII::SUBri) :
126 getOpcode(ARMII::ADDri)), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
129 else
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? getOpcode(ARMII::SUBrr) :
132 getOpcode(ARMII::ADDrr)), WBReg)
133 .addReg(BaseReg).addReg(OffReg)
134 .addImm(Pred).addReg(0).addReg(0);
135 break;
136 }
137 }
138
139 std::vector NewMIs;
140 if (isPre) {
141 if (isLoad)
142 MemMI = BuildMI(MF, MI->getDebugLoc(),
143 get(MemOpc), MI->getOperand(0).getReg())
144 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 else
146 MemMI = BuildMI(MF, MI->getDebugLoc(),
147 get(MemOpc)).addReg(MI->getOperand(1).getReg())
148 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
149 NewMIs.push_back(MemMI);
150 NewMIs.push_back(UpdateMI);
151 } else {
152 if (isLoad)
153 MemMI = BuildMI(MF, MI->getDebugLoc(),
154 get(MemOpc), MI->getOperand(0).getReg())
155 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 else
157 MemMI = BuildMI(MF, MI->getDebugLoc(),
158 get(MemOpc)).addReg(MI->getOperand(1).getReg())
159 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 if (WB.isDead())
161 UpdateMI->getOperand(0).setIsDead();
162 NewMIs.push_back(UpdateMI);
163 NewMIs.push_back(MemMI);
164 }
165
166 // Transfer LiveVariables states, kill / dead info.
167 if (LV) {
168 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
169 MachineOperand &MO = MI->getOperand(i);
170 if (MO.isReg() && MO.getReg() &&
171 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
172 unsigned Reg = MO.getReg();
173
174 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 if (MO.isDef()) {
176 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 if (MO.isDead())
178 LV->addVirtualRegisterDead(Reg, NewMI);
179 }
180 if (MO.isUse() && MO.isKill()) {
181 for (unsigned j = 0; j < 2; ++j) {
182 // Look at the two new MI's in reverse order.
183 MachineInstr *NewMI = NewMIs[j];
184 if (!NewMI->readsRegister(Reg))
185 continue;
186 LV->addVirtualRegisterKilled(Reg, NewMI);
187 if (VI.removeKill(MI))
188 VI.Kills.push_back(NewMI);
189 break;
190 }
191 }
192 }
193 }
194 }
195
196 MFI->insert(MBBI, NewMIs[1]);
197 MFI->insert(MBBI, NewMIs[0]);
198 return NewMIs[0];
199 }
200
201 // Branch analysis.
202 bool
203 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
204 MachineBasicBlock *&FBB,
205 SmallVectorImpl &Cond,
206 bool AllowModify) const {
207 // If the block has no terminators, it just falls into the block after it.
208 MachineBasicBlock::iterator I = MBB.end();
209 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
210 return false;
211
212 // Get the last instruction in the block.
213 MachineInstr *LastInst = I;
214
215 // If there is only one terminator instruction, process it.
216 unsigned LastOpc = LastInst->getOpcode();
217 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
218 if (LastOpc == getOpcode(ARMII::B)) {
219 TBB = LastInst->getOperand(0).getMBB();
220 return false;
221 }
222 if (LastOpc == getOpcode(ARMII::Bcc)) {
223 // Block ends with fall-through condbranch.
224 TBB = LastInst->getOperand(0).getMBB();
225 Cond.push_back(LastInst->getOperand(1));
226 Cond.push_back(LastInst->getOperand(2));
227 return false;
228 }
229 return true; // Can't handle indirect branch.
230 }
231
232 // Get the instruction before it if it is a terminator.
233 MachineInstr *SecondLastInst = I;
234
235 // If there are three terminators, we don't know what sort of block this is.
236 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
237 return true;
238
239 // If the block ends with ARMII::B and a ARMII::Bcc, handle it.
240 unsigned SecondLastOpc = SecondLastInst->getOpcode();
241 if ((SecondLastOpc == getOpcode(ARMII::Bcc)) &&
242 (LastOpc == getOpcode(ARMII::B))) {
243 TBB = SecondLastInst->getOperand(0).getMBB();
244 Cond.push_back(SecondLastInst->getOperand(1));
245 Cond.push_back(SecondLastInst->getOperand(2));
246 FBB = LastInst->getOperand(0).getMBB();
247 return false;
248 }
249
250 // If the block ends with two unconditional branches, handle it. The second
251 // one is not executed, so remove it.
252 if ((SecondLastOpc == getOpcode(ARMII::B)) &&
253 (LastOpc == getOpcode(ARMII::B))) {
254 TBB = SecondLastInst->getOperand(0).getMBB();
255 I = LastInst;
256 if (AllowModify)
257 I->eraseFromParent();
258 return false;
259 }
260
261 // ...likewise if it ends with a branch table followed by an unconditional
262 // branch. The branch folder can create these, and we must get rid of them for
263 // correctness of Thumb constant islands.
264 if (((SecondLastOpc == getOpcode(ARMII::BR_JTr)) ||
265 (SecondLastOpc == getOpcode(ARMII::BR_JTm)) ||
266 (SecondLastOpc == getOpcode(ARMII::BR_JTadd))) &&
267 (LastOpc == getOpcode(ARMII::B))) {
268 I = LastInst;
269 if (AllowModify)
270 I->eraseFromParent();
271 return true;
272 }
273
274 // Otherwise, can't handle this.
275 return true;
276 }
277
278
279 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
280 int BOpc = getOpcode(ARMII::B);
281 int BccOpc = getOpcode(ARMII::Bcc);
282
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin()) return 0;
285 --I;
286 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
287 return 0;
288
289 // Remove the branch.
290 I->eraseFromParent();
291
292 I = MBB.end();
293
294 if (I == MBB.begin()) return 1;
295 --I;
296 if (I->getOpcode() != BccOpc)
297 return 1;
298
299 // Remove the branch.
300 I->eraseFromParent();
301 return 2;
302 }
303
304 unsigned
305 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
306 MachineBasicBlock *FBB,
307 const SmallVectorImpl &Cond) const {
308 // FIXME this should probably have a DebugLoc argument
309 DebugLoc dl = DebugLoc::getUnknownLoc();
310 int BOpc = getOpcode(ARMII::B);
311 int BccOpc = getOpcode(ARMII::Bcc);
312
313 // Shouldn't be a fall through.
314 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
315 assert((Cond.size() == 2 || Cond.size() == 0) &&
316 "ARM branch conditions have two components!");
317
318 if (FBB == 0) {
319 if (Cond.empty()) // Unconditional branch?
320 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
321 else
322 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
323 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
324 return 1;
325 }
326
327 // Two-way conditional branch.
328 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
329 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
330 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
331 return 2;
332 }
333
334 bool ARMBaseInstrInfo::
335 ReverseBranchCondition(SmallVectorImpl &Cond) const {
336 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
337 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
338 return false;
339 }
340
341 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
342 int PIdx = MI->findFirstPredOperandIdx();
343 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
344 }
345
346 bool ARMBaseInstrInfo::
347 PredicateInstruction(MachineInstr *MI,
348 const SmallVectorImpl &Pred) const {
349 unsigned Opc = MI->getOpcode();
350 if (Opc == getOpcode(ARMII::B)) {
351 MI->setDesc(get(getOpcode(ARMII::Bcc)));
352 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
353 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
354 return true;
355 }
356
357 int PIdx = MI->findFirstPredOperandIdx();
358 if (PIdx != -1) {
359 MachineOperand &PMO = MI->getOperand(PIdx);
360 PMO.setImm(Pred[0].getImm());
361 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
362 return true;
363 }
364 return false;
365 }
366
367 bool ARMBaseInstrInfo::
368 SubsumesPredicate(const SmallVectorImpl &Pred1,
369 const SmallVectorImpl &Pred2) const {
370 if (Pred1.size() > 2 || Pred2.size() > 2)
371 return false;
372
373 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
374 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
375 if (CC1 == CC2)
376 return true;
377
378 switch (CC1) {
379 default:
380 return false;
381 case ARMCC::AL:
382 return true;
383 case ARMCC::HS:
384 return CC2 == ARMCC::HI;
385 case ARMCC::LS:
386 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
387 case ARMCC::GE:
388 return CC2 == ARMCC::GT;
389 case ARMCC::LE:
390 return CC2 == ARMCC::LT;
391 }
392 }
393
394 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
395 std::vector &Pred) const {
396 const TargetInstrDesc &TID = MI->getDesc();
397 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
398 return false;
399
400 bool Found = false;
401 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
402 const MachineOperand &MO = MI->getOperand(i);
403 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
404 Pred.push_back(MO);
405 Found = true;
406 }
407 }
408
409 return Found;
410 }
411
412
413 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
414 static unsigned getNumJTEntries(const std::vector &JT,
415 unsigned JTI) DISABLE_INLINE;
416 static unsigned getNumJTEntries(const std::vector &JT,
417 unsigned JTI) {
418 return JT[JTI].MBBs.size();
419 }
420
421 /// GetInstSize - Return the size of the specified MachineInstr.
422 ///
423 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
424 const MachineBasicBlock &MBB = *MI->getParent();
425 const MachineFunction *MF = MBB.getParent();
426 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
427
428 // Basic size info comes from the TSFlags field.
429 const TargetInstrDesc &TID = MI->getDesc();
430 unsigned TSFlags = TID.TSFlags;
431
432 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
433 default: {
434 // If this machine instr is an inline asm, measure it.
435 if (MI->getOpcode() == ARM::INLINEASM)
436 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
437 if (MI->isLabel())
438 return 0;
439 switch (MI->getOpcode()) {
440 default:
441 assert(0 && "Unknown or unset size field for instr!");
442 break;
443 case TargetInstrInfo::IMPLICIT_DEF:
444 case TargetInstrInfo::DECLARE:
445 case TargetInstrInfo::DBG_LABEL:
446 case TargetInstrInfo::EH_LABEL:
447 return 0;
448 }
449 break;
450 }
451 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
452 case ARMII::Size4Bytes: return 4; // Arm instruction.
453 case ARMII::Size2Bytes: return 2; // Thumb instruction.
454 case ARMII::SizeSpecial: {
455 switch (MI->getOpcode()) {
456 case ARM::CONSTPOOL_ENTRY:
457 // If this machine instr is a constant pool entry, its size is recorded as
458 // operand #2.
459 return MI->getOperand(2).getImm();
460 case ARM::Int_eh_sjlj_setjmp: return 12;
461 case ARM::BR_JTr:
462 case ARM::BR_JTm:
463 case ARM::BR_JTadd:
464 case ARM::t2BR_JTr:
465 case ARM::t2BR_JTm:
466 case ARM::t2BR_JTadd:
467 case ARM::tBR_JTr: {
468 // These are jumptable branches, i.e. a branch followed by an inlined
469 // jumptable. The size is 4 + 4 * number of entries.
470 unsigned NumOps = TID.getNumOperands();
471 MachineOperand JTOP =
472 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
473 unsigned JTI = JTOP.getIndex();
474 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
475 const std::vector &JT = MJTI->getJumpTables();
476 assert(JTI < JT.size());
477 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
478 // 4 aligned. The assembler / linker may add 2 byte padding just before
479 // the JT entries. The size does not include this padding; the
480 // constant islands pass does separate bookkeeping for it.
481 // FIXME: If we know the size of the function is less than (1 << 16) *2
482 // bytes, we can use 16-bit entries instead. Then there won't be an
483 // alignment issue.
484 return getNumJTEntries(JT, JTI) * 4 +
485 ((MI->getOpcode()==ARM::tBR_JTr) ? 2 : 4);
486 }
487 default:
488 // Otherwise, pseudo-instruction sizes are zero.
489 return 0;
490 }
491 }
492 }
493 return 0; // Not reached
494 }
495
496 /// Return true if the instruction is a register to register move and
497 /// leave the source and dest operands in the passed parameters.
498 ///
499 bool
500 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
501 unsigned &SrcReg, unsigned &DstReg,
502 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
503 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
504
505 unsigned oc = MI.getOpcode();
506 if ((oc == getOpcode(ARMII::FCPYS)) ||
507 (oc == getOpcode(ARMII::FCPYD)) ||
508 (oc == getOpcode(ARMII::VMOVD)) ||
509 (oc == getOpcode(ARMII::VMOVQ))) {
510 SrcReg = MI.getOperand(1).getReg();
511 DstReg = MI.getOperand(0).getReg();
512 return true;
513 }
514 else if (oc == getOpcode(ARMII::MOVr)) {
515 assert(MI.getDesc().getNumOperands() >= 2 &&
516 MI.getOperand(0).isReg() &&
517 MI.getOperand(1).isReg() &&
518 "Invalid ARM MOV instruction");
519 SrcReg = MI.getOperand(1).getReg();
520 DstReg = MI.getOperand(0).getReg();
521 return true;
522 }
523
524 return false;
525 }
526
527 unsigned
528 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
529 int &FrameIndex) const {
530 unsigned oc = MI->getOpcode();
531 if (oc == getOpcode(ARMII::LDR)) {
532 if (MI->getOperand(1).isFI() &&
533 MI->getOperand(2).isReg() &&
534 MI->getOperand(3).isImm() &&
535 MI->getOperand(2).getReg() == 0 &&
536 MI->getOperand(3).getImm() == 0) {
537 FrameIndex = MI->getOperand(1).getIndex();
538 return MI->getOperand(0).getReg();
539 }
540 }
541 else if ((oc == getOpcode(ARMII::FLDD)) ||
542 (oc == getOpcode(ARMII::FLDS))) {
543 if (MI->getOperand(1).isFI() &&
544 MI->getOperand(2).isImm() &&
545 MI->getOperand(2).getImm() == 0) {
546 FrameIndex = MI->getOperand(1).getIndex();
547 return MI->getOperand(0).getReg();
548 }
549 }
550
551 return 0;
552 }
553
554 unsigned
555 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
556 int &FrameIndex) const {
557 unsigned oc = MI->getOpcode();
558 if (oc == getOpcode(ARMII::STR)) {
559 if (MI->getOperand(1).isFI() &&
560 MI->getOperand(2).isReg() &&
561 MI->getOperand(3).isImm() &&
562 MI->getOperand(2).getReg() == 0 &&
563 MI->getOperand(3).getImm() == 0) {
564 FrameIndex = MI->getOperand(1).getIndex();
565 return MI->getOperand(0).getReg();
566 }
567 }
568 else if ((oc == getOpcode(ARMII::FSTD)) ||
569 (oc == getOpcode(ARMII::FSTS))) {
570 if (MI->getOperand(1).isFI() &&
571 MI->getOperand(2).isImm() &&
572 MI->getOperand(2).getImm() == 0) {
573 FrameIndex = MI->getOperand(1).getIndex();
574 return MI->getOperand(0).getReg();
575 }
576 }
577
578 return 0;
579 }
580
581 bool
582 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
583 MachineBasicBlock::iterator I,
584 unsigned DestReg, unsigned SrcReg,
585 const TargetRegisterClass *DestRC,
586 const TargetRegisterClass *SrcRC) const {
587 DebugLoc DL = DebugLoc::getUnknownLoc();
588 if (I != MBB.end()) DL = I->getDebugLoc();
589
590 if (DestRC != SrcRC) {
591 // Not yet supported!
592 return false;
593 }
594
595 if (DestRC == ARM::GPRRegisterClass)
596 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), DestReg)
597 .addReg(SrcReg)));
598 else if (DestRC == ARM::SPRRegisterClass)
599 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg)
600 .addReg(SrcReg));
601 else if (DestRC == ARM::DPRRegisterClass)
602 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYD)), DestReg)
603 .addReg(SrcReg));
604 else if (DestRC == ARM::QPRRegisterClass)
605 BuildMI(MBB, I, DL, get(getOpcode(ARMII::VMOVQ)), DestReg).addReg(SrcReg);
606 else
607 return false;
608
609 return true;
610 }
611
612 void ARMBaseInstrInfo::
613 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
614 unsigned SrcReg, bool isKill, int FI,
615 const TargetRegisterClass *RC) const {
616 DebugLoc DL = DebugLoc::getUnknownLoc();
617 if (I != MBB.end()) DL = I->getDebugLoc();
618
619 if (RC == ARM::GPRRegisterClass) {
620 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STR)))
621 .addReg(SrcReg, getKillRegState(isKill))
622 .addFrameIndex(FI).addReg(0).addImm(0));
623 } else if (RC == ARM::DPRRegisterClass) {
624 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FSTD)))
625 .addReg(SrcReg, getKillRegState(isKill))
626 .addFrameIndex(FI).addImm(0));
627 } else {
628 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
629 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FSTS)))
630 .addReg(SrcReg, getKillRegState(isKill))
631 .addFrameIndex(FI).addImm(0));
632 }
633 }
634
635 void
636 ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
637 bool isKill,
638 SmallVectorImpl &Addr,
639 const TargetRegisterClass *RC,
640 SmallVectorImpl &NewMIs) const{
641 DebugLoc DL = DebugLoc::getUnknownLoc();
642 unsigned Opc = 0;
643 if (RC == ARM::GPRRegisterClass) {
644 Opc = getOpcode(ARMII::STR);
645 } else if (RC == ARM::DPRRegisterClass) {
646 Opc = getOpcode(ARMII::FSTD);
647 } else {
648 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
649 Opc = getOpcode(ARMII::FSTS);
650 }
651
652 MachineInstrBuilder MIB =
653 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
654 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
655 MIB.addOperand(Addr[i]);
656 AddDefaultPred(MIB);
657 NewMIs.push_back(MIB);
658 return;
659 }
660
661 void ARMBaseInstrInfo::
662 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
663 unsigned DestReg, int FI,
664 const TargetRegisterClass *RC) const {
665 DebugLoc DL = DebugLoc::getUnknownLoc();
666 if (I != MBB.end()) DL = I->getDebugLoc();
667
668 if (RC == ARM::GPRRegisterClass) {
669 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDR)), DestReg)
670 .addFrameIndex(FI).addReg(0).addImm(0));
671 } else if (RC == ARM::DPRRegisterClass) {
672 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDD)), DestReg)
673 .addFrameIndex(FI).addImm(0));
674 } else {
675 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
676 AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDS)), DestReg)
677 .addFrameIndex(FI).addImm(0));
678 }
679 }
680
681 void ARMBaseInstrInfo::
682 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
683 SmallVectorImpl &Addr,
684 const TargetRegisterClass *RC,
685 SmallVectorImpl &NewMIs) const {
686 DebugLoc DL = DebugLoc::getUnknownLoc();
687 unsigned Opc = 0;
688 if (RC == ARM::GPRRegisterClass) {
689 Opc = getOpcode(ARMII::LDR);
690 } else if (RC == ARM::DPRRegisterClass) {
691 Opc = getOpcode(ARMII::FLDD);
692 } else {
693 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
694 Opc = getOpcode(ARMII::FLDS);
695 }
696
697 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
698 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
699 MIB.addOperand(Addr[i]);
700 AddDefaultPred(MIB);
701 NewMIs.push_back(MIB);
702 return;
703 }
704
705 MachineInstr *ARMBaseInstrInfo::
706 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
707 const SmallVectorImpl &Ops, int FI) const {
708 if (Ops.size() != 1) return NULL;
709
710 unsigned OpNum = Ops[0];
711 unsigned Opc = MI->getOpcode();
712 MachineInstr *NewMI = NULL;
713 if (Opc == getOpcode(ARMII::MOVr)) {
714 // If it is updating CPSR, then it cannot be folded.
715 if (MI->getOperand(4).getReg() != ARM::CPSR) {
716 unsigned Pred = MI->getOperand(2).getImm();
717 unsigned PredReg = MI->getOperand(3).getReg();
718 if (OpNum == 0) { // move -> store
719 unsigned SrcReg = MI->getOperand(1).getReg();
720 bool isKill = MI->getOperand(1).isKill();
721 bool isUndef = MI->getOperand(1).isUndef();
722 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STR)))
723 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
724 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
725 } else { // move -> load
726 unsigned DstReg = MI->getOperand(0).getReg();
727 bool isDead = MI->getOperand(0).isDead();
728 bool isUndef = MI->getOperand(0).isUndef();
729 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDR)))
730 .addReg(DstReg,
731 RegState::Define |
732 getDeadRegState(isDead) |
733 getUndefRegState(isUndef))
734 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
735 }
736 }
737 }
738 else if (Opc == getOpcode(ARMII::FCPYS)) {
739 unsigned Pred = MI->getOperand(2).getImm();
740 unsigned PredReg = MI->getOperand(3).getReg();
741 if (OpNum == 0) { // move -> store
742 unsigned SrcReg = MI->getOperand(1).getReg();
743 bool isKill = MI->getOperand(1).isKill();
744 bool isUndef = MI->getOperand(1).isUndef();
745 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FSTS)))
746 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
747 .addFrameIndex(FI)
748 .addImm(0).addImm(Pred).addReg(PredReg);
749 } else { // move -> load
750 unsigned DstReg = MI->getOperand(0).getReg();
751 bool isDead = MI->getOperand(0).isDead();
752 bool isUndef = MI->getOperand(0).isUndef();
753 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FLDS)))
754 .addReg(DstReg,
755 RegState::Define |
756 getDeadRegState(isDead) |
757 getUndefRegState(isUndef))
758 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
759 }
760 }
761 else if (Opc == getOpcode(ARMII::FCPYD)) {
762 unsigned Pred = MI->getOperand(2).getImm();
763 unsigned PredReg = MI->getOperand(3).getReg();
764 if (OpNum == 0) { // move -> store
765 unsigned SrcReg = MI->getOperand(1).getReg();
766 bool isKill = MI->getOperand(1).isKill();
767 bool isUndef = MI->getOperand(1).isUndef();
768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FSTD)))
769 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
770 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
771 } else { // move -> load
772 unsigned DstReg = MI->getOperand(0).getReg();
773 bool isDead = MI->getOperand(0).isDead();
774 bool isUndef = MI->getOperand(0).isUndef();
775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::FLDD)))
776 .addReg(DstReg,
777 RegState::Define |
778 getDeadRegState(isDead) |
779 getUndefRegState(isUndef))
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
781 }
782 }
783
784 return NewMI;
785 }
786
787 MachineInstr*
788 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
789 MachineInstr* MI,
790 const SmallVectorImpl &Ops,
791 MachineInstr* LoadMI) const {
792 return 0;
793 }
794
795 bool
796 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
797 const SmallVectorImpl &Ops) const {
798 if (Ops.size() != 1) return false;
799
800 unsigned Opc = MI->getOpcode();
801 if (Opc == getOpcode(ARMII::MOVr)) {
802 // If it is updating CPSR, then it cannot be folded.
803 return MI->getOperand(4).getReg() != ARM::CPSR;
804 }
805 else if ((Opc == getOpcode(ARMII::FCPYS)) ||
806 (Opc == getOpcode(ARMII::FCPYD))) {
807 return true;
808 }
809 else if ((Opc == getOpcode(ARMII::VMOVD)) ||
810 (Opc == getOpcode(ARMII::VMOVQ))) {
811 return false; // FIXME
812 }
813
814 return false;
815 }
0 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ARMBASEINSTRUCTIONINFO_H
14 #define ARMBASEINSTRUCTIONINFO_H
15
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "ARMRegisterInfo.h"
18 #include "ARM.h"
19
20 namespace llvm {
21 class ARMSubtarget;
22
23 /// ARMII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
25 ///
26 namespace ARMII {
27 enum {
28 //===------------------------------------------------------------------===//
29 // Instruction Flags.
30
31 //===------------------------------------------------------------------===//
32 // This four-bit field describes the addressing mode used.
33
34 AddrModeMask = 0xf,
35 AddrModeNone = 0,
36 AddrMode1 = 1,
37 AddrMode2 = 2,
38 AddrMode3 = 3,
39 AddrMode4 = 4,
40 AddrMode5 = 5,
41 AddrMode6 = 6,
42 AddrModeT1_1 = 7,
43 AddrModeT1_2 = 8,
44 AddrModeT1_4 = 9,
45 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
46 AddrModeT2_i12 = 11,
47 AddrModeT2_i8 = 12,
48 AddrModeT2_so = 13,
49 AddrModeT2_pc = 14, // +/- i12 for pc relative data
50 AddrModeT2_i8s4 = 15, // i8 * 4
51
52 // Size* - Flags to keep track of the size of an instruction.
53 SizeShift = 4,
54 SizeMask = 7 << SizeShift,
55 SizeSpecial = 1, // 0 byte pseudo or special case.
56 Size8Bytes = 2,
57 Size4Bytes = 3,
58 Size2Bytes = 4,
59
60 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
61 // and store ops
62 IndexModeShift = 7,
63 IndexModeMask = 3 << IndexModeShift,
64 IndexModePre = 1,
65 IndexModePost = 2,
66
67 //===------------------------------------------------------------------===//
68 // Instruction encoding formats.
69 //
70 FormShift = 9,
71 FormMask = 0x3f << FormShift,
72
73 // Pseudo instructions
74 Pseudo = 0 << FormShift,
75
76 // Multiply instructions
77 MulFrm = 1 << FormShift,
78
79 // Branch instructions
80 BrFrm = 2 << FormShift,
81 BrMiscFrm = 3 << FormShift,
82
83 // Data Processing instructions
84 DPFrm = 4 << FormShift,
85 DPSoRegFrm = 5 << FormShift,
86
87 // Load and Store
88 LdFrm = 6 << FormShift,
89 StFrm = 7 << FormShift,
90 LdMiscFrm = 8 << FormShift,
91 StMiscFrm = 9 << FormShift,
92 LdStMulFrm = 10 << FormShift,
93
94 // Miscellaneous arithmetic instructions
95 ArithMiscFrm = 11 << FormShift,
96
97 // Extend instructions
98 ExtFrm = 12 << FormShift,
99
100 // VFP formats
101 VFPUnaryFrm = 13 << FormShift,
102 VFPBinaryFrm = 14 << FormShift,
103 VFPConv1Frm = 15 << FormShift,
104 VFPConv2Frm = 16 << FormShift,
105 VFPConv3Frm = 17 << FormShift,
106 VFPConv4Frm = 18 << FormShift,
107 VFPConv5Frm = 19 << FormShift,
108 VFPLdStFrm = 20 << FormShift,
109 VFPLdStMulFrm = 21 << FormShift,
110 VFPMiscFrm = 22 << FormShift,
111
112 // Thumb format
113 ThumbFrm = 23 << FormShift,
114
115 // NEON format
116 NEONFrm = 24 << FormShift,
117 NEONGetLnFrm = 25 << FormShift,
118 NEONSetLnFrm = 26 << FormShift,
119 NEONDupFrm = 27 << FormShift,
120
121 //===------------------------------------------------------------------===//
122 // Misc flags.
123
124 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
125 // it doesn't have a Rn operand.
126 UnaryDP = 1 << 15,
127
128 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
129 // a 16-bit Thumb instruction if certain conditions are met.
130 Xform16Bit = 1 << 16,
131
132 //===------------------------------------------------------------------===//
133 // Field shifts - such shifts are used to set field while generating
134 // machine instructions.
135 M_BitShift = 5,
136 ShiftImmShift = 5,
137 ShiftShift = 7,
138 N_BitShift = 7,
139 ImmHiShift = 8,
140 SoRotImmShift = 8,
141 RegRsShift = 8,
142 ExtRotImmShift = 10,
143 RegRdLoShift = 12,
144 RegRdShift = 12,
145 RegRdHiShift = 16,
146 RegRnShift = 16,
147 S_BitShift = 20,
148 W_BitShift = 21,
149 AM3_I_BitShift = 22,
150 D_BitShift = 22,
151 U_BitShift = 23,
152 P_BitShift = 24,
153 I_BitShift = 25,
154 CondShift = 28
155 };
156
157 /// ARMII::Op - Holds all of the instruction types required by
158 /// target specific instruction and register code. ARMBaseInstrInfo
159 /// and subclasses should return a specific opcode that implements
160 /// the instruction type.
161 ///
162 enum Op {
163 ADDri,
164 ADDrs,
165 ADDrr,
166 B,
167 Bcc,
168 BR_JTr,
169 BR_JTm,
170 BR_JTadd,
171 FCPYS,
172 FCPYD,
173 FLDD,
174 FLDS,
175 FSTD,
176 FSTS,
177 LDR,
178 MOVr,
179 STR,
180 SUBri,
181 SUBrs,
182 SUBrr,
183 VMOVD,
184 VMOVQ
185 };
186 }
187
188 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
189 protected:
190 // Can be only subclassed.
191 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
192 public:
193 // Return the non-pre/post incrementing version of 'Opc'. Return 0
194 // if there is not such an opcode.
195 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
196
197 // Return the opcode that implements 'Op', or 0 if no opcode
198 virtual unsigned getOpcode(ARMII::Op Op) const =0;
199
200 // Return true if the block does not fall through.
201 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
202
203 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
204 MachineBasicBlock::iterator &MBBI,
205 LiveVariables *LV) const;
206
207 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
208
209 // Branch analysis.
210 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
211 MachineBasicBlock *&FBB,
212 SmallVectorImpl &Cond,
213 bool AllowModify) const;
214 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
215 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
216 MachineBasicBlock *FBB,
217 const SmallVectorImpl &Cond) const;
218
219 virtual
220 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
221
222 // Predication support.
223 virtual bool isPredicated(const MachineInstr *MI) const;
224
225 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
226 int PIdx = MI->findFirstPredOperandIdx();
227 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
228 : ARMCC::AL;
229 }
230
231 virtual
232 bool PredicateInstruction(MachineInstr *MI,
233 const SmallVectorImpl &Pred) const;
234
235 virtual
236 bool SubsumesPredicate(const SmallVectorImpl &Pred1,
237 const SmallVectorImpl &Pred2) const;
238
239 virtual bool DefinesPredicate(MachineInstr *MI,
240 std::vector &Pred) const;
241
242 /// GetInstSize - Returns the size of the specified MachineInstr.
243 ///
244 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
245
246 /// Return true if the instruction is a register to register move and return
247 /// the source and dest operands and their sub-register indices by reference.
248 virtual bool isMoveInstr(const MachineInstr &MI,
249 unsigned &SrcReg, unsigned &DstReg,
250 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
251
252 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
253 int &FrameIndex) const;
254 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
255 int &FrameIndex) const;
256
257 virtual bool copyRegToReg(MachineBasicBlock &MBB,
258 MachineBasicBlock::iterator I,
259 unsigned DestReg, unsigned SrcReg,
260 const TargetRegisterClass *DestRC,
261 const TargetRegisterClass *SrcRC) const;
262 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator MBBI,
264 unsigned SrcReg, bool isKill, int FrameIndex,
265 const TargetRegisterClass *RC) const;
266
267 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
268 SmallVectorImpl &Addr,
269 const TargetRegisterClass *RC,
270 SmallVectorImpl &NewMIs) const;
271
272 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator MBBI,
274 unsigned DestReg, int FrameIndex,
275 const TargetRegisterClass *RC) const;
276
277 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
278 SmallVectorImpl &Addr,
279 const TargetRegisterClass *RC,
280 SmallVectorImpl &NewMIs) const;
281
282 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
283 const SmallVectorImpl &Ops) const;
284
285 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
286 MachineInstr* MI,
287 const SmallVectorImpl &Ops,
288 int FrameIndex) const;
289
290 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
291 MachineInstr* MI,
292 const SmallVectorImpl &Ops,
293 MachineInstr* LoadMI) const;
294 };
295 }
296
297 #endif
2424 #include "llvm/Support/CommandLine.h"
2525 using namespace llvm;
2626
27 static cl::opt
28 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
30
31 static inline
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
34 }
35
36 static inline
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
38 return MIB.addReg(0);
39 }
40
41 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
43 }
44
4527 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
4628 : ARMBaseInstrInfo(STI), RI(*this, STI) {
4729 }
4830
49 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator I,
51 unsigned DestReg,
52 const MachineInstr *Orig) const {
53 DebugLoc dl = Orig->getDebugLoc();
54 if (Orig->getOpcode() == ARM::MOVi2pieces) {
55 RI.emitLoadConstPool(MBB, I, this, dl,
56 DestReg,
57 Orig->getOperand(1).getImm(),
58 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
59 Orig->getOperand(3).getReg());
60 return;
61 }
62
63 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
64 MI->getOperand(0).setReg(DestReg);
65 MBB.insert(I, MI);
66 }
67
68 static unsigned getUnindexedOpcode(unsigned Opc) {
31 unsigned ARMInstrInfo::
32 getUnindexedOpcode(unsigned Opc) const {
6933 switch (Opc) {
7034 default: break;
7135 case ARM::LDR_PRE:
9357 case ARM::STRB_POST:
9458 return ARM::STRB;
9559 }
60
9661 return 0;
9762 }
9863
99 MachineInstr *
100 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
101 MachineBasicBlock::iterator &MBBI,
102 LiveVariables *LV) const {
103 if (!EnableARM3Addr)
104 return NULL;
105
106 MachineInstr *MI = MBBI;
107 MachineFunction &MF = *MI->getParent()->getParent();
108 unsigned TSFlags = MI->getDesc().TSFlags;
109 bool isPre = false;
110 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
111 default: return NULL;
112 case ARMII::IndexModePre:
113 isPre = true;
114 break;
115 case ARMII::IndexModePost:
116 break;
117 }
118
119 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
120 // operation.
121 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
122 if (MemOpc == 0)
123 return NULL;
124
125 MachineInstr *UpdateMI = NULL;
126 MachineInstr *MemMI = NULL;
127 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
128 const TargetInstrDesc &TID = MI->getDesc();
129 unsigned NumOps = TID.getNumOperands();
130 bool isLoad = !TID.mayStore();
131 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
132 const MachineOperand &Base = MI->getOperand(2);
133 const MachineOperand &Offset = MI->getOperand(NumOps-3);
134 unsigned WBReg = WB.getReg();
135 unsigned BaseReg = Base.getReg();
136 unsigned OffReg = Offset.getReg();
137 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
138 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
139 switch (AddrMode) {
64 unsigned ARMInstrInfo::
65 getOpcode(ARMII::Op Op) const {
66 switch (Op) {
67 case ARMII::ADDri: return ARM::ADDri;
68 case ARMII::ADDrs: return ARM::ADDrs;
69 case ARMII::ADDrr: return ARM::ADDrr;
70 case ARMII::B: return ARM::B;
71 case ARMII::Bcc: return ARM::Bcc;
72 case ARMII::BR_JTr: return ARM::BR_JTr;
73 case ARMII::BR_JTm: return ARM::BR_JTm;
74 case ARMII::BR_JTadd: return ARM::BR_JTadd;
75 case ARMII::FCPYS: return ARM::FCPYS;
76 case ARMII::FCPYD: return ARM::FCPYD;
77 case ARMII::FLDD: return ARM::FLDD;
78 case ARMII::FLDS: return ARM::FLDS;
79 case ARMII::FSTD: return ARM::FSTD;
80 case ARMII::FSTS: return ARM::FSTS;
81 case ARMII::LDR: return ARM::LDR;
82 case ARMII::MOVr: return ARM::MOVr;
83 case ARMII::STR: return ARM::STR;
84 case ARMII::SUBri: return ARM::SUBri;
85 case ARMII::SUBrs: return ARM::SUBrs;
86 case ARMII::SUBrr: return ARM::SUBrr;
87 case ARMII::VMOVD: return ARM::VMOVD;
88 case ARMII::VMOVQ: return ARM::VMOVQ;
14089 default:
141 assert(false && "Unknown indexed op!");
142 return NULL;
143 case ARMII::AddrMode2: {
144 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
145 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
146 if (OffReg == 0) {
147 int SOImmVal = ARM_AM::getSOImmVal(Amt);
148 if (SOImmVal == -1)
149 // Can't encode it in a so_imm operand. This transformation will
150 // add more than 1 instruction. Abandon!
151 return NULL;
152 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
153 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
154 .addReg(BaseReg).addImm(SOImmVal)
155 .addImm(Pred).addReg(0).addReg(0);
156 } else if (Amt != 0) {
157 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
158 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
159 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
160 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
161 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
162 .addImm(Pred).addReg(0).addReg(0);
163 } else
164 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
165 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
166 .addReg(BaseReg).addReg(OffReg)
167 .addImm(Pred).addReg(0).addReg(0);
168 break;
169 }
170 case ARMII::AddrMode3 : {
171 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
172 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
173 if (OffReg == 0)
174 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
177 .addReg(BaseReg).addImm(Amt)
178 .addImm(Pred).addReg(0).addReg(0);
179 else
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
184 break;
185 }
186 }
187
188 std::vector NewMIs;
189 if (isPre) {
190 if (isLoad)
191 MemMI = BuildMI(MF, MI->getDebugLoc(),
192 get(MemOpc), MI->getOperand(0).getReg())
193 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
194 else
195 MemMI = BuildMI(MF, MI->getDebugLoc(),
196 get(MemOpc)).addReg(MI->getOperand(1).getReg())
197 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
198 NewMIs.push_back(MemMI);
199 NewMIs.push_back(UpdateMI);
200 } else {
201 if (isLoad)
202 MemMI = BuildMI(MF, MI->getDebugLoc(),
203 get(MemOpc), MI->getOperand(0).getReg())
204 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
205 else
206 MemMI = BuildMI(MF, MI->getDebugLoc(),
207 get(MemOpc)).addReg(MI->getOperand(1).getReg())
208 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
209 if (WB.isDead())
210 UpdateMI->getOperand(0).setIsDead();
211 NewMIs.push_back(UpdateMI);
212 NewMIs.push_back(MemMI);
213 }
214
215 // Transfer LiveVariables states, kill / dead info.
216 if (LV) {
217 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
218 MachineOperand &MO = MI->getOperand(i);
219 if (MO.isReg() && MO.getReg() &&
220 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
221 unsigned Reg = MO.getReg();
222
223 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
224 if (MO.isDef()) {
225 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
226 if (MO.isDead())
227 LV->addVirtualRegisterDead(Reg, NewMI);
228 }
229 if (MO.isUse() && MO.isKill()) {
230 for (unsigned j = 0; j < 2; ++j) {
231 // Look at the two new MI's in reverse order.
232 MachineInstr *NewMI = NewMIs[j];
233 if (!NewMI->readsRegister(Reg))
234 continue;
235 LV->addVirtualRegisterKilled(Reg, NewMI);
236 if (VI.removeKill(MI))
237 VI.Kills.push_back(NewMI);
238 break;
239 }
240 }
241 }
242 }
243 }
244
245 MFI->insert(MBBI, NewMIs[1]);
246 MFI->insert(MBBI, NewMIs[0]);
247 return NewMIs[0];
248 }
249
250 // Branch analysis.
251 bool
252 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
253 MachineBasicBlock *&FBB,
254 SmallVectorImpl &Cond,
255 bool AllowModify) const {
256 // If the block has no terminators, it just falls into the block after it.
257 MachineBasicBlock::iterator I = MBB.end();
258 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
259 return false;
260
261 // Get the last instruction in the block.
262 MachineInstr *LastInst = I;
263
264 // If there is only one terminator instruction, process it.
265 unsigned LastOpc = LastInst->getOpcode();
266 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
267 if (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B) {
268 TBB = LastInst->getOperand(0).getMBB();
269 return false;
270 }
271 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc || LastOpc == ARM::t2Bcc) {
272 // Block ends with fall-through condbranch.
273 TBB = LastInst->getOperand(0).getMBB();
274 Cond.push_back(LastInst->getOperand(1));
275 Cond.push_back(LastInst->getOperand(2));
276 return false;
277 }
278 return true; // Can't handle indirect branch.
279 }
280
281 // Get the instruction before it if it is a terminator.
282 MachineInstr *SecondLastInst = I;
283
284 // If there are three terminators, we don't know what sort of block this is.
285 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
286 return true;
287
288 // If the block ends with ARM::B/ARM::tB/ARM::t2B and a
289 // ARM::Bcc/ARM::tBcc/ARM::t2Bcc, handle it.
290 unsigned SecondLastOpc = SecondLastInst->getOpcode();
291 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
292 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB) ||
293 (SecondLastOpc == ARM::t2Bcc && LastOpc == ARM::t2B)) {
294 TBB = SecondLastInst->getOperand(0).getMBB();
295 Cond.push_back(SecondLastInst->getOperand(1));
296 Cond.push_back(SecondLastInst->getOperand(2));
297 FBB = LastInst->getOperand(0).getMBB();
298 return false;
299 }
300
301 // If the block ends with two unconditional branches, handle it. The second
302 // one is not executed, so remove it.
303 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB ||
304 SecondLastOpc==ARM::t2B) &&
305 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
306 TBB = SecondLastInst->getOperand(0).getMBB();
307 I = LastInst;
308 if (AllowModify)
309 I->eraseFromParent();
310 return false;
311 }
312
313 // ...likewise if it ends with a branch table followed by an unconditional
314 // branch. The branch folder can create these, and we must get rid of them for
315 // correctness of Thumb constant islands.
316 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
317 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr ||
318 SecondLastOpc == ARM::t2BR_JTr || SecondLastOpc==ARM::t2BR_JTm ||
319 SecondLastOpc == ARM::t2BR_JTadd) &&
320 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
321 I = LastInst;
322 if (AllowModify)
323 I->eraseFromParent();
324 return true;
325 }
326
327 // Otherwise, can't handle this.
328 return true;
329 }
330
331
332 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
333 MachineFunction &MF = *MBB.getParent();
334 ARMFunctionInfo *AFI = MF.getInfo();
335 int BOpc = AFI->isThumbFunction() ?
336 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
337 int BccOpc = AFI->isThumbFunction() ?
338 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
339
340 MachineBasicBlock::iterator I = MBB.end();
341 if (I == MBB.begin()) return 0;
342 --I;
343 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
344 return 0;
345
346 // Remove the branch.
347 I->eraseFromParent();
348
349 I = MBB.end();
350
351 if (I == MBB.begin()) return 1;
352 --I;
353 if (I->getOpcode() != BccOpc)
354 return 1;
355
356 // Remove the branch.
357 I->eraseFromParent();
358 return 2;
359 }
360
361 unsigned
362 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
363 MachineBasicBlock *FBB,
364 const SmallVectorImpl &Cond) const {
365 // FIXME this should probably have a DebugLoc argument
366 DebugLoc dl = DebugLoc::getUnknownLoc();
367 MachineFunction &MF = *MBB.getParent();
368 ARMFunctionInfo *AFI = MF.getInfo();
369 int BOpc = AFI->isThumbFunction() ?
370 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
371 int BccOpc = AFI->isThumbFunction() ?
372 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
373
374 // Shouldn't be a fall through.
375 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
376 assert((Cond.size() == 2 || Cond.size() == 0) &&
377 "ARM branch conditions have two components!");
378
379 if (FBB == 0) {
380 if (Cond.empty()) // Unconditional branch?
381 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
382 else
383 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
384 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
385 return 1;
386 }
387
388 // Two-way conditional branch.
389 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
390 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
391 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
392 return 2;
393 }
394
395 bool
396 ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
397 if (MBB.empty()) return false;
398
399 switch (MBB.back().getOpcode()) {
400 case ARM::BX_RET: // Return.
401 case ARM::LDM_RET:
402 case ARM::tBX_RET:
403 case ARM::tBX_RET_vararg:
404 case ARM::tPOP_RET:
405 case ARM::B:
406 case ARM::tB:
407 case ARM::t2B: // Uncond branch.
408 case ARM::tBR_JTr:
409 case ARM::t2BR_JTr:
410 case ARM::BR_JTr: // Jumptable branch.
411 case ARM::t2BR_JTm:
412 case ARM::BR_JTm: // Jumptable branch through mem.
413 case ARM::t2BR_JTadd:
414 case ARM::BR_JTadd: // Jumptable branch add to pc.
415 return true;
416 default: return false;
417 }
418 }
419
420 bool ARMBaseInstrInfo::
421 ReverseBranchCondition(SmallVectorImpl &Cond) const {
422 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
423 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
424 return false;
425 }
426
427 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
428 int PIdx = MI->findFirstPredOperandIdx();
429 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
430 }
431
432 bool ARMBaseInstrInfo::
433 PredicateInstruction(MachineInstr *MI,
434 const SmallVectorImpl &Pred) const {
435 unsigned Opc = MI->getOpcode();
436 if (Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B) {
437 MI->setDesc(get((Opc == ARM::B) ? ARM::Bcc :
438 ((Opc == ARM::tB) ? ARM::tBcc : ARM::t2Bcc)));
439 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
440 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
441 return true;
442 }
443
444 int PIdx = MI->findFirstPredOperandIdx();
445 if (PIdx != -1) {
446 MachineOperand &PMO = MI->getOperand(PIdx);
447 PMO.setImm(Pred[0].getImm());
448 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
449 return true;
450 }
451 return false;
452 }
453
454 bool ARMBaseInstrInfo::
455 SubsumesPredicate(const SmallVectorImpl &Pred1,
456 const SmallVectorImpl &Pred2) const {
457 if (Pred1.size() > 2 || Pred2.size() > 2)
458 return false;
459
460 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
461 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
462 if (CC1 == CC2)
463 return true;
464
465 switch (CC1) {
466 default:
467 return false;
468 case ARMCC::AL:
469 return true;
470 case ARMCC::HS:
471 return CC2 == ARMCC::HI;
472 case ARMCC::LS:
473 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
474 case ARMCC::GE:
475 return CC2 == ARMCC::GT;
476 case ARMCC::LE:
477 return CC2 == ARMCC::LT;
478 }
479 }
480
481 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
482 std::vector &Pred) const {
483 const TargetInstrDesc &TID = MI->getDesc();
484 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
485 return false;
486
487 bool Found = false;
488 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
489 const MachineOperand &MO = MI->getOperand(i);
490 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
491 Pred.push_back(MO);
492 Found = true;
493 }
494 }
495
496 return Found;
497 }
498
499
500 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
501 static unsigned getNumJTEntries(const std::vector &JT,
502 unsigned JTI) DISABLE_INLINE;
503 static unsigned getNumJTEntries(const std::vector &JT,
504 unsigned JTI) {
505 return JT[JTI].MBBs.size();
506 }
507
508 /// GetInstSize - Return the size of the specified MachineInstr.
509 ///
510 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
511 const MachineBasicBlock &MBB = *MI->getParent();
512 const MachineFunction *MF = MBB.getParent();
513 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
514
515 // Basic size info comes from the TSFlags field.
516 const TargetInstrDesc &TID = MI->getDesc();
517 unsigned TSFlags = TID.TSFlags;
518
519 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
520 default: {
521 // If this machine instr is an inline asm, measure it.
522 if (MI->getOpcode() == ARM::INLINEASM)
523 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
524 if (MI->isLabel())
525 return 0;
526 switch (MI->getOpcode()) {
527 default:
528 assert(0 && "Unknown or unset size field for instr!");
529 break;
530 case TargetInstrInfo::IMPLICIT_DEF:
531 case TargetInstrInfo::DECLARE:
532 case TargetInstrInfo::DBG_LABEL:
533 case TargetInstrInfo::EH_LABEL:
534 return 0;
535 }
536 break;
537 }
538 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
539 case ARMII::Size4Bytes: return 4; // Arm instruction.
540 case ARMII::Size2Bytes: return 2; // Thumb instruction.
541 case ARMII::SizeSpecial: {
542 switch (MI->getOpcode()) {
543 case ARM::CONSTPOOL_ENTRY:
544 // If this machine instr is a constant pool entry, its size is recorded as
545 // operand #2.
546 return MI->getOperand(2).getImm();
547 case ARM::Int_eh_sjlj_setjmp: return 12;
548 case ARM::BR_JTr:
549 case ARM::BR_JTm:
550 case ARM::BR_JTadd:
551 case ARM::t2BR_JTr:
552 case ARM::t2BR_JTm:
553 case ARM::t2BR_JTadd:
554 case ARM::tBR_JTr: {
555 // These are jumptable branches, i.e. a branch followed by an inlined
556 // jumptable. The size is 4 + 4 * number of entries.
557 unsigned NumOps = TID.getNumOperands();
558 MachineOperand JTOP =
559 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
560 unsigned JTI = JTOP.getIndex();
561 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
562 const std::vector &JT = MJTI->getJumpTables();
563 assert(JTI < JT.size());
564 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
565 // 4 aligned. The assembler / linker may add 2 byte padding just before
566 // the JT entries. The size does not include this padding; the
567 // constant islands pass does separate bookkeeping for it.
568 // FIXME: If we know the size of the function is less than (1 << 16) *2
569 // bytes, we can use 16-bit entries instead. Then there won't be an
570 // alignment issue.
571 return getNumJTEntries(JT, JTI) * 4 +
572 ((MI->getOpcode()==ARM::tBR_JTr) ? 2 : 4);
573 }
574 default:
575 // Otherwise, pseudo-instruction sizes are zero.
576 return 0;
577 }
578 }
579 }
580 return 0; // Not reached
581 }
582
583 /// Return true if the instruction is a register to register move and
584 /// leave the source and dest operands in the passed parameters.
585 ///
586 bool
587 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
588 unsigned &SrcReg, unsigned &DstReg,
589 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
590 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
591
592 unsigned oc = MI.getOpcode();
593 switch (oc) {
594 default:
595 return false;
596 case ARM::FCPYS:
597 case ARM::FCPYD:
598 case ARM::VMOVD:
599 case ARM::VMOVQ:
600 SrcReg = MI.getOperand(1).getReg();
601 DstReg = MI.getOperand(0).getReg();
602 return true;
603 case ARM::MOVr:
604 assert(MI.getDesc().getNumOperands() >= 2 &&
605 MI.getOperand(0).isReg() &&
606 MI.getOperand(1).isReg() &&
607 "Invalid ARM MOV instruction");
608 SrcReg = MI.getOperand(1).getReg();
609 DstReg = MI.getOperand(0).getReg();
610 return true;
611 }
612 }
613
614 unsigned
615 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
616 int &FrameIndex) const {
617 switch (MI->getOpcode()) {
618 default: break;
619 case ARM::LDR:
620 if (MI->getOperand(1).isFI() &&
621 MI->getOperand(2).isReg() &&
622 MI->getOperand(3).isImm() &&
623 MI->getOperand(2).getReg() == 0 &&
624 MI->getOperand(3).getImm() == 0) {
625 FrameIndex = MI->getOperand(1).getIndex();
626 return MI->getOperand(0).getReg();
627 }
628 break;
629 case ARM::FLDD:
630 case ARM::FLDS:
631 if (MI->getOperand(1).isFI() &&
632 MI->getOperand(2).isImm() &&
633 MI->getOperand(2).getImm() == 0) {
634 FrameIndex = MI->getOperand(1).getIndex();
635 return MI->getOperand(0).getReg();
636 }
637 break;
638 }
639 return 0;
640 }
641
642 unsigned
643 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
644 int &FrameIndex) const {
645 switch (MI->getOpcode()) {
646 default: break;
647 case ARM::STR:
648 if (MI->getOperand(1).isFI() &&
649 MI->getOperand(2).isReg() &&
650 MI->getOperand(3).isImm() &&
651 MI->getOperand(2).getReg() == 0 &&
652 MI->getOperand(3).getImm() == 0) {
653 FrameIndex = MI->getOperand(1).getIndex();
654 return MI->getOperand(0).getReg();
655 }
656 break;
657 case ARM::FSTD:
658 case ARM::FSTS:
659 if (MI->getOperand(1).isFI() &&
660 MI->getOperand(2).isImm() &&
661 MI->getOperand(2).getImm() == 0) {
662 FrameIndex = MI->getOperand(1).getIndex();
663 return MI->getOperand(0).getReg();
664 }
66590 break;
66691 }
66792
66893 return 0;
66994 }
67095
671 bool
672 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
673 MachineBasicBlock::iterator I,
674 unsigned DestReg, unsigned SrcReg,
675 const TargetRegisterClass *DestRC,
676 const TargetRegisterClass *SrcRC) const {
677 DebugLoc DL = DebugLoc::getUnknownLoc();
678 if (I != MBB.end()) DL = I->getDebugLoc();
96 bool ARMInstrInfo::
97 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
98 if (MBB.empty()) return false;
67999
680 if (DestRC != SrcRC) {
681 // Not yet supported!
682 return false;
683 }
684
685 if (DestRC == ARM::GPRRegisterClass)
686 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
687 .addReg(SrcReg)));
688 else if (DestRC == ARM::SPRRegisterClass)
689 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
690 .addReg(SrcReg));
691 else if (DestRC == ARM::DPRRegisterClass)
692 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
693 .addReg(SrcReg));
694 else if (DestRC == ARM::QPRRegisterClass)
695 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
696 else
697 return false;
698
699 return true;
700 }
701
702 void ARMBaseInstrInfo::
703 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
704 unsigned SrcReg, bool isKill, int FI,
705 const TargetRegisterClass *RC) const {
706 DebugLoc DL = DebugLoc::getUnknownLoc();
707 if (I != MBB.end()) DL = I->getDebugLoc();
708
709 if (RC == ARM::GPRRegisterClass) {
710 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
711 .addReg(SrcReg, getKillRegState(isKill))
712 .addFrameIndex(FI).addReg(0).addImm(0));
713 } else if (RC == ARM::DPRRegisterClass) {
714 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
715 .addReg(SrcReg, getKillRegState(isKill))
716 .addFrameIndex(FI).addImm(0));
717 } else {
718 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
720 .addReg(SrcReg, getKillRegState(isKill))
721 .addFrameIndex(FI).addImm(0));
722 }
723 }
724
725 void
726 ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
727 bool isKill,
728 SmallVectorImpl &Addr,
729 const TargetRegisterClass *RC,
730 SmallVectorImpl &NewMIs) const{
731 DebugLoc DL = DebugLoc::getUnknownLoc();
732 unsigned Opc = 0;
733 if (RC == ARM::GPRRegisterClass) {
734 Opc = ARM::STR;
735 } else if (RC == ARM::DPRRegisterClass) {
736 Opc = ARM::FSTD;
737 } else {
738 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
739 Opc = ARM::FSTS;
740 }
741
742 MachineInstrBuilder MIB =
743 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
744 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
745 MIB.addOperand(Addr[i]);
746 AddDefaultPred(MIB);
747 NewMIs.push_back(MIB);
748 return;
749 }
750
751 void ARMBaseInstrInfo::
752 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
753 unsigned DestReg, int FI,
754 const TargetRegisterClass *RC) const {
755 DebugLoc DL = DebugLoc::getUnknownLoc();
756 if (I != MBB.end()) DL = I->getDebugLoc();
757
758 if (RC == ARM::GPRRegisterClass) {
759 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
760 .addFrameIndex(FI).addReg(0).addImm(0));
761 } else if (RC == ARM::DPRRegisterClass) {
762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
763 .addFrameIndex(FI).addImm(0));
764 } else {
765 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
766 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
767 .addFrameIndex(FI).addImm(0));
768 }
769 }
770
771 void ARMBaseInstrInfo::
772 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
773 SmallVectorImpl &Addr,
774 const TargetRegisterClass *RC,
775 SmallVectorImpl &NewMIs) const {
776 DebugLoc DL = DebugLoc::getUnknownLoc();
777 unsigned Opc = 0;
778 if (RC == ARM::GPRRegisterClass) {
779 Opc = ARM::LDR;
780 } else if (RC == ARM::DPRRegisterClass) {
781 Opc = ARM::FLDD;
782 } else {
783 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
784 Opc = ARM::FLDS;
785 }
786
787 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
788 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
789 MIB.addOperand(Addr[i]);
790 AddDefaultPred(MIB);
791 NewMIs.push_back(MIB);
792 return;
793 }
794
795 MachineInstr *ARMBaseInstrInfo::
796 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
797 const SmallVectorImpl &Ops, int FI) const {
798 if (Ops.size() != 1) return NULL;
799
800 unsigned OpNum = Ops[0];
801 unsigned Opc = MI->getOpcode();
802 MachineInstr *NewMI = NULL;
803 switch (Opc) {
804 default: break;
805 case ARM::MOVr: {
806 if (MI->getOperand(4).getReg() == ARM::CPSR)
807 // If it is updating CPSR, then it cannot be folded.
808 break;
809 unsigned Pred = MI->getOperand(2).getImm();
810 unsigned PredReg = MI->getOperand(3).getReg();
811 if (OpNum == 0) { // move -> store
812 unsigned SrcReg = MI->getOperand(1).getReg();
813 bool isKill = MI->getOperand(1).isKill();
814 bool isUndef = MI->getOperand(1).isUndef();
815 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
816 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
817 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
818 } else { // move -> load
819 unsigned DstReg = MI->getOperand(0).getReg();
820 bool isDead = MI->getOperand(0).isDead();
821 bool isUndef = MI->getOperand(0).isUndef();
822 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
823 .addReg(DstReg,
824 RegState::Define |
825 getDeadRegState(isDead) |
826 getUndefRegState(isUndef))
827 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
828 }
100 switch (MBB.back().getOpcode()) {
101 case ARM::BX_RET: // Return.
102 case ARM::LDM_RET:
103 case ARM::B:
104 case ARM::BR_JTr: // Jumptable branch.
105 case ARM::BR_JTm: // Jumptable branch through mem.
106 case ARM::BR_JTadd: // Jumptable branch add to pc.
107 return true;
108 default:
829109 break;
830 }
831 case ARM::FCPYS: {
832 unsigned Pred = MI->getOperand(2).getImm();
833 unsigned PredReg = MI->getOperand(3).getReg();
834 if (OpNum == 0) { // move -> store
835 unsigned SrcReg = MI->getOperand(1).getReg();
836 bool isKill = MI->getOperand(1).isKill();
837 bool isUndef = MI->getOperand(1).isUndef();
838 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
839 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
840 .addFrameIndex(FI)
841 .addImm(0).addImm(Pred).addReg(PredReg);
842 } else { // move -> load
843 unsigned DstReg = MI->getOperand(0).getReg();
844 bool isDead = MI->getOperand(0).isDead();
845 bool isUndef = MI->getOperand(0).isUndef();
846 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
847 .addReg(DstReg,
848 RegState::Define |
849 getDeadRegState(isDead) |
850 getUndefRegState(isUndef))
851 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
852 }
853 break;
854 }
855 case ARM::FCPYD: {
856 unsigned Pred = MI->getOperand(2).getImm();
857 unsigned PredReg = MI->getOperand(3).getReg();
858 if (OpNum == 0) { // move -> store
859 unsigned SrcReg = MI->getOperand(1).getReg();
860 bool isKill = MI->getOperand(1).isKill();
861 bool isUndef = MI->getOperand(1).isUndef();
862 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
863 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
864 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
865 } else { // move -> load
866 unsigned DstReg = MI->getOperand(0).getReg();
867 bool isDead = MI->getOperand(0).isDead();
868 bool isUndef = MI->getOperand(0).isUndef();
869 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
870 .addReg(DstReg,
871 RegState::Define |
872 getDeadRegState(isDead) |
873 getUndefRegState(isUndef))
874 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
875 }
876 break;
877 }
878 }
879
880 return NewMI;
881 }
882
883 MachineInstr*
884 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
885 MachineInstr* MI,
886 const SmallVectorImpl &Ops,
887 MachineInstr* LoadMI) const {
888 return 0;
889 }
890
891 bool
892 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
893 const SmallVectorImpl &Ops) const {
894 if (Ops.size() != 1) return false;
895
896 unsigned Opc = MI->getOpcode();
897 switch (Opc) {
898 default: break;
899 case ARM::MOVr:
900 // If it is updating CPSR, then it cannot be folded.
901 return MI->getOperand(4).getReg() != ARM::CPSR;
902 case ARM::FCPYS:
903 case ARM::FCPYD:
904 return true;
905
906 case ARM::VMOVD:
907 case ARM::VMOVQ:
908 return false; // FIXME
909110 }
910111
911112 return false;
912113 }
114
115 void ARMInstrInfo::
116 reMaterialize(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator I,
118 unsigned DestReg,
119 const MachineInstr *Orig) const {
120 DebugLoc dl = Orig->getDebugLoc();
121 if (Orig->getOpcode() == ARM::MOVi2pieces) {
122 RI.emitLoadConstPool(MBB, I, this, dl,
123 DestReg,
124 Orig->getOperand(1).getImm(),
125 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
126 Orig->getOperand(3).getReg());
127 return;
128 }
129
130 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
131 MI->getOperand(0).setReg(DestReg);
132 MBB.insert(I, MI);
133 }
1414 #define ARMINSTRUCTIONINFO_H
1515
1616 #include "llvm/Target/TargetInstrInfo.h"
17 #include "ARMBaseInstrInfo.h"
1718 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
1820 #include "ARM.h"
1921
2022 namespace llvm {
2123 class ARMSubtarget;
2224
23 /// ARMII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
25 ///
26 namespace ARMII {
27 enum {
28 //===------------------------------------------------------------------===//
29 // Instruction Flags.
30
31 //===------------------------------------------------------------------===//
32 // This four-bit field describes the addressing mode used.
33
34 AddrModeMask = 0xf,
35 AddrModeNone = 0,
36 AddrMode1 = 1,
37 AddrMode2 = 2,
38 AddrMode3 = 3,
39 AddrMode4 = 4,
40 AddrMode5 = 5,
41 AddrMode6 = 6,
42 AddrModeT1_1 = 7,
43 AddrModeT1_2 = 8,
44 AddrModeT1_4 = 9,
45 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
46 AddrModeT2_i12 = 11,
47 AddrModeT2_i8 = 12,
48 AddrModeT2_so = 13,
49 AddrModeT2_pc = 14, // +/- i12 for pc relative data
50 AddrModeT2_i8s4 = 15, // i8 * 4
51
52 // Size* - Flags to keep track of the size of an instruction.
53 SizeShift = 4,
54 SizeMask = 7 << SizeShift,
55 SizeSpecial = 1, // 0 byte pseudo or special case.
56 Size8Bytes = 2,
57 Size4Bytes = 3,
58 Size2Bytes = 4,
59
60 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
61 // and store ops
62 IndexModeShift = 7,
63 IndexModeMask = 3 << IndexModeShift,
64 IndexModePre = 1,
65 IndexModePost = 2,
66
67 //===------------------------------------------------------------------===//
68 // Instruction encoding formats.
69 //
70 FormShift = 9,
71 FormMask = 0x3f << FormShift,
72
73 // Pseudo instructions
74 Pseudo = 0 << FormShift,
75
76 // Multiply instructions
77 MulFrm = 1 << FormShift,
78
79 // Branch instructions
80 BrFrm = 2 << FormShift,
81 BrMiscFrm = 3 << FormShift,
82
83 // Data Processing instructions
84 DPFrm = 4 << FormShift,
85 DPSoRegFrm = 5 << FormShift,
86
87 // Load and Store
88 LdFrm = 6 << FormShift,
89 StFrm = 7 << FormShift,
90 LdMiscFrm = 8 << FormShift,
91 StMiscFrm = 9 << FormShift,
92 LdStMulFrm = 10 << FormShift,
93
94 // Miscellaneous arithmetic instructions
95 ArithMiscFrm = 11 << FormShift,
96
97 // Extend instructions
98 ExtFrm = 12 << FormShift,
99
100 // VFP formats
101 VFPUnaryFrm = 13 << FormShift,
102 VFPBinaryFrm = 14 << FormShift,
103 VFPConv1Frm = 15 << FormShift,
104 VFPConv2Frm = 16 << FormShift,
105 VFPConv3Frm = 17 << FormShift,
106 VFPConv4Frm = 18 << FormShift,
107 VFPConv5Frm = 19 << FormShift,
108 VFPLdStFrm = 20 << FormShift,
109 VFPLdStMulFrm = 21 << FormShift,
110 VFPMiscFrm = 22 << FormShift,
111
112 // Thumb format
113 ThumbFrm = 23 << FormShift,
114
115 // NEON format
116 NEONFrm = 24 << FormShift,
117 NEONGetLnFrm = 25 << FormShift,
118 NEONSetLnFrm = 26 << FormShift,
119 NEONDupFrm = 27 << FormShift,
120
121 //===------------------------------------------------------------------===//
122 // Misc flags.
123
124 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
125 // it doesn't have a Rn operand.
126 UnaryDP = 1 << 15,
127
128 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
129 // a 16-bit Thumb instruction if certain conditions are met.
130 Xform16Bit = 1 << 16,
131
132 //===------------------------------------------------------------------===//
133 // Field shifts - such shifts are used to set field while generating
134 // machine instructions.
135 M_BitShift = 5,
136 ShiftImmShift = 5,
137 ShiftShift = 7,
138 N_BitShift = 7,
139 ImmHiShift = 8,
140 SoRotImmShift = 8,
141 RegRsShift = 8,
142 ExtRotImmShift = 10,
143 RegRdLoShift = 12,
144 RegRdShift = 12,
145 RegRdHiShift = 16,
146 RegRnShift = 16,
147 S_BitShift = 20,
148 W_BitShift = 21,
149 AM3_I_BitShift = 22,
150 D_BitShift = 22,
151 U_BitShift = 23,
152 P_BitShift = 24,
153 I_BitShift = 25,
154 CondShift = 28
155 };
156 }
157
158 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
159 protected:
160 // Can be only subclassed.
161 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
162 public:
163 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
164 MachineBasicBlock::iterator &MBBI,
165 LiveVariables *LV) const;
166
167 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
168
169 // Branch analysis.
170 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
171 MachineBasicBlock *&FBB,
172 SmallVectorImpl &Cond,
173 bool AllowModify) const;
174 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
175 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
176 MachineBasicBlock *FBB,
177 const SmallVectorImpl &Cond) const;
178
179 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
180 virtual
181 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
182
183 // Predication support.
184 virtual bool isPredicated(const MachineInstr *MI) const;
185
186 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
187 int PIdx = MI->findFirstPredOperandIdx();
188 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
189 : ARMCC::AL;
190 }
191
192 virtual
193 bool PredicateInstruction(MachineInstr *MI,
194 const SmallVectorImpl &Pred) const;
195
196 virtual
197 bool SubsumesPredicate(const SmallVectorImpl &Pred1,
198 const SmallVectorImpl &Pred2) const;
199
200 virtual bool DefinesPredicate(MachineInstr *MI,
201 std::vector &Pred) const;
202
203 /// GetInstSize - Returns the size of the specified MachineInstr.
204 ///
205 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
206
207 /// Return true if the instruction is a register to register move and return
208 /// the source and dest operands and their sub-register indices by reference.
209 virtual bool isMoveInstr(const MachineInstr &MI,
210 unsigned &SrcReg, unsigned &DstReg,
211 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
212
213 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
214 int &FrameIndex) const;
215 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
216 int &FrameIndex) const;
217
218 virtual bool copyRegToReg(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator I,
220 unsigned DestReg, unsigned SrcReg,
221 const TargetRegisterClass *DestRC,
222 const TargetRegisterClass *SrcRC) const;
223 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator MBBI,
225 unsigned SrcReg, bool isKill, int FrameIndex,
226 const TargetRegisterClass *RC) const;
227
228 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
229 SmallVectorImpl &Addr,
230 const TargetRegisterClass *RC,
231 SmallVectorImpl &NewMIs) const;
232
233 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MBBI,
235 unsigned DestReg, int FrameIndex,
236 const TargetRegisterClass *RC) const;
237
238 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
239 SmallVectorImpl &Addr,
240 const TargetRegisterClass *RC,
241 SmallVectorImpl &NewMIs) const;
242
243 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
244 const SmallVectorImpl &Ops) const;
245
246 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
247 MachineInstr* MI,
248 const SmallVectorImpl &Ops,
249 int FrameIndex) const;
250
251 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
252 MachineInstr* MI,
253 const SmallVectorImpl &Ops,
254 MachineInstr* LoadMI) const;
255 };
256
25725 class ARMInstrInfo : public ARMBaseInstrInfo {
25826 ARMRegisterInfo RI;
25927 public:
26028 explicit ARMInstrInfo(const ARMSubtarget &STI);
29
30 // Return the non-pre/post incrementing version of 'Opc'. Return 0
31 // if there is not such an opcode.
32 unsigned getUnindexedOpcode(unsigned Opc) const;
33
34 // Return the opcode that implements 'Op', or 0 if no opcode
35 unsigned getOpcode(ARMII::Op Op) const;
36
37 // Return true if the block does not fall through.
38 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
26139
26240 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
26341 /// such, whenever a client has an instance of instruction info, it should
156156 let isReturn = 1, isTerminator = 1 in {
157157 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
158158 // Alternative return instruction used by vararg functions.
159 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
159 def tBX_RET_vararg : T1I<(outs), (ins tGPR:$target), "bx $target", []>;
160160 }
161161
162162 // FIXME: remove when we have a way to marking a MI with these properties.
163163 let isReturn = 1, isTerminator = 1 in
164 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
164 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
165165 "pop $dst1", []>;
166166
167167 let isCall = 1,
168168 Defs = [R0, R1, R2, R3, LR,
169169 D0, D1, D2, D3, D4, D5, D6, D7] in {
170 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
170 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
171171 "bl ${func:call}",
172172 [(ARMtcall tglobaladdr:$func)]>;
173173 // ARMv5T and above
174 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
174 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
175175 "blx ${func:call}",
176176 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
177 def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops),
177 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
178178 "blx $func",
179179 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
180180 // ARMv4T
181 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
181 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
182182 "cpy lr, pc\n\tbx $func",
183183 [(ARMcall_nolink tGPR:$func)]>;
184184 }
283283 // TODO: A7-44: LDMIA - load multiple
284284
285285 let mayLoad = 1 in
286 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
286 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
287287 "pop $dst1", []>;
288288
289289 let mayStore = 1 in
290 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
290 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
291291 "push $src1", []>;
292292
293293 //===----------------------------------------------------------------------===//
576576
577577 // tLEApcrel - Load a pc-relative address into a register without offending the
578578 // assembler.
579 def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label),
579 def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label),
580580 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
581581 "${:private}PCRELL${:uid}+4))\n"),
582582 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
583583 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
584584 []>;
585585
586 def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
586 def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
587587 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
588588 "${:private}PCRELL${:uid}+4))\n"),
589589 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
597597 // __aeabi_read_tp preserves the registers r1-r3.
598598 let isCall = 1,
599599 Defs = [R0, LR] in {
600 def tTPsoft : TIx2<(outs), (ins),
600 def tTPsoft : T1Ix2<(outs), (ins),
601601 "bl __aeabi_read_tp",
602602 [(set R0, ARMthread_pointer)]>;
603603 }
10471047 RegConstraint<"$false = $dst">;
10481048
10491049 //===----------------------------------------------------------------------===//
1050 // TLS Instructions
1051 //
1052
1053 // __aeabi_read_tp preserves the registers r1-r3.
1054 let isCall = 1,
1055 Defs = [R0, R12, LR, CPSR] in {
1056 def t2TPsoft : T2XI<(outs), (ins),
1057 "bl __aeabi_read_tp",
1058 [(set R0, ARMthread_pointer)]>;
1059 }
1060
1061 //===----------------------------------------------------------------------===//
10501062 // Control-Flow Instructions
10511063 //
1064
1065 //let isReturn = 1, isTerminator = 1 in
1066 // def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
1067 //
1068 // On non-Darwin platforms R9 is callee-saved.
1069 //let isCall = 1,
1070 // Defs = [R0, R1, R2, R3, R12, LR,
1071 // D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1072 //def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1073 // "bl ${func:call}",
1074 // [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1075 //
1076 //def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1077 // "blx $func",
1078 // [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1079 //}
1080
1081 // On Darwin R9 is call-clobbered.
1082 //let isCall = 1,
1083 // Defs = [R0, R1, R2, R3, R9, R12, LR,
1084 // D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1085 //def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1086 // "bl ${func:call}",
1087 // [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1088 //
1089 //def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1090 // "blx $func",
1091 // [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1092 //}
10521093
10531094 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
10541095 let isPredicable = 1 in
1111 tablegen(ARMGenSubtarget.inc -gen-subtarget)
1212
1313 add_llvm_target(ARMCodeGen
14 ARMBaseInstrInfo.cpp
1415 ARMCodeEmitter.cpp
1516 ARMConstantIslandPass.cpp
1617 ARMConstantPoolValue.cpp
2323
2424 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
2525 : ARMBaseInstrInfo(STI), RI(*this, STI) {
26 }
27
28 unsigned Thumb1InstrInfo::
29 getUnindexedOpcode(unsigned Opc) const {
30 return 0;
31 }
32
33 unsigned Thumb1InstrInfo::
34 getOpcode(ARMII::Op Op) const {
35 switch (Op) {
36 case ARMII::ADDri: return ARM::tADDi8;
37 case ARMII::ADDrs: return 0;
38 case ARMII::ADDrr: return ARM::tADDrr;
39 case ARMII::B: return ARM::tB;
40 case ARMII::Bcc: return ARM::tBcc;
41 case ARMII::BR_JTr: return ARM::tBR_JTr;
42 case ARMII::BR_JTm: return 0;
43 case ARMII::BR_JTadd: return 0;
44 case ARMII::FCPYS: return 0;
45 case ARMII::FCPYD: return 0;
46 case ARMII::FLDD: return 0;
47 case ARMII::FLDS: return 0;
48 case ARMII::FSTD: return 0;
49 case ARMII::FSTS: return 0;
50 case ARMII::LDR: return ARM::tLDR;
51 case ARMII::MOVr: return ARM::tMOVr;
52 case ARMII::STR: return ARM::tSTR;
53 case ARMII::SUBri: return ARM::tSUBi8;
54 case ARMII::SUBrs: return 0;
55 case ARMII::SUBrr: return ARM::tSUBrr;
56 case ARMII::VMOVD: return 0;
57 case ARMII::VMOVQ: return 0;
58 default:
59 break;
60 }
61
62 return 0;
63 }
64
65 bool
66 Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
67 if (MBB.empty()) return false;
68
69 switch (MBB.back().getOpcode()) {
70 case ARM::tBX_RET:
71 case ARM::tBX_RET_vararg:
72 case ARM::tPOP_RET:
73 case ARM::tB:
74 case ARM::tBR_JTr:
75 return true;
76 default:
77 break;
78 }
79
80 return false;
2681 }
2782
2883 bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
2525 Thumb1RegisterInfo RI;
2626 public:
2727 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
28
29 // Return the non-pre/post incrementing version of 'Opc'. Return 0
30 // if there is not such an opcode.
31 unsigned getUnindexedOpcode(unsigned Opc) const;
32
33 // Return the opcode that implements 'Op', or 0 if no opcode
34 unsigned getOpcode(ARMII::Op Op) const;
35
36 // Return true if the block does not fall through.
37 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
2838
2939 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3040 /// such, whenever a client has an instance of instruction info, it should
2525 : ARMBaseInstrInfo(STI), RI(*this, STI) {
2626 }
2727
28 unsigned Thumb2InstrInfo::
29 getUnindexedOpcode(unsigned Opc) const {
30 // FIXME
31 return 0;
32 }
33
34 unsigned Thumb2InstrInfo::
35 getOpcode(ARMII::Op Op) const {
36 switch (Op) {
37 case ARMII::ADDri: return ARM::t2ADDri;
38 case ARMII::ADDrs: return ARM::t2ADDrs;
39 case ARMII::ADDrr: return ARM::t2ADDrr;
40 case ARMII::B: return ARM::t2B;
41 case ARMII::Bcc: return ARM::t2Bcc;
42 case ARMII::BR_JTr: return ARM::t2BR_JTr;
43 case ARMII::BR_JTm: return ARM::t2BR_JTm;
44 case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
45 case ARMII::FCPYS: return ARM::FCPYS;
46 case ARMII::FCPYD: return ARM::FCPYD;
47 case ARMII::FLDD: return ARM::FLDD;
48 case ARMII::FLDS: return ARM::FLDS;
49 case ARMII::FSTD: return ARM::FSTD;
50 case ARMII::FSTS: return ARM::FSTS;
51 case ARMII::LDR: return ARM::LDR; // FIXME
52 case ARMII::MOVr: return ARM::t2MOVr;
53 case ARMII::STR: return ARM::STR; // FIXME
54 case ARMII::SUBri: return ARM::t2SUBri;
55 case ARMII::SUBrs: return ARM::t2SUBrs;
56 case ARMII::SUBrr: return ARM::t2SUBrr;
57 case ARMII::VMOVD: return ARM::VMOVD;
58 case ARMII::VMOVQ: return ARM::VMOVQ;
59 default:
60 break;
61 }
62
63 return 0;
64 }
65
66 bool
67 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
68 if (MBB.empty()) return false;
69
70 // FIXME
71 switch (MBB.back().getOpcode()) {
72 //case ARM::t2BX_RET:
73 // case ARM::LDM_RET:
74 case ARM::t2B: // Uncond branch.
75 case ARM::t2BR_JTr: // Jumptable branch.
76 case ARM::t2BR_JTm: // Jumptable branch through mem.
77 case ARM::t2BR_JTadd: // Jumptable branch add to pc.
78 return true;
79 case ARM::tBX_RET:
80 case ARM::tBX_RET_vararg:
81 case ARM::tPOP_RET:
82 case ARM::tB:
83 case ARM::tBR_JTr:
84 return true;
85 default:
86 break;
87 }
88
89 return false;
90 }
91
92
93 bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator I,
95 unsigned DestReg, unsigned SrcReg,
96 const TargetRegisterClass *DestRC,
97 const TargetRegisterClass *SrcRC) const {
98 DebugLoc DL = DebugLoc::getUnknownLoc();
99 if (I != MBB.end()) DL = I->getDebugLoc();
100
101 if (DestRC == ARM::GPRRegisterClass) {
102 if (SrcRC == ARM::GPRRegisterClass) {
103 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
104 } else if (SrcRC == ARM::tGPRRegisterClass) {
105 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
106 return true;
107 }
108 } else if (DestRC == ARM::tGPRRegisterClass) {
109 if (SrcRC == ARM::GPRRegisterClass) {
110 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
111 return true;
112 } else if (SrcRC == ARM::tGPRRegisterClass) {
113 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
114 return true;
115 }
116 }
117
118 return false;
119 }
120
121
122
123
124
125
28126 bool Thumb2InstrInfo::isMoveInstr(const MachineInstr &MI,
29127 unsigned &SrcReg, unsigned &DstReg,
30128 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
34132 switch (oc) {
35133 default:
36134 return false;
37 // FIXME: Thumb2
38135 case ARM::tMOVr:
39136 case ARM::tMOVhir2lor:
40137 case ARM::tMOVlor2hir:
53150 int &FrameIndex) const {
54151 switch (MI->getOpcode()) {
55152 default: break;
56 // FIXME: Thumb2
57153 case ARM::tRestore:
58154 if (MI->getOperand(1).isFI() &&
59155 MI->getOperand(2).isImm() &&
70166 int &FrameIndex) const {
71167 switch (MI->getOpcode()) {
72168 default: break;
73 // FIXME: Thumb2
74169 case ARM::tSpill:
75170 if (MI->getOperand(1).isFI() &&
76171 MI->getOperand(2).isImm() &&
81176 break;
82177 }
83178 return 0;
84 }
85
86 bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I,
88 unsigned DestReg, unsigned SrcReg,
89 const TargetRegisterClass *DestRC,
90 const TargetRegisterClass *SrcRC) const {
91 DebugLoc DL = DebugLoc::getUnknownLoc();
92 if (I != MBB.end()) DL = I->getDebugLoc();
93
94 // FIXME: Thumb2
95 if (DestRC == ARM::GPRRegisterClass) {
96 if (SrcRC == ARM::GPRRegisterClass) {
97 BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
98 return true;
99 } else if (SrcRC == ARM::tGPRRegisterClass) {
100 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
101 return true;
102 }
103 } else if (DestRC == ARM::tGPRRegisterClass) {
104 if (SrcRC == ARM::GPRRegisterClass) {
105 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
106 return true;
107 } else if (SrcRC == ARM::tGPRRegisterClass) {
108 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
109 return true;
110 }
111 }
112
113 return false;
114179 }
115180
116181 bool Thumb2InstrInfo::
153218
154219 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
155220
156 // FIXME: Thumb2
157221 if (RC == ARM::tGPRRegisterClass) {
158222 BuildMI(MBB, I, DL, get(ARM::tSpill))
159223 .addReg(SrcReg, getKillRegState(isKill))
169233 DebugLoc DL = DebugLoc::getUnknownLoc();
170234 unsigned Opc = 0;
171235
172 // FIXME: Thumb2. Is GPRRegClass here correct?
173236 assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
174237 if (RC == ARM::GPRRegisterClass) {
175238 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
190253 DebugLoc DL = DebugLoc::getUnknownLoc();
191254 if (I != MBB.end()) DL = I->getDebugLoc();
192255
193 // FIXME: Thumb2
194256 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
195257
196258 if (RC == ARM::tGPRRegisterClass) {
207269 DebugLoc DL = DebugLoc::getUnknownLoc();
208270 unsigned Opc = 0;
209271
210 // FIXME: Thumb2. Is GPRRegClass ok here?
211272 if (RC == ARM::GPRRegisterClass) {
212273 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
213274 }
2626 public:
2727 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
2828
29 // Return the non-pre/post incrementing version of 'Opc'. Return 0
30 // if there is not such an opcode.
31 unsigned getUnindexedOpcode(unsigned Opc) const;
32
33 // Return the opcode that implements 'Op', or 0 if no opcode
34 unsigned getOpcode(ARMII::Op Op) const;
35
36 // Return true if the block does not fall through.
37 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
38
2939 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3040 /// such, whenever a client has an instance of instruction info, it should
3141 /// always be able to get register info as well (through this method).
3242 ///
3343 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
44
45 bool copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator I,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC) const;
50
51
52
3453
3554 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
3655 MachineBasicBlock::iterator MI,
4766 unsigned isStoreToStackSlot(const MachineInstr *MI,
4867 int &FrameIndex) const;
4968
50 bool copyRegToReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I,
52 unsigned DestReg, unsigned SrcReg,
53 const TargetRegisterClass *DestRC,
54 const TargetRegisterClass *SrcRC) const;
5569 void storeRegToStackSlot(MachineBasicBlock &MBB,
5670 MachineBasicBlock::iterator MBBI,
5771 unsigned SrcReg, bool isKill, int FrameIndex,
7993 MachineInstr* MI,
8094 const SmallVectorImpl &Ops,
8195 int FrameIndex) const;
82
96
8397 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
8498 MachineInstr* MI,
8599 const SmallVectorImpl &Ops,
86100 MachineInstr* LoadMI) const {
87101 return 0;
88102 }
103
104
89105 };
90106 }
91107
0 ; XFAIL: *
1 ; fixme
2 ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mov | count 3
13 ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep mvn | count 1
24