llvm.org GIT mirror llvm / 3346491
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 9 years ago
82 changed file(s) with 4284 addition(s) and 3361 deletion(s). Raw diff Collapse all Expand all
1616 #include
1717
1818 namespace llvm {
19 class MachineFunction;
20 class MachineBasicBlock;
1921
2022 /// Information about stack frame layout on the target. It holds the direction
2123 /// of stack growth, the known stack alignment on entry to each function, and
8991 NumEntries = 0;
9092 return 0;
9193 }
94
95 /// targetHandlesStackFrameRounding - Returns true if the target is
96 /// responsible for rounding up the stack frame (probably at emitPrologue
97 /// time).
98 virtual bool targetHandlesStackFrameRounding() const {
99 return false;
100 }
101
102 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
103 /// the function.
104 virtual void emitPrologue(MachineFunction &MF) const = 0;
105 virtual void emitEpilogue(MachineFunction &MF,
106 MachineBasicBlock &MBB) const = 0;
92107 };
93108
94109 } // End llvm namespace
576576 // Do nothing.
577577 }
578578
579 /// targetHandlesStackFrameRounding - Returns true if the target is
580 /// responsible for rounding up the stack frame (probably at emitPrologue
581 /// time).
582 virtual bool targetHandlesStackFrameRounding() const {
583 return false;
584 }
585
586579 /// requiresRegisterScavenging - returns true if the target requires (and can
587580 /// make use of) the register scavenger.
588581 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
747740 /// instruction.
748741 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
749742 int SPAdj, RegScavenger *RS=NULL) const = 0;
750
751 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
752 /// the function.
753 virtual void emitPrologue(MachineFunction &MF) const = 0;
754 virtual void emitEpilogue(MachineFunction &MF,
755 MachineBasicBlock &MBB) const = 0;
756743
757744 //===--------------------------------------------------------------------===//
758745 /// Debug information queries.
640640 AdjustStackOffset(MFI, SFI, StackGrowsDown, Offset, MaxAlign);
641641 }
642642
643 if (!RegInfo->targetHandlesStackFrameRounding()) {
643 if (!TFI.targetHandlesStackFrameRounding()) {
644644 // If we have reserved argument space for call sites in the function
645645 // immediately on entry to the current function, count it as part of the
646646 // overall stack size.
675675 /// prolog and epilog code to the function.
676676 ///
677677 void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
678 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
678 const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
679679
680680 // Add prologue to the function...
681 TRI->emitPrologue(Fn);
681 TFI.emitPrologue(Fn);
682682
683683 // Add epilogue to restore the callee-save registers in each exiting block
684684 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
685685 // If last instruction is a return instruction, add an epilogue
686686 if (!I->empty() && I->back().getDesc().isReturn())
687 TRI->emitEpilogue(Fn, *I);
687 TFI.emitEpilogue(Fn, *I);
688688 }
689689 }
690690
16581658 }
16591659 }
16601660
1661 /// Move iterator past the next bunch of callee save load / store ops for
1662 /// the particular spill area (1: integer area 1, 2: integer area 2,
1663 /// 3: fp area, 0: don't care).
1664 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1665 MachineBasicBlock::iterator &MBBI,
1666 int Opc1, int Opc2, unsigned Area,
1667 const ARMSubtarget &STI) {
1668 while (MBBI != MBB.end() &&
1669 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1670 MBBI->getOperand(1).isFI()) {
1671 if (Area != 0) {
1672 bool Done = false;
1673 unsigned Category = 0;
1674 switch (MBBI->getOperand(0).getReg()) {
1675 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1676 case ARM::LR:
1677 Category = 1;
1678 break;
1679 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1680 Category = STI.isTargetDarwin() ? 2 : 1;
1681 break;
1682 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1683 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1684 Category = 3;
1685 break;
1686 default:
1687 Done = true;
1688 break;
1689 }
1690 if (Done || Category != Area)
1691 break;
1692 }
1693
1694 ++MBBI;
1695 }
1696 }
1697
1698 void ARMBaseRegisterInfo::
1699 emitPrologue(MachineFunction &MF) const {
1700 MachineBasicBlock &MBB = MF.front();
1701 MachineBasicBlock::iterator MBBI = MBB.begin();
1702 MachineFrameInfo *MFI = MF.getFrameInfo();
1703 ARMFunctionInfo *AFI = MF.getInfo();
1704 assert(!AFI->isThumb1OnlyFunction() &&
1705 "This emitPrologue does not support Thumb1!");
1706 bool isARM = !AFI->isThumbFunction();
1707 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1708 unsigned NumBytes = MFI->getStackSize();
1709 const std::vector &CSI = MFI->getCalleeSavedInfo();
1710 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1711
1712 // Determine the sizes of each callee-save spill areas and record which frame
1713 // belongs to which callee-save spill areas.
1714 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1715 int FramePtrSpillFI = 0;
1716
1717 // Allocate the vararg register save area. This is not counted in NumBytes.
1718 if (VARegSaveSize)
1719 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1720
1721 if (!AFI->hasStackFrame()) {
1722 if (NumBytes != 0)
1723 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1724 return;
1725 }
1726
1727 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1728 unsigned Reg = CSI[i].getReg();
1729 int FI = CSI[i].getFrameIdx();
1730 switch (Reg) {
1731 case ARM::R4:
1732 case ARM::R5:
1733 case ARM::R6:
1734 case ARM::R7:
1735 case ARM::LR:
1736 if (Reg == FramePtr)
1737 FramePtrSpillFI = FI;
1738 AFI->addGPRCalleeSavedArea1Frame(FI);
1739 GPRCS1Size += 4;
1740 break;
1741 case ARM::R8:
1742 case ARM::R9:
1743 case ARM::R10:
1744 case ARM::R11:
1745 if (Reg == FramePtr)
1746 FramePtrSpillFI = FI;
1747 if (STI.isTargetDarwin()) {
1748 AFI->addGPRCalleeSavedArea2Frame(FI);
1749 GPRCS2Size += 4;
1750 } else {
1751 AFI->addGPRCalleeSavedArea1Frame(FI);
1752 GPRCS1Size += 4;
1753 }
1754 break;
1755 default:
1756 AFI->addDPRCalleeSavedAreaFrame(FI);
1757 DPRCSSize += 8;
1758 }
1759 }
1760
1761 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1762 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1763 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
1764
1765 // Set FP to point to the stack slot that contains the previous FP.
1766 // For Darwin, FP is R7, which has now been stored in spill area 1.
1767 // Otherwise, if this is not Darwin, all the callee-saved registers go
1768 // into spill area 1, including the FP in R11. In either case, it is
1769 // now safe to emit this assignment.
1770 bool HasFP = hasFP(MF);
1771 if (HasFP) {
1772 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1773 MachineInstrBuilder MIB =
1774 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1775 .addFrameIndex(FramePtrSpillFI).addImm(0);
1776 AddDefaultCC(AddDefaultPred(MIB));
1777 }
1778
1779 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1780 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1781
1782 // Build the new SUBri to adjust SP for FP callee-save spill area.
1783 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
1784 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1785
1786 // Determine starting offsets of spill areas.
1787 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1788 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1789 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1790 if (HasFP)
1791 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1792 NumBytes);
1793 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1794 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1795 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1796
1797 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1798 NumBytes = DPRCSOffset;
1799 if (NumBytes) {
1800 // Adjust SP after all the callee-save spills.
1801 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1802 if (HasFP)
1803 AFI->setShouldRestoreSPFromFP(true);
1804 }
1805
1806 if (STI.isTargetELF() && hasFP(MF)) {
1807 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1808 AFI->getFramePtrSpillOffset());
1809 AFI->setShouldRestoreSPFromFP(true);
1810 }
1811
1812 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1813 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1814 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1815
1816 // If we need dynamic stack realignment, do it here. Be paranoid and make
1817 // sure if we also have VLAs, we have a base pointer for frame access.
1818 if (needsStackRealignment(MF)) {
1819 unsigned MaxAlign = MFI->getMaxAlignment();
1820 assert (!AFI->isThumb1OnlyFunction());
1821 if (!AFI->isThumbFunction()) {
1822 // Emit bic sp, sp, MaxAlign
1823 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1824 TII.get(ARM::BICri), ARM::SP)
1825 .addReg(ARM::SP, RegState::Kill)
1826 .addImm(MaxAlign-1)));
1827 } else {
1828 // We cannot use sp as source/dest register here, thus we're emitting the
1829 // following sequence:
1830 // mov r4, sp
1831 // bic r4, r4, MaxAlign
1832 // mov sp, r4
1833 // FIXME: It will be better just to find spare register here.
1834 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1835 .addReg(ARM::SP, RegState::Kill);
1836 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1837 TII.get(ARM::t2BICri), ARM::R4)
1838 .addReg(ARM::R4, RegState::Kill)
1839 .addImm(MaxAlign-1)));
1840 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1841 .addReg(ARM::R4, RegState::Kill);
1842 }
1843
1844 AFI->setShouldRestoreSPFromFP(true);
1845 }
1846
1847 // If we need a base pointer, set it up here. It's whatever the value
1848 // of the stack pointer is at this point. Any variable size objects
1849 // will be allocated after this, so we can still use the base pointer
1850 // to reference locals.
1851 if (hasBasePointer(MF)) {
1852 if (isARM)
1853 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1854 .addReg(ARM::SP)
1855 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1856 else
1857 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1858 .addReg(ARM::SP);
1859 }
1860
1861 // If the frame has variable sized objects then the epilogue must restore
1862 // the sp from fp.
1863 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1864 AFI->setShouldRestoreSPFromFP(true);
1865 }
1866
1867 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1868 for (unsigned i = 0; CSRegs[i]; ++i)
1869 if (Reg == CSRegs[i])
1870 return true;
1871 return false;
1872 }
1873
1874 static bool isCSRestore(MachineInstr *MI,
1875 const ARMBaseInstrInfo &TII,
1876 const unsigned *CSRegs) {
1877 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1878 MI->getOpcode() == (int)ARM::LDRi12 ||
1879 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1880 MI->getOperand(1).isFI() &&
1881 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1882 }
1883
1884 void ARMBaseRegisterInfo::
1885 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1886 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1887 assert(MBBI->getDesc().isReturn() &&
1888 "Can only insert epilog into returning blocks");
1889 unsigned RetOpcode = MBBI->getOpcode();
1890 DebugLoc dl = MBBI->getDebugLoc();
1891 MachineFrameInfo *MFI = MF.getFrameInfo();
1892 ARMFunctionInfo *AFI = MF.getInfo();
1893 assert(!AFI->isThumb1OnlyFunction() &&
1894 "This emitEpilogue does not support Thumb1!");
1895 bool isARM = !AFI->isThumbFunction();
1896
1897 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1898 int NumBytes = (int)MFI->getStackSize();
1899
1900 if (!AFI->hasStackFrame()) {
1901 if (NumBytes != 0)
1902 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1903 } else {
1904 // Unwind MBBI to point to first LDR / VLDRD.
1905 const unsigned *CSRegs = getCalleeSavedRegs();
1906 if (MBBI != MBB.begin()) {
1907 do
1908 --MBBI;
1909 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1910 if (!isCSRestore(MBBI, TII, CSRegs))
1911 ++MBBI;
1912 }
1913
1914 // Move SP to start of FP callee save spill area.
1915 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1916 AFI->getGPRCalleeSavedArea2Size() +
1917 AFI->getDPRCalleeSavedAreaSize());
1918
1919 // Reset SP based on frame pointer only if the stack frame extends beyond
1920 // frame pointer stack slot or target is ELF and the function has FP.
1921 if (AFI->shouldRestoreSPFromFP()) {
1922 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1923 if (NumBytes) {
1924 if (isARM)
1925 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1926 ARMCC::AL, 0, TII);
1927 else
1928 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1929 ARMCC::AL, 0, TII);
1930 } else {
1931 // Thumb2 or ARM.
1932 if (isARM)
1933 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1934 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1935 else
1936 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1937 .addReg(FramePtr);
1938 }
1939 } else if (NumBytes)
1940 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1941
1942 // Move SP to start of integer callee save spill area 2.
1943 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1944 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1945
1946 // Move SP to start of integer callee save spill area 1.
1947 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
1948 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1949
1950 // Move SP to SP upon entry to the function.
1951 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
1952 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1953 }
1954
1955 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1956 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1957 // Tail call return: adjust the stack pointer and jump to callee.
1958 MBBI = prior(MBB.end());
1959 MachineOperand &JumpTarget = MBBI->getOperand(0);
1960
1961 // Jump to label or value in register.
1962 if (RetOpcode == ARM::TCRETURNdi) {
1963 BuildMI(MBB, MBBI, dl,
1964 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1965 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1966 JumpTarget.getTargetFlags());
1967 } else if (RetOpcode == ARM::TCRETURNdiND) {
1968 BuildMI(MBB, MBBI, dl,
1969 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1970 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1971 JumpTarget.getTargetFlags());
1972 } else if (RetOpcode == ARM::TCRETURNri) {
1973 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1974 addReg(JumpTarget.getReg(), RegState::Kill);
1975 } else if (RetOpcode == ARM::TCRETURNriND) {
1976 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1977 addReg(JumpTarget.getReg(), RegState::Kill);
1978 }
1979
1980 MachineInstr *NewMI = prior(MBBI);
1981 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1982 NewMI->addOperand(MBBI->getOperand(i));
1983
1984 // Delete the pseudo instruction TCRETURN.
1985 MBB.erase(MBBI);
1986 }
1987
1988 if (VARegSaveSize)
1989 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1990 }
1991
19921661 #include "ARMGenRegisterInfo.inc"
121121 // Debug information queries.
122122 unsigned getRARegister() const;
123123 unsigned getFrameRegister(const MachineFunction &MF) const;
124 unsigned getBaseRegister() const { return BasePtr; };
124125 int getFrameIndexReference(const MachineFunction &MF, int FI,
125126 unsigned &FrameReg) const;
126127 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
165166 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
166167 int SPAdj, RegScavenger *RS = NULL) const;
167168
168 virtual void emitPrologue(MachineFunction &MF) const;
169 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
170
171169 private:
172170 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
173171
0 //=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMFrameInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19
20 using namespace llvm;
21
22 /// Move iterator past the next bunch of callee save load / store ops for
23 /// the particular spill area (1: integer area 1, 2: integer area 2,
24 /// 3: fp area, 0: don't care).
25 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
26 MachineBasicBlock::iterator &MBBI,
27 int Opc1, int Opc2, unsigned Area,
28 const ARMSubtarget &STI) {
29 while (MBBI != MBB.end() &&
30 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
31 MBBI->getOperand(1).isFI()) {
32 if (Area != 0) {
33 bool Done = false;
34 unsigned Category = 0;
35 switch (MBBI->getOperand(0).getReg()) {
36 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
37 case ARM::LR:
38 Category = 1;
39 break;
40 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
41 Category = STI.isTargetDarwin() ? 2 : 1;
42 break;
43 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
44 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
45 Category = 3;
46 break;
47 default:
48 Done = true;
49 break;
50 }
51 if (Done || Category != Area)
52 break;
53 }
54
55 ++MBBI;
56 }
57 }
58
59 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
60 for (unsigned i = 0; CSRegs[i]; ++i)
61 if (Reg == CSRegs[i])
62 return true;
63 return false;
64 }
65
66 static bool isCSRestore(MachineInstr *MI,
67 const ARMBaseInstrInfo &TII,
68 const unsigned *CSRegs) {
69 return ((MI->getOpcode() == (int)ARM::VLDRD ||
70 MI->getOpcode() == (int)ARM::LDRi12 ||
71 MI->getOpcode() == (int)ARM::t2LDRi12) &&
72 MI->getOperand(1).isFI() &&
73 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
74 }
75
76 static void
77 emitSPUpdate(bool isARM,
78 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
79 DebugLoc dl, const ARMBaseInstrInfo &TII,
80 int NumBytes,
81 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
82 if (isARM)
83 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
84 Pred, PredReg, TII);
85 else
86 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
87 Pred, PredReg, TII);
88 }
89
90 void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
91 MachineBasicBlock &MBB = MF.front();
92 MachineBasicBlock::iterator MBBI = MBB.begin();
93 MachineFrameInfo *MFI = MF.getFrameInfo();
94 ARMFunctionInfo *AFI = MF.getInfo();
95 const ARMBaseRegisterInfo *RegInfo =
96 static_cast(MF.getTarget().getRegisterInfo());
97 const ARMBaseInstrInfo &TII =
98 *static_cast(MF.getTarget().getInstrInfo());
99 assert(!AFI->isThumb1OnlyFunction() &&
100 "This emitPrologue does not support Thumb1!");
101 bool isARM = !AFI->isThumbFunction();
102 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
103 unsigned NumBytes = MFI->getStackSize();
104 const std::vector &CSI = MFI->getCalleeSavedInfo();
105 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
106 unsigned FramePtr = RegInfo->getFrameRegister(MF);
107
108 // Determine the sizes of each callee-save spill areas and record which frame
109 // belongs to which callee-save spill areas.
110 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
111 int FramePtrSpillFI = 0;
112
113 // Allocate the vararg register save area. This is not counted in NumBytes.
114 if (VARegSaveSize)
115 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
116
117 if (!AFI->hasStackFrame()) {
118 if (NumBytes != 0)
119 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
120 return;
121 }
122
123 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
124 unsigned Reg = CSI[i].getReg();
125 int FI = CSI[i].getFrameIdx();
126 switch (Reg) {
127 case ARM::R4:
128 case ARM::R5:
129 case ARM::R6:
130 case ARM::R7:
131 case ARM::LR:
132 if (Reg == FramePtr)
133 FramePtrSpillFI = FI;
134 AFI->addGPRCalleeSavedArea1Frame(FI);
135 GPRCS1Size += 4;
136 break;
137 case ARM::R8:
138 case ARM::R9:
139 case ARM::R10:
140 case ARM::R11:
141 if (Reg == FramePtr)
142 FramePtrSpillFI = FI;
143 if (STI.isTargetDarwin()) {
144 AFI->addGPRCalleeSavedArea2Frame(FI);
145 GPRCS2Size += 4;
146 } else {
147 AFI->addGPRCalleeSavedArea1Frame(FI);
148 GPRCS1Size += 4;
149 }
150 break;
151 default:
152 AFI->addDPRCalleeSavedAreaFrame(FI);
153 DPRCSSize += 8;
154 }
155 }
156
157 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
158 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
159 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
160
161 // Set FP to point to the stack slot that contains the previous FP.
162 // For Darwin, FP is R7, which has now been stored in spill area 1.
163 // Otherwise, if this is not Darwin, all the callee-saved registers go
164 // into spill area 1, including the FP in R11. In either case, it is
165 // now safe to emit this assignment.
166 bool HasFP = RegInfo->hasFP(MF);
167 if (HasFP) {
168 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
169 MachineInstrBuilder MIB =
170 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
171 .addFrameIndex(FramePtrSpillFI).addImm(0);
172 AddDefaultCC(AddDefaultPred(MIB));
173 }
174
175 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
176 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
177
178 // Build the new SUBri to adjust SP for FP callee-save spill area.
179 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
180 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
181
182 // Determine starting offsets of spill areas.
183 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
184 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
185 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
186 if (HasFP)
187 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
188 NumBytes);
189 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
190 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
191 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
192
193 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
194 NumBytes = DPRCSOffset;
195 if (NumBytes) {
196 // Adjust SP after all the callee-save spills.
197 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
198 if (HasFP)
199 AFI->setShouldRestoreSPFromFP(true);
200 }
201
202 if (STI.isTargetELF() && RegInfo->hasFP(MF)) {
203 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
204 AFI->getFramePtrSpillOffset());
205 AFI->setShouldRestoreSPFromFP(true);
206 }
207
208 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
209 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
210 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
211
212 // If we need dynamic stack realignment, do it here. Be paranoid and make
213 // sure if we also have VLAs, we have a base pointer for frame access.
214 if (RegInfo->needsStackRealignment(MF)) {
215 unsigned MaxAlign = MFI->getMaxAlignment();
216 assert (!AFI->isThumb1OnlyFunction());
217 if (!AFI->isThumbFunction()) {
218 // Emit bic sp, sp, MaxAlign
219 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
220 TII.get(ARM::BICri), ARM::SP)
221 .addReg(ARM::SP, RegState::Kill)
222 .addImm(MaxAlign-1)));
223 } else {
224 // We cannot use sp as source/dest register here, thus we're emitting the
225 // following sequence:
226 // mov r4, sp
227 // bic r4, r4, MaxAlign
228 // mov sp, r4
229 // FIXME: It will be better just to find spare register here.
230 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
231 .addReg(ARM::SP, RegState::Kill);
232 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
233 TII.get(ARM::t2BICri), ARM::R4)
234 .addReg(ARM::R4, RegState::Kill)
235 .addImm(MaxAlign-1)));
236 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
237 .addReg(ARM::R4, RegState::Kill);
238 }
239
240 AFI->setShouldRestoreSPFromFP(true);
241 }
242
243 // If we need a base pointer, set it up here. It's whatever the value
244 // of the stack pointer is at this point. Any variable size objects
245 // will be allocated after this, so we can still use the base pointer
246 // to reference locals.
247 if (RegInfo->hasBasePointer(MF)) {
248 if (isARM)
249 BuildMI(MBB, MBBI, dl,
250 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
251 .addReg(ARM::SP)
252 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
253 else
254 BuildMI(MBB, MBBI, dl,
255 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
256 .addReg(ARM::SP);
257 }
258
259 // If the frame has variable sized objects then the epilogue must restore
260 // the sp from fp.
261 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
262 AFI->setShouldRestoreSPFromFP(true);
263 }
264
265 void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
266 MachineBasicBlock &MBB) const {
267 MachineBasicBlock::iterator MBBI = prior(MBB.end());
268 assert(MBBI->getDesc().isReturn() &&
269 "Can only insert epilog into returning blocks");
270 unsigned RetOpcode = MBBI->getOpcode();
271 DebugLoc dl = MBBI->getDebugLoc();
272 MachineFrameInfo *MFI = MF.getFrameInfo();
273 ARMFunctionInfo *AFI = MF.getInfo();
274 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
275 const ARMBaseInstrInfo &TII =
276 *static_cast(MF.getTarget().getInstrInfo());
277 assert(!AFI->isThumb1OnlyFunction() &&
278 "This emitEpilogue does not support Thumb1!");
279 bool isARM = !AFI->isThumbFunction();
280
281 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
282 int NumBytes = (int)MFI->getStackSize();
283 unsigned FramePtr = RegInfo->getFrameRegister(MF);
284
285 if (!AFI->hasStackFrame()) {
286 if (NumBytes != 0)
287 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
288 } else {
289 // Unwind MBBI to point to first LDR / VLDRD.
290 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
291 if (MBBI != MBB.begin()) {
292 do
293 --MBBI;
294 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
295 if (!isCSRestore(MBBI, TII, CSRegs))
296 ++MBBI;
297 }
298
299 // Move SP to start of FP callee save spill area.
300 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
301 AFI->getGPRCalleeSavedArea2Size() +
302 AFI->getDPRCalleeSavedAreaSize());
303
304 // Reset SP based on frame pointer only if the stack frame extends beyond
305 // frame pointer stack slot or target is ELF and the function has FP.
306 if (AFI->shouldRestoreSPFromFP()) {
307 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
308 if (NumBytes) {
309 if (isARM)
310 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
311 ARMCC::AL, 0, TII);
312 else
313 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
314 ARMCC::AL, 0, TII);
315 } else {
316 // Thumb2 or ARM.
317 if (isARM)
318 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
319 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
320 else
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
322 .addReg(FramePtr);
323 }
324 } else if (NumBytes)
325 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
326
327 // Move SP to start of integer callee save spill area 2.
328 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
329 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
330
331 // Move SP to start of integer callee save spill area 1.
332 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
333 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
334
335 // Move SP to SP upon entry to the function.
336 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
337 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
338 }
339
340 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
341 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
342 // Tail call return: adjust the stack pointer and jump to callee.
343 MBBI = prior(MBB.end());
344 MachineOperand &JumpTarget = MBBI->getOperand(0);
345
346 // Jump to label or value in register.
347 if (RetOpcode == ARM::TCRETURNdi) {
348 BuildMI(MBB, MBBI, dl,
349 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
350 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
351 JumpTarget.getTargetFlags());
352 } else if (RetOpcode == ARM::TCRETURNdiND) {
353 BuildMI(MBB, MBBI, dl,
354 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
355 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
356 JumpTarget.getTargetFlags());
357 } else if (RetOpcode == ARM::TCRETURNri) {
358 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
359 addReg(JumpTarget.getReg(), RegState::Kill);
360 } else if (RetOpcode == ARM::TCRETURNriND) {
361 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
362 addReg(JumpTarget.getReg(), RegState::Kill);
363 }
364
365 MachineInstr *NewMI = prior(MBBI);
366 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
367 NewMI->addOperand(MBBI->getOperand(i));
368
369 // Delete the pseudo instruction TCRETURN.
370 MBB.erase(MBBI);
371 }
372
373 if (VARegSaveSize)
374 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
375 }
1818 #include "llvm/Target/TargetFrameInfo.h"
1919
2020 namespace llvm {
21 class ARMSubtarget;
2122
2223 class ARMFrameInfo : public TargetFrameInfo {
24 protected:
25 const ARMSubtarget &STI;
26
2327 public:
24 explicit ARMFrameInfo(const ARMSubtarget &ST)
25 : TargetFrameInfo(StackGrowsDown, ST.getStackAlignment(), 0, 4) {
28 explicit ARMFrameInfo(const ARMSubtarget &sti)
29 : TargetFrameInfo(StackGrowsDown, sti.getStackAlignment(), 0, 4), STI(sti) {
2630 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
2736 };
2837
2938 } // End llvm namespace
8888 bool isThumb)
8989 : LLVMTargetMachine(T, TT),
9090 Subtarget(TT, FS, isThumb),
91 FrameInfo(Subtarget),
9291 JITInfo(),
9392 InstrItins(Subtarget.getInstrItineraryData())
9493 {
105104 "v128:64:128-v64:64:64-n32")),
106105 ELFWriterInfo(*this),
107106 TLInfo(*this),
108 TSInfo(*this) {
107 TSInfo(*this),
108 FrameInfo(Subtarget) {
109109 if (!Subtarget.hasARMOps())
110110 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
111111 "support ARM mode execution!");
126126 "v128:64:128-v64:64:64-a:0:32-n32")),
127127 ELFWriterInfo(*this),
128128 TLInfo(*this),
129 TSInfo(*this) {
129 TSInfo(*this),
130 FrameInfo(Subtarget.hasThumb2()
131 ? new ARMFrameInfo(Subtarget)
132 : (ARMFrameInfo*)new Thumb1FrameInfo(Subtarget)) {
130133 }
131134
132135 // Pass Pipeline Configuration
1313 #ifndef ARMTARGETMACHINE_H
1414 #define ARMTARGETMACHINE_H
1515
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/MC/MCStreamer.h"
1916 #include "ARMInstrInfo.h"
2017 #include "ARMELFWriterInfo.h"
2118 #include "ARMFrameInfo.h"
2421 #include "ARMISelLowering.h"
2522 #include "ARMSelectionDAGInfo.h"
2623 #include "Thumb1InstrInfo.h"
24 #include "Thumb1FrameInfo.h"
2725 #include "Thumb2InstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/MC/MCStreamer.h"
2829 #include "llvm/ADT/OwningPtr.h"
2930
3031 namespace llvm {
3233 class ARMBaseTargetMachine : public LLVMTargetMachine {
3334 protected:
3435 ARMSubtarget Subtarget;
35
3636 private:
37 ARMFrameInfo FrameInfo;
3837 ARMJITInfo JITInfo;
3938 InstrItineraryData InstrItins;
4039 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
4342 ARMBaseTargetMachine(const Target &T, const std::string &TT,
4443 const std::string &FS, bool isThumb);
4544
46 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
4745 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
4846 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
4947 virtual const InstrItineraryData *getInstrItineraryData() const {
6866 ARMELFWriterInfo ELFWriterInfo;
6967 ARMTargetLowering TLInfo;
7068 ARMSelectionDAGInfo TSInfo;
71 public:
69 ARMFrameInfo FrameInfo;
70 public:
7271 ARMTargetMachine(const Target &T, const std::string &TT,
7372 const std::string &FS);
7473
8382 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
8483 return &TSInfo;
8584 }
85 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
8686
8787 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
8888 virtual const TargetData *getTargetData() const { return &DataLayout; }
102102 ARMELFWriterInfo ELFWriterInfo;
103103 ARMTargetLowering TLInfo;
104104 ARMSelectionDAGInfo TSInfo;
105 // Either Thumb1FrameInfo or ARMFrameInfo.
106 OwningPtr FrameInfo;
105107 public:
106108 ThumbTargetMachine(const Target &T, const std::string &TT,
107109 const std::string &FS);
123125 virtual const ARMBaseInstrInfo *getInstrInfo() const {
124126 return InstrInfo.get();
125127 }
128 /// returns either Thumb1FrameInfo or ARMFrameInfo
129 virtual const ARMFrameInfo *getFrameInfo() const {
130 return FrameInfo.get();
131 }
126132 virtual const TargetData *getTargetData() const { return &DataLayout; }
127133 virtual const ARMELFWriterInfo *getELFWriterInfo() const {
128134 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
0 //=======- Thumb1FrameInfo.cpp - Thumb1 Frame Information ------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Thumb1FrameInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19
20 using namespace llvm;
21
22 static void emitSPUpdate(MachineBasicBlock &MBB,
23 MachineBasicBlock::iterator &MBBI,
24 const TargetInstrInfo &TII, DebugLoc dl,
25 const Thumb1RegisterInfo &MRI,
26 int NumBytes) {
27 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
28 MRI, dl);
29 }
30
31 void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const {
32 MachineBasicBlock &MBB = MF.front();
33 MachineBasicBlock::iterator MBBI = MBB.begin();
34 MachineFrameInfo *MFI = MF.getFrameInfo();
35 ARMFunctionInfo *AFI = MF.getInfo();
36 const Thumb1RegisterInfo *RegInfo =
37 static_cast(MF.getTarget().getRegisterInfo());
38 const Thumb1InstrInfo &TII =
39 *static_cast(MF.getTarget().getInstrInfo());
40
41 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
42 unsigned NumBytes = MFI->getStackSize();
43 const std::vector &CSI = MFI->getCalleeSavedInfo();
44 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
45 unsigned FramePtr = RegInfo->getFrameRegister(MF);
46 unsigned BasePtr = RegInfo->getBaseRegister();
47
48 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
49 NumBytes = (NumBytes + 3) & ~3;
50 MFI->setStackSize(NumBytes);
51
52 // Determine the sizes of each callee-save spill areas and record which frame
53 // belongs to which callee-save spill areas.
54 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
55 int FramePtrSpillFI = 0;
56
57 if (VARegSaveSize)
58 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize);
59
60 if (!AFI->hasStackFrame()) {
61 if (NumBytes != 0)
62 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
63 return;
64 }
65
66 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
67 unsigned Reg = CSI[i].getReg();
68 int FI = CSI[i].getFrameIdx();
69 switch (Reg) {
70 case ARM::R4:
71 case ARM::R5:
72 case ARM::R6:
73 case ARM::R7:
74 case ARM::LR:
75 if (Reg == FramePtr)
76 FramePtrSpillFI = FI;
77 AFI->addGPRCalleeSavedArea1Frame(FI);
78 GPRCS1Size += 4;
79 break;
80 case ARM::R8:
81 case ARM::R9:
82 case ARM::R10:
83 case ARM::R11:
84 if (Reg == FramePtr)
85 FramePtrSpillFI = FI;
86 if (STI.isTargetDarwin()) {
87 AFI->addGPRCalleeSavedArea2Frame(FI);
88 GPRCS2Size += 4;
89 } else {
90 AFI->addGPRCalleeSavedArea1Frame(FI);
91 GPRCS1Size += 4;
92 }
93 break;
94 default:
95 AFI->addDPRCalleeSavedAreaFrame(FI);
96 DPRCSSize += 8;
97 }
98 }
99
100 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
101 ++MBBI;
102 if (MBBI != MBB.end())
103 dl = MBBI->getDebugLoc();
104 }
105
106 // Adjust FP so it point to the stack slot that contains the previous FP.
107 if (RegInfo->hasFP(MF)) {
108 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
109 .addFrameIndex(FramePtrSpillFI).addImm(0);
110 AFI->setShouldRestoreSPFromFP(true);
111 }
112
113 // Determine starting offsets of spill areas.
114 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
115 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
116 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
117 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
118 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
119 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
120 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
121
122 NumBytes = DPRCSOffset;
123 if (NumBytes) {
124 // Insert it after all the callee-save spills.
125 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
126 }
127
128 if (STI.isTargetELF() && RegInfo->hasFP(MF))
129 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
130 AFI->getFramePtrSpillOffset());
131
132 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
133 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
134 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
135
136 // If we need a base pointer, set it up here. It's whatever the value
137 // of the stack pointer is at this point. Any variable size objects
138 // will be allocated after this, so we can still use the base pointer
139 // to reference locals.
140 if (RegInfo->hasBasePointer(MF))
141 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP);
142 }
143
144 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
145 for (unsigned i = 0; CSRegs[i]; ++i)
146 if (Reg == CSRegs[i])
147 return true;
148 return false;
149 }
150
151 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
152 if (MI->getOpcode() == ARM::tRestore &&
153 MI->getOperand(1).isFI() &&
154 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
155 return true;
156 else if (MI->getOpcode() == ARM::tPOP) {
157 // The first two operands are predicates. The last two are
158 // imp-def and imp-use of SP. Check everything in between.
159 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
160 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
161 return false;
162 return true;
163 }
164 return false;
165 }
166
167 void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF,
168 MachineBasicBlock &MBB) const {
169 MachineBasicBlock::iterator MBBI = prior(MBB.end());
170 assert((MBBI->getOpcode() == ARM::tBX_RET ||
171 MBBI->getOpcode() == ARM::tPOP_RET) &&
172 "Can only insert epilog into returning blocks");
173 DebugLoc dl = MBBI->getDebugLoc();
174 MachineFrameInfo *MFI = MF.getFrameInfo();
175 ARMFunctionInfo *AFI = MF.getInfo();
176 const Thumb1RegisterInfo *RegInfo =
177 static_cast(MF.getTarget().getRegisterInfo());
178 const Thumb1InstrInfo &TII =
179 *static_cast(MF.getTarget().getInstrInfo());
180
181 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
182 int NumBytes = (int)MFI->getStackSize();
183 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
184 unsigned FramePtr = RegInfo->getFrameRegister(MF);
185
186 if (!AFI->hasStackFrame()) {
187 if (NumBytes != 0)
188 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
189 } else {
190 // Unwind MBBI to point to first LDR / VLDRD.
191 if (MBBI != MBB.begin()) {
192 do
193 --MBBI;
194 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
195 if (!isCSRestore(MBBI, CSRegs))
196 ++MBBI;
197 }
198
199 // Move SP to start of FP callee save spill area.
200 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
201 AFI->getGPRCalleeSavedArea2Size() +
202 AFI->getDPRCalleeSavedAreaSize());
203
204 if (AFI->shouldRestoreSPFromFP()) {
205 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
206 // Reset SP based on frame pointer only if the stack frame extends beyond
207 // frame pointer stack slot or target is ELF and the function has FP.
208 if (NumBytes)
209 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
210 TII, *RegInfo, dl);
211 else
212 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
213 .addReg(FramePtr);
214 } else {
215 if (MBBI->getOpcode() == ARM::tBX_RET &&
216 &MBB.front() != MBBI &&
217 prior(MBBI)->getOpcode() == ARM::tPOP) {
218 MachineBasicBlock::iterator PMBBI = prior(MBBI);
219 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
220 } else
221 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
222 }
223 }
224
225 if (VARegSaveSize) {
226 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
227 // to LR, and we can't pop the value directly to the PC since
228 // we need to update the SP after popping the value. Therefore, we
229 // pop the old LR into R3 as a temporary.
230
231 // Move back past the callee-saved register restoration
232 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
233 ++MBBI;
234 // Epilogue for vararg functions: pop LR to R3 and branch off it.
235 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
236 .addReg(ARM::R3, RegState::Define);
237
238 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
239
240 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
241 .addReg(ARM::R3, RegState::Kill);
242 // erase the old tBX_RET instruction
243 MBB.erase(MBBI);
244 }
245 }
0 //===-- Thumb1FrameInfo.h - Thumb1-specific frame info stuff ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef __THUMB_FRAMEINFO_H_
14 #define __THUMM_FRAMEINFO_H_
15
16 #include "ARM.h"
17 #include "ARMFrameInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb1InstrInfo.h"
20 #include "Thumb1RegisterInfo.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22
23 namespace llvm {
24 class ARMSubtarget;
25
26 class Thumb1FrameInfo : public ARMFrameInfo {
27 public:
28 explicit Thumb1FrameInfo(const ARMSubtarget &sti)
29 : ARMFrameInfo(sti) {
30 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36 };
37
38 } // End llvm namespace
39
40 #endif
690690 AddDefaultPred(MIB);
691691 }
692692 }
693
694 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
695 MachineBasicBlock &MBB = MF.front();
696 MachineBasicBlock::iterator MBBI = MBB.begin();
697 MachineFrameInfo *MFI = MF.getFrameInfo();
698 ARMFunctionInfo *AFI = MF.getInfo();
699 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
700 unsigned NumBytes = MFI->getStackSize();
701 const std::vector &CSI = MFI->getCalleeSavedInfo();
702 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
703
704 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
705 NumBytes = (NumBytes + 3) & ~3;
706 MFI->setStackSize(NumBytes);
707
708 // Determine the sizes of each callee-save spill areas and record which frame
709 // belongs to which callee-save spill areas.
710 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
711 int FramePtrSpillFI = 0;
712
713 if (VARegSaveSize)
714 emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
715
716 if (!AFI->hasStackFrame()) {
717 if (NumBytes != 0)
718 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
719 return;
720 }
721
722 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
723 unsigned Reg = CSI[i].getReg();
724 int FI = CSI[i].getFrameIdx();
725 switch (Reg) {
726 case ARM::R4:
727 case ARM::R5:
728 case ARM::R6:
729 case ARM::R7:
730 case ARM::LR:
731 if (Reg == FramePtr)
732 FramePtrSpillFI = FI;
733 AFI->addGPRCalleeSavedArea1Frame(FI);
734 GPRCS1Size += 4;
735 break;
736 case ARM::R8:
737 case ARM::R9:
738 case ARM::R10:
739 case ARM::R11:
740 if (Reg == FramePtr)
741 FramePtrSpillFI = FI;
742 if (STI.isTargetDarwin()) {
743 AFI->addGPRCalleeSavedArea2Frame(FI);
744 GPRCS2Size += 4;
745 } else {
746 AFI->addGPRCalleeSavedArea1Frame(FI);
747 GPRCS1Size += 4;
748 }
749 break;
750 default:
751 AFI->addDPRCalleeSavedAreaFrame(FI);
752 DPRCSSize += 8;
753 }
754 }
755
756 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
757 ++MBBI;
758 if (MBBI != MBB.end())
759 dl = MBBI->getDebugLoc();
760 }
761
762 // Adjust FP so it point to the stack slot that contains the previous FP.
763 if (hasFP(MF)) {
764 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
765 .addFrameIndex(FramePtrSpillFI).addImm(0);
766 AFI->setShouldRestoreSPFromFP(true);
767 }
768
769 // Determine starting offsets of spill areas.
770 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
771 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
772 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
773 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
774 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
775 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
776 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
777
778 NumBytes = DPRCSOffset;
779 if (NumBytes) {
780 // Insert it after all the callee-save spills.
781 emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
782 }
783
784 if (STI.isTargetELF() && hasFP(MF))
785 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
786 AFI->getFramePtrSpillOffset());
787
788 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
789 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
790 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
791
792 // If we need a base pointer, set it up here. It's whatever the value
793 // of the stack pointer is at this point. Any variable size objects
794 // will be allocated after this, so we can still use the base pointer
795 // to reference locals.
796 if (hasBasePointer(MF))
797 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP);
798 }
799
800 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
801 for (unsigned i = 0; CSRegs[i]; ++i)
802 if (Reg == CSRegs[i])
803 return true;
804 return false;
805 }
806
807 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
808 if (MI->getOpcode() == ARM::tRestore &&
809 MI->getOperand(1).isFI() &&
810 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
811 return true;
812 else if (MI->getOpcode() == ARM::tPOP) {
813 // The first two operands are predicates. The last two are
814 // imp-def and imp-use of SP. Check everything in between.
815 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
816 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
817 return false;
818 return true;
819 }
820 return false;
821 }
822
823 void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
824 MachineBasicBlock &MBB) const {
825 MachineBasicBlock::iterator MBBI = prior(MBB.end());
826 assert((MBBI->getOpcode() == ARM::tBX_RET ||
827 MBBI->getOpcode() == ARM::tPOP_RET) &&
828 "Can only insert epilog into returning blocks");
829 DebugLoc dl = MBBI->getDebugLoc();
830 MachineFrameInfo *MFI = MF.getFrameInfo();
831 ARMFunctionInfo *AFI = MF.getInfo();
832 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
833 int NumBytes = (int)MFI->getStackSize();
834 const unsigned *CSRegs = getCalleeSavedRegs();
835
836 if (!AFI->hasStackFrame()) {
837 if (NumBytes != 0)
838 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
839 } else {
840 // Unwind MBBI to point to first LDR / VLDRD.
841 if (MBBI != MBB.begin()) {
842 do
843 --MBBI;
844 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
845 if (!isCSRestore(MBBI, CSRegs))
846 ++MBBI;
847 }
848
849 // Move SP to start of FP callee save spill area.
850 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
851 AFI->getGPRCalleeSavedArea2Size() +
852 AFI->getDPRCalleeSavedAreaSize());
853
854 if (AFI->shouldRestoreSPFromFP()) {
855 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
856 // Reset SP based on frame pointer only if the stack frame extends beyond
857 // frame pointer stack slot or target is ELF and the function has FP.
858 if (NumBytes)
859 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
860 TII, *this, dl);
861 else
862 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
863 .addReg(FramePtr);
864 } else {
865 if (MBBI->getOpcode() == ARM::tBX_RET &&
866 &MBB.front() != MBBI &&
867 prior(MBBI)->getOpcode() == ARM::tPOP) {
868 MachineBasicBlock::iterator PMBBI = prior(MBBI);
869 emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
870 } else
871 emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
872 }
873 }
874
875 if (VARegSaveSize) {
876 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore
877 // to LR, and we can't pop the value directly to the PC since
878 // we need to update the SP after popping the value. Therefore, we
879 // pop the old LR into R3 as a temporary.
880
881 // Move back past the callee-saved register restoration
882 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs))
883 ++MBBI;
884 // Epilogue for vararg functions: pop LR to R3 and branch off it.
885 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
886 .addReg(ARM::R3, RegState::Define);
887
888 emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
889
890 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
891 .addReg(ARM::R3, RegState::Kill);
892 // erase the old tBX_RET instruction
893 MBB.erase(MBBI);
894 }
895 }
5858 unsigned Reg) const;
5959 void eliminateFrameIndex(MachineBasicBlock::iterator II,
6060 int SPAdj, RegScavenger *RS = NULL) const;
61
62 void emitPrologue(MachineFunction &MF) const;
63 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
6461 };
6562 }
6663
1717 #include "llvm/Target/TargetMachine.h"
1818
1919 namespace llvm {
20 namespace Alpha {
21 // These describe LDAx
22
23 static const int IMM_LOW = -32768;
24 static const int IMM_HIGH = 32767;
25 static const int IMM_MULT = 65536;
26 }
2027
2128 class AlphaTargetMachine;
2229 class FunctionPass;
0 //=====- AlphaFrameInfo.cpp - Alpha Frame Information ----------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Alpha implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AlphaFrameInfo.h"
14 #include "AlphaInstrInfo.h"
15 #include "AlphaMachineFunctionInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/Twine.h"
21
22 using namespace llvm;
23
24 static long getUpper16(long l) {
25 long y = l / Alpha::IMM_MULT;
26 if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
27 ++y;
28 return y;
29 }
30
31 static long getLower16(long l) {
32 long h = getUpper16(l);
33 return l - h * Alpha::IMM_MULT;
34 }
35
36 void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const {
37 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
38 MachineBasicBlock::iterator MBBI = MBB.begin();
39 MachineFrameInfo *MFI = MF.getFrameInfo();
40 const AlphaRegisterInfo *RegInfo =
41 static_cast(MF.getTarget().getRegisterInfo());
42 const AlphaInstrInfo &TII =
43 *static_cast(MF.getTarget().getInstrInfo());
44
45 DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
46 bool FP = RegInfo->hasFP(MF);
47
48 // Handle GOP offset
49 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
50 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist);
51 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
52 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist);
53
54 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
55 .addGlobalAddress(MF.getFunction());
56
57 // Get the number of bytes to allocate from the FrameInfo
58 long NumBytes = MFI->getStackSize();
59
60 if (FP)
61 NumBytes += 8; //reserve space for the old FP
62
63 // Do we need to allocate space on the stack?
64 if (NumBytes == 0) return;
65
66 unsigned Align = getStackAlignment();
67 NumBytes = (NumBytes+Align-1)/Align*Align;
68
69 // Update frame info to pretend that this is part of the stack...
70 MFI->setStackSize(NumBytes);
71
72 // adjust stack pointer: r30 -= numbytes
73 NumBytes = -NumBytes;
74 if (NumBytes >= Alpha::IMM_LOW) {
75 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
76 .addReg(Alpha::R30);
77 } else if (getUpper16(NumBytes) >= Alpha::IMM_LOW) {
78 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
79 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
80 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
81 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
82 } else {
83 report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
84 }
85
86 // Now if we need to, save the old FP and set the new
87 if (FP) {
88 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
89 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
90 // This must be the last instr in the prolog
91 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
92 .addReg(Alpha::R30).addReg(Alpha::R30);
93 }
94
95 }
96
97 void AlphaFrameInfo::emitEpilogue(MachineFunction &MF,
98 MachineBasicBlock &MBB) const {
99 const MachineFrameInfo *MFI = MF.getFrameInfo();
100 MachineBasicBlock::iterator MBBI = prior(MBB.end());
101 const AlphaRegisterInfo *RegInfo =
102 static_cast(MF.getTarget().getRegisterInfo());
103 const AlphaInstrInfo &TII =
104 *static_cast(MF.getTarget().getInstrInfo());
105
106 assert((MBBI->getOpcode() == Alpha::RETDAG ||
107 MBBI->getOpcode() == Alpha::RETDAGp)
108 && "Can only insert epilog into returning blocks");
109 DebugLoc dl = MBBI->getDebugLoc();
110
111 bool FP = RegInfo->hasFP(MF);
112
113 // Get the number of bytes allocated from the FrameInfo...
114 long NumBytes = MFI->getStackSize();
115
116 //now if we need to, restore the old FP
117 if (FP) {
118 //copy the FP into the SP (discards allocas)
119 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
120 .addReg(Alpha::R15);
121 //restore the FP
122 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15)
123 .addImm(0).addReg(Alpha::R15);
124 }
125
126 if (NumBytes != 0) {
127 if (NumBytes <= Alpha::IMM_HIGH) {
128 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
129 .addReg(Alpha::R30);
130 } else if (getUpper16(NumBytes) <= Alpha::IMM_HIGH) {
131 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
132 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
133 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
134 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
135 } else {
136 report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
137 }
138 }
139 }
0 //===--- AlphaFrameInfo.h - Define TargetFrameInfo for Alpha --*- C++ -*---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHA_FRAMEINFO_H
14 #define ALPHA_FRAMEINFO_H
15
16 #include "Alpha.h"
17 #include "AlphaSubtarget.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19
20 namespace llvm {
21 class AlphaSubtarget;
22
23 class AlphaFrameInfo : public TargetFrameInfo {
24 const AlphaSubtarget &STI;
25 // FIXME: This should end in MachineFunctionInfo, not here!
26 mutable int curgpdist;
27 public:
28 explicit AlphaFrameInfo(const AlphaSubtarget &sti)
29 : TargetFrameInfo(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) {
30 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36 };
37
38 } // End llvm namespace
39
40 #endif
3434 #include
3535 using namespace llvm;
3636
37 //These describe LDAx
38 static const int IMM_LOW = -32768;
39 static const int IMM_HIGH = 32767;
40 static const int IMM_MULT = 65536;
41
42 static long getUpper16(long l)
43 {
44 long y = l / IMM_MULT;
45 if (l % IMM_MULT > IMM_HIGH)
37 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
38 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
39 TII(tii) {
40 }
41
42 static long getUpper16(long l) {
43 long y = l / Alpha::IMM_MULT;
44 if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
4645 ++y;
4746 return y;
4847 }
4948
50 static long getLower16(long l)
51 {
49 static long getLower16(long l) {
5250 long h = getUpper16(l);
53 return l - h * IMM_MULT;
54 }
55
56 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
57 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
58 TII(tii), curgpdist(0)
59 {
51 return l - h * Alpha::IMM_MULT;
6052 }
6153
6254 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
167159 DEBUG(errs() << "Corrected Offset " << Offset
168160 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
169161
170 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
162 if (Offset > Alpha::IMM_HIGH || Offset < Alpha::IMM_LOW) {
171163 DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
172164 << Offset << "\n");
173165 //so in this case, we need to use a temporary register, and move the
185177 }
186178 }
187179
188
189 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
190 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
191 MachineBasicBlock::iterator MBBI = MBB.begin();
192 MachineFrameInfo *MFI = MF.getFrameInfo();
193 DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
194 bool FP = hasFP(MF);
195
196 //handle GOP offset
197 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
198 .addGlobalAddress(MF.getFunction())
199 .addReg(Alpha::R27).addImm(++curgpdist);
200 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
201 .addGlobalAddress(MF.getFunction())
202 .addReg(Alpha::R29).addImm(curgpdist);
203
204 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
205 .addGlobalAddress(MF.getFunction());
206
207 // Get the number of bytes to allocate from the FrameInfo
208 long NumBytes = MFI->getStackSize();
209
210 if (FP)
211 NumBytes += 8; //reserve space for the old FP
212
213 // Do we need to allocate space on the stack?
214 if (NumBytes == 0) return;
215
216 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
217 NumBytes = (NumBytes+Align-1)/Align*Align;
218
219 // Update frame info to pretend that this is part of the stack...
220 MFI->setStackSize(NumBytes);
221
222 // adjust stack pointer: r30 -= numbytes
223 NumBytes = -NumBytes;
224 if (NumBytes >= IMM_LOW) {
225 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
226 .addReg(Alpha::R30);
227 } else if (getUpper16(NumBytes) >= IMM_LOW) {
228 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
229 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
230 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
231 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
232 } else {
233 report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
234 }
235
236 //now if we need to, save the old FP and set the new
237 if (FP)
238 {
239 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
240 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
241 //this must be the last instr in the prolog
242 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
243 .addReg(Alpha::R30).addReg(Alpha::R30);
244 }
245
246 }
247
248 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
249 MachineBasicBlock &MBB) const {
250 const MachineFrameInfo *MFI = MF.getFrameInfo();
251 MachineBasicBlock::iterator MBBI = prior(MBB.end());
252 assert((MBBI->getOpcode() == Alpha::RETDAG ||
253 MBBI->getOpcode() == Alpha::RETDAGp)
254 && "Can only insert epilog into returning blocks");
255 DebugLoc dl = MBBI->getDebugLoc();
256
257 bool FP = hasFP(MF);
258
259 // Get the number of bytes allocated from the FrameInfo...
260 long NumBytes = MFI->getStackSize();
261
262 //now if we need to, restore the old FP
263 if (FP) {
264 //copy the FP into the SP (discards allocas)
265 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
266 .addReg(Alpha::R15);
267 //restore the FP
268 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15)
269 .addImm(0).addReg(Alpha::R15);
270 }
271
272 if (NumBytes != 0) {
273 if (NumBytes <= IMM_HIGH) {
274 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
275 .addReg(Alpha::R30);
276 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
277 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
278 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
279 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
280 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
281 } else {
282 report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
283 }
284 }
285 }
286
287180 unsigned AlphaRegisterInfo::getRARegister() const {
288181 return Alpha::R26;
289182 }
4040 void eliminateFrameIndex(MachineBasicBlock::iterator II,
4141 int SPAdj, RegScavenger *RS = NULL) const;
4242
43 //void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
44
45 void emitPrologue(MachineFunction &MF) const;
46 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
47
4843 // Debug information queries.
4944 unsigned getRARegister() const;
5045 unsigned getFrameRegister(const MachineFunction &MF) const;
5651 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
5752
5853 static std::string getPrettyName(unsigned reg);
59
60 private:
61 mutable int curgpdist;
6254 };
6355
6456 } // end namespace llvm
2727 const std::string &FS)
2828 : LLVMTargetMachine(T, TT),
2929 DataLayout("e-f128:128:128-n64"),
30 FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
30 FrameInfo(Subtarget),
3131 Subtarget(TT, FS),
3232 TLInfo(*this),
3333 TSInfo(*this) {
1313 #ifndef ALPHA_TARGETMACHINE_H
1414 #define ALPHA_TARGETMACHINE_H
1515
16 #include "AlphaInstrInfo.h"
17 #include "AlphaISelLowering.h"
18 #include "AlphaFrameInfo.h"
19 #include "AlphaSelectionDAGInfo.h"
20 #include "AlphaSubtarget.h"
1621 #include "llvm/Target/TargetMachine.h"
1722 #include "llvm/Target/TargetData.h"
1823 #include "llvm/Target/TargetFrameInfo.h"
19 #include "AlphaInstrInfo.h"
20 #include "AlphaISelLowering.h"
21 #include "AlphaSelectionDAGInfo.h"
22 #include "AlphaSubtarget.h"
2324
2425 namespace llvm {
2526
2829 class AlphaTargetMachine : public LLVMTargetMachine {
2930 const TargetData DataLayout; // Calculates type size & alignment
3031 AlphaInstrInfo InstrInfo;
31 TargetFrameInfo FrameInfo;
32 AlphaFrameInfo FrameInfo;
3233 AlphaSubtarget Subtarget;
3334 AlphaTargetLowering TLInfo;
3435 AlphaSelectionDAGInfo TSInfo;
0 //====- BlackfinFrameInfo.cpp - Blackfin Frame Information ------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Blackfin implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "BlackfinFrameInfo.h"
14 #include "BlackfinInstrInfo.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18
19 using namespace llvm;
20
21
22 // Emit a prologue that sets up a stack frame.
23 // On function entry, R0-R2 and P0 may hold arguments.
24 // R3, P1, and P2 may be used as scratch registers
25 void BlackfinFrameInfo::emitPrologue(MachineFunction &MF) const {
26 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
27 MachineBasicBlock::iterator MBBI = MBB.begin();
28 MachineFrameInfo *MFI = MF.getFrameInfo();
29 const BlackfinRegisterInfo *RegInfo =
30 static_cast(MF.getTarget().getRegisterInfo());
31 const BlackfinInstrInfo &TII =
32 *static_cast(MF.getTarget().getInstrInfo());
33
34 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
35
36 int FrameSize = MFI->getStackSize();
37 if (FrameSize%4) {
38 FrameSize = (FrameSize+3) & ~3;
39 MFI->setStackSize(FrameSize);
40 }
41
42 if (!RegInfo->hasFP(MF)) {
43 assert(!MFI->adjustsStack() &&
44 "FP elimination on a non-leaf function is not supported");
45 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
46 return;
47 }
48
49 // emit a LINK instruction
50 if (FrameSize <= 0x3ffff) {
51 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
52 return;
53 }
54
55 // Frame is too big, do a manual LINK:
56 // [--SP] = RETS;
57 // [--SP] = FP;
58 // FP = SP;
59 // P1 = -FrameSize;
60 // SP = SP + P1;
61 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
62 .addReg(BF::RETS, RegState::Kill);
63 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
64 .addReg(BF::FP, RegState::Kill);
65 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
66 .addReg(BF::SP);
67 RegInfo->loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
68 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
69 .addReg(BF::SP, RegState::Kill)
70 .addReg(BF::P1, RegState::Kill);
71
72 }
73
74 void BlackfinFrameInfo::emitEpilogue(MachineFunction &MF,
75 MachineBasicBlock &MBB) const {
76 MachineFrameInfo *MFI = MF.getFrameInfo();
77 const BlackfinRegisterInfo *RegInfo =
78 static_cast(MF.getTarget().getRegisterInfo());
79 const BlackfinInstrInfo &TII =
80 *static_cast(MF.getTarget().getInstrInfo());
81 MachineBasicBlock::iterator MBBI = prior(MBB.end());
82 DebugLoc dl = MBBI->getDebugLoc();
83
84 int FrameSize = MFI->getStackSize();
85 assert(FrameSize%4 == 0 && "Misaligned frame size");
86
87 if (!RegInfo->hasFP(MF)) {
88 assert(!MFI->adjustsStack() &&
89 "FP elimination on a non-leaf function is not supported");
90 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
91 return;
92 }
93
94 // emit an UNLINK instruction
95 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
96 }
0 //=- BlackfinFrameInfo.h - Define TargetFrameInfo for Blackfin --*- C++ -*--==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHA_FRAMEINFO_H
14 #define ALPHA_FRAMEINFO_H
15
16 #include "Blackfin.h"
17 #include "BlackfinSubtarget.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19
20 namespace llvm {
21 class BlackfinSubtarget;
22
23 class BlackfinFrameInfo : public TargetFrameInfo {
24 protected:
25 const BlackfinSubtarget &STI;
26
27 public:
28 explicit BlackfinFrameInfo(const BlackfinSubtarget &sti)
29 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), STI(sti) {
30 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36 };
37
38 } // End llvm namespace
39
40 #endif
341341 }
342342 }
343343
344 // Emit a prologue that sets up a stack frame.
345 // On function entry, R0-R2 and P0 may hold arguments.
346 // R3, P1, and P2 may be used as scratch registers
347 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
348 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
349 MachineBasicBlock::iterator MBBI = MBB.begin();
350 MachineFrameInfo *MFI = MF.getFrameInfo();
351 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
352
353 int FrameSize = MFI->getStackSize();
354 if (FrameSize%4) {
355 FrameSize = (FrameSize+3) & ~3;
356 MFI->setStackSize(FrameSize);
357 }
358
359 if (!hasFP(MF)) {
360 assert(!MFI->adjustsStack() &&
361 "FP elimination on a non-leaf function is not supported");
362 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
363 return;
364 }
365
366 // emit a LINK instruction
367 if (FrameSize <= 0x3ffff) {
368 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
369 return;
370 }
371
372 // Frame is too big, do a manual LINK:
373 // [--SP] = RETS;
374 // [--SP] = FP;
375 // FP = SP;
376 // P1 = -FrameSize;
377 // SP = SP + P1;
378 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
379 .addReg(BF::RETS, RegState::Kill);
380 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
381 .addReg(BF::FP, RegState::Kill);
382 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
383 .addReg(BF::SP);
384 loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
385 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
386 .addReg(BF::SP, RegState::Kill)
387 .addReg(BF::P1, RegState::Kill);
388
389 }
390
391 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
392 MachineBasicBlock &MBB) const {
393 MachineFrameInfo *MFI = MF.getFrameInfo();
394 MachineBasicBlock::iterator MBBI = prior(MBB.end());
395 DebugLoc dl = MBBI->getDebugLoc();
396
397 int FrameSize = MFI->getStackSize();
398 assert(FrameSize%4 == 0 && "Misaligned frame size");
399
400 if (!hasFP(MF)) {
401 assert(!MFI->adjustsStack() &&
402 "FP elimination on a non-leaf function is not supported");
403 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
404 return;
405 }
406
407 // emit an UNLINK instruction
408 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
409 }
410
411344 unsigned BlackfinRegisterInfo::getRARegister() const {
412345 return BF::RETS;
413346 }
5656 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
5757 RegScavenger *RS) const;
5858
59 void emitPrologue(MachineFunction &MF) const;
60 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
61
6259 unsigned getFrameRegister(const MachineFunction &MF) const;
6360 unsigned getRARegister() const;
6461
3232 TLInfo(*this),
3333 TSInfo(*this),
3434 InstrInfo(Subtarget),
35 FrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0) {
35 FrameInfo(Subtarget) {
3636 }
3737
3838 bool BlackfinTargetMachine::addInstSelector(PassManagerBase &PM,
1313 #ifndef BLACKFINTARGETMACHINE_H
1414 #define BLACKFINTARGETMACHINE_H
1515
16 #include "BlackfinInstrInfo.h"
17 #include "BlackfinIntrinsicInfo.h"
18 #include "BlackfinISelLowering.h"
19 #include "BlackfinFrameInfo.h"
20 #include "BlackfinSubtarget.h"
21 #include "BlackfinSelectionDAGInfo.h"
1622 #include "llvm/Target/TargetMachine.h"
1723 #include "llvm/Target/TargetData.h"
1824 #include "llvm/Target/TargetFrameInfo.h"
19 #include "BlackfinInstrInfo.h"
20 #include "BlackfinSubtarget.h"
21 #include "BlackfinISelLowering.h"
22 #include "BlackfinSelectionDAGInfo.h"
23 #include "BlackfinIntrinsicInfo.h"
2425
2526 namespace llvm {
2627
3031 BlackfinTargetLowering TLInfo;
3132 BlackfinSelectionDAGInfo TSInfo;
3233 BlackfinInstrInfo InstrInfo;
33 TargetFrameInfo FrameInfo;
34 BlackfinFrameInfo FrameInfo;
3435 BlackfinIntrinsicInfo IntrinsicInfo;
3536 public:
3637 BlackfinTargetMachine(const Target &T, const std::string &TT,
1313 #include "SPU.h"
1414 #include "SPUFrameInfo.h"
1515 #include "SPURegisterNames.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUInstrInfo.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Support/CommandLine.h"
1627 using namespace llvm;
1728
1829 //===----------------------------------------------------------------------===//
1930 // SPUFrameInfo:
2031 //===----------------------------------------------------------------------===//
2132
22 SPUFrameInfo::SPUFrameInfo(const TargetMachine &tm):
23 TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
24 TM(tm)
25 {
33 SPUFrameInfo::SPUFrameInfo(const SPUSubtarget &sti)
34 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
35 Subtarget(sti) {
2636 LR[0].first = SPU::R0;
2737 LR[0].second = 16;
2838 }
39
40
41 /// determineFrameLayout - Determine the size of the frame and maximum call
42 /// frame size.
43 void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const {
44 MachineFrameInfo *MFI = MF.getFrameInfo();
45
46 // Get the number of bytes to allocate from the FrameInfo
47 unsigned FrameSize = MFI->getStackSize();
48
49 // Get the alignments provided by the target, and the maximum alignment
50 // (if any) of the fixed frame objects.
51 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
52 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
53 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
54 unsigned AlignMask = Align - 1;
55
56 // Get the maximum call frame size of all the calls.
57 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
58
59 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
60 // that allocations will be aligned.
61 if (MFI->hasVarSizedObjects())
62 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
63
64 // Update maximum call frame size.
65 MFI->setMaxCallFrameSize(maxCallFrameSize);
66
67 // Include call frame size in total.
68 FrameSize += maxCallFrameSize;
69
70 // Make sure the frame is aligned.
71 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
72
73 // Update frame info.
74 MFI->setStackSize(FrameSize);
75 }
76
77 void SPUFrameInfo::emitPrologue(MachineFunction &MF) const {
78 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
79 MachineBasicBlock::iterator MBBI = MBB.begin();
80 MachineFrameInfo *MFI = MF.getFrameInfo();
81 const SPUInstrInfo &TII =
82 *static_cast(MF.getTarget().getInstrInfo());
83 MachineModuleInfo &MMI = MF.getMMI();
84 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
85
86 // Prepare for debug frame info.
87 bool hasDebugInfo = MMI.hasDebugInfo();
88 MCSymbol *FrameLabel = 0;
89
90 // Move MBBI back to the beginning of the function.
91 MBBI = MBB.begin();
92
93 // Work out frame sizes.
94 determineFrameLayout(MF);
95 int FrameSize = MFI->getStackSize();
96
97 assert((FrameSize & 0xf) == 0
98 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
99
100 // the "empty" frame size is 16 - just the register scavenger spill slot
101 if (FrameSize > 16 || MFI->adjustsStack()) {
102 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
103 if (hasDebugInfo) {
104 // Mark effective beginning of when frame pointer becomes valid.
105 FrameLabel = MMI.getContext().CreateTempSymbol();
106 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
107 }
108
109 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
110 // for the ABI
111 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
112 .addReg(SPU::R1);
113 if (isInt<10>(FrameSize)) {
114 // Spill $sp to adjusted $sp
115 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
116 .addReg(SPU::R1);
117 // Adjust $sp by required amout
118 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
119 .addImm(FrameSize);
120 } else if (isInt<16>(FrameSize)) {
121 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
122 // $r2 to adjust $sp:
123 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
124 .addImm(-16)
125 .addReg(SPU::R1);
126 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
127 .addImm(FrameSize);
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
129 .addReg(SPU::R2)
130 .addReg(SPU::R1);
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
132 .addReg(SPU::R1)
133 .addReg(SPU::R2);
134 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
135 .addReg(SPU::R2)
136 .addImm(16);
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
138 .addReg(SPU::R2)
139 .addReg(SPU::R1);
140 } else {
141 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
142 }
143
144 if (hasDebugInfo) {
145 std::vector &Moves = MMI.getFrameMoves();
146
147 // Show update of SP.
148 MachineLocation SPDst(MachineLocation::VirtualFP);
149 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
150 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
151
152 // Add callee saved registers to move list.
153 const std::vector &CSI = MFI->getCalleeSavedInfo();
154 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
155 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
156 unsigned Reg = CSI[I].getReg();
157 if (Reg == SPU::R0) continue;
158 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
159 MachineLocation CSSrc(Reg);
160 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
161 }
162
163 // Mark effective beginning of when frame pointer is ready.
164 MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol();
165 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel);
166
167 MachineLocation FPDst(SPU::R1);
168 MachineLocation FPSrc(MachineLocation::VirtualFP);
169 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
170 }
171 } else {
172 // This is a leaf function -- insert a branch hint iff there are
173 // sufficient number instructions in the basic block. Note that
174 // this is just a best guess based on the basic block's size.
175 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
176 MachineBasicBlock::iterator MBBI = prior(MBB.end());
177 dl = MBBI->getDebugLoc();
178
179 // Insert terminator label
180 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL))
181 .addSym(MMI.getContext().CreateTempSymbol());
182 }
183 }
184 }
185
186 void SPUFrameInfo::emitEpilogue(MachineFunction &MF,
187 MachineBasicBlock &MBB) const {
188 MachineBasicBlock::iterator MBBI = prior(MBB.end());
189 const SPUInstrInfo &TII =
190 *static_cast(MF.getTarget().getInstrInfo());
191 const MachineFrameInfo *MFI = MF.getFrameInfo();
192 int FrameSize = MFI->getStackSize();
193 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
194 DebugLoc dl = MBBI->getDebugLoc();
195
196 assert(MBBI->getOpcode() == SPU::RET &&
197 "Can only insert epilog into returning blocks");
198 assert((FrameSize & 0xf) == 0 && "FrameSize not aligned");
199
200 // the "empty" frame size is 16 - just the register scavenger spill slot
201 if (FrameSize > 16 || MFI->adjustsStack()) {
202 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
203 if (isInt<10>(FrameSize + LinkSlotOffset)) {
204 // Reload $lr, adjust $sp by required amount
205 // Note: We do this to slightly improve dual issue -- not by much, but it
206 // is an opportunity for dual issue.
207 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
208 .addImm(FrameSize + LinkSlotOffset)
209 .addReg(SPU::R1);
210 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
211 .addReg(SPU::R1)
212 .addImm(FrameSize);
213 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
214 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
215 // $r2 to adjust $sp:
216 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
217 .addImm(16)
218 .addReg(SPU::R1);
219 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
220 .addImm(FrameSize);
221 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
222 .addReg(SPU::R1)
223 .addReg(SPU::R2);
224 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
225 .addImm(16)
226 .addReg(SPU::R1);
227 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
228 addReg(SPU::R2)
229 .addImm(16);
230 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
231 .addReg(SPU::R2)
232 .addReg(SPU::R1);
233 } else {
234 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
235 }
236 }
237 }
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #if !defined(SPUFRAMEINFO_H)
14 #ifndef SPU_FRAMEINFO_H
15 #define SPU_FRAMEINFO_H
1516
17 #include "SPURegisterInfo.h"
1618 #include "llvm/Target/TargetFrameInfo.h"
1719 #include "llvm/Target/TargetMachine.h"
18 #include "SPURegisterInfo.h"
1920
2021 namespace llvm {
22 class SPUSubtarget;
23
2124 class SPUFrameInfo: public TargetFrameInfo {
22 const TargetMachine &TM;
25 const SPUSubtarget &Subtarget;
2326 std::pair LR[1];
2427
2528 public:
26 SPUFrameInfo(const TargetMachine &tm);
29 SPUFrameInfo(const SPUSubtarget &sti);
30
31 //! Determine the frame's layour
32 void determineFrameLayout(MachineFunction &MF) const;
33
34 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
35 /// the function.
36 void emitPrologue(MachineFunction &MF) const;
37 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
2738
2839 //! Return a function's saved spill slots
2940 /*!
7081 };
7182 }
7283
73 #define SPUFRAMEINFO_H 1
7484 #endif
328328 }
329329 }
330330
331 /// determineFrameLayout - Determine the size of the frame and maximum call
332 /// frame size.
333 void
334 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
335 {
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337
338 // Get the number of bytes to allocate from the FrameInfo
339 unsigned FrameSize = MFI->getStackSize();
340
341 // Get the alignments provided by the target, and the maximum alignment
342 // (if any) of the fixed frame objects.
343 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
344 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
345 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
346 unsigned AlignMask = Align - 1;
347
348 // Get the maximum call frame size of all the calls.
349 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
350
351 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
352 // that allocations will be aligned.
353 if (MFI->hasVarSizedObjects())
354 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
355
356 // Update maximum call frame size.
357 MFI->setMaxCallFrameSize(maxCallFrameSize);
358
359 // Include call frame size in total.
360 FrameSize += maxCallFrameSize;
361
362 // Make sure the frame is aligned.
363 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
364
365 // Update frame info.
366 MFI->setStackSize(FrameSize);
367 }
368
369331 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
370332 RegScavenger *RS)
371333 const {
377339 MF.getRegInfo().setPhysRegUnused(SPU::R1);
378340 MF.getRegInfo().setPhysRegUnused(SPU::R2);
379341
380 MachineFrameInfo *MFI = MF.getFrameInfo();
342 MachineFrameInfo *MFI = MF.getFrameInfo();
381343 const TargetRegisterClass *RC = &SPU::R32CRegClass;
382344 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
383345 RC->getAlignment(),
384346 false));
385
386
387 }
388
389 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
390 {
391 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
392 MachineBasicBlock::iterator MBBI = MBB.begin();
393 MachineFrameInfo *MFI = MF.getFrameInfo();
394 MachineModuleInfo &MMI = MF.getMMI();
395 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
396
397 // Prepare for debug frame info.
398 bool hasDebugInfo = MMI.hasDebugInfo();
399 MCSymbol *FrameLabel = 0;
400
401 // Move MBBI back to the beginning of the function.
402 MBBI = MBB.begin();
403
404 // Work out frame sizes.
405 determineFrameLayout(MF);
406 int FrameSize = MFI->getStackSize();
407
408 assert((FrameSize & 0xf) == 0
409 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
410
411 // the "empty" frame size is 16 - just the register scavenger spill slot
412 if (FrameSize > 16 || MFI->adjustsStack()) {
413 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
414 if (hasDebugInfo) {
415 // Mark effective beginning of when frame pointer becomes valid.
416 FrameLabel = MMI.getContext().CreateTempSymbol();
417 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
418 }
419
420 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
421 // for the ABI
422 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
423 .addReg(SPU::R1);
424 if (isInt<10>(FrameSize)) {
425 // Spill $sp to adjusted $sp
426 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
427 .addReg(SPU::R1);
428 // Adjust $sp by required amout
429 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
430 .addImm(FrameSize);
431 } else if (isInt<16>(FrameSize)) {
432 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
433 // $r2 to adjust $sp:
434 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
435 .addImm(-16)
436 .addReg(SPU::R1);
437 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
438 .addImm(FrameSize);
439 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
440 .addReg(SPU::R2)
441 .addReg(SPU::R1);
442 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
443 .addReg(SPU::R1)
444 .addReg(SPU::R2);
445 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
446 .addReg(SPU::R2)
447 .addImm(16);
448 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
449 .addReg(SPU::R2)
450 .addReg(SPU::R1);
451 } else {
452 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
453 }
454
455 if (hasDebugInfo) {
456 std::vector &Moves = MMI.getFrameMoves();
457
458 // Show update of SP.
459 MachineLocation SPDst(MachineLocation::VirtualFP);
460 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
461 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
462
463 // Add callee saved registers to move list.
464 const std::vector &CSI = MFI->getCalleeSavedInfo();
465 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
466 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
467 unsigned Reg = CSI[I].getReg();
468 if (Reg == SPU::R0) continue;
469 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
470 MachineLocation CSSrc(Reg);
471 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
472 }
473
474 // Mark effective beginning of when frame pointer is ready.
475 MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol();
476 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel);
477
478 MachineLocation FPDst(SPU::R1);
479 MachineLocation FPSrc(MachineLocation::VirtualFP);
480 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
481 }
482 } else {
483 // This is a leaf function -- insert a branch hint iff there are
484 // sufficient number instructions in the basic block. Note that
485 // this is just a best guess based on the basic block's size.
486 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
487 MachineBasicBlock::iterator MBBI = prior(MBB.end());
488 dl = MBBI->getDebugLoc();
489
490 // Insert terminator label
491 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL))
492 .addSym(MMI.getContext().CreateTempSymbol());
493 }
494 }
495 }
496
497 void
498 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
499 {
500 MachineBasicBlock::iterator MBBI = prior(MBB.end());
501 const MachineFrameInfo *MFI = MF.getFrameInfo();
502 int FrameSize = MFI->getStackSize();
503 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
504 DebugLoc dl = MBBI->getDebugLoc();
505
506 assert(MBBI->getOpcode() == SPU::RET &&
507 "Can only insert epilog into returning blocks");
508 assert((FrameSize & 0xf) == 0
509 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
510
511 // the "empty" frame size is 16 - just the register scavenger spill slot
512 if (FrameSize > 16 || MFI->adjustsStack()) {
513 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
514 if (isInt<10>(FrameSize + LinkSlotOffset)) {
515 // Reload $lr, adjust $sp by required amount
516 // Note: We do this to slightly improve dual issue -- not by much, but it
517 // is an opportunity for dual issue.
518 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
519 .addImm(FrameSize + LinkSlotOffset)
520 .addReg(SPU::R1);
521 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
522 .addReg(SPU::R1)
523 .addImm(FrameSize);
524 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
525 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
526 // $r2 to adjust $sp:
527 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
528 .addImm(16)
529 .addReg(SPU::R1);
530 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
531 .addImm(FrameSize);
532 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
533 .addReg(SPU::R1)
534 .addReg(SPU::R2);
535 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
536 .addImm(16)
537 .addReg(SPU::R1);
538 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
539 addReg(SPU::R2)
540 .addImm(16);
541 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
542 .addReg(SPU::R2)
543 .addReg(SPU::R1);
544 } else {
545 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
546 }
547 }
548347 }
549348
550349 unsigned
575374 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
576375 }
577376
578 int
377 int
579378 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
580379 {
581 switch(dFormOpcode)
380 switch(dFormOpcode)
582381 {
583382 case SPU::AIr32: return SPU::Ar32;
584383 case SPU::LQDr32: return SPU::LQXr32;
601400
602401 // TODO this is already copied from PPC. Could this convenience function
603402 // be moved to the RegScavenger class?
604 unsigned
605 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
403 unsigned
404 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
606405 RegScavenger *RS,
607 const TargetRegisterClass *RC,
406 const TargetRegisterClass *RC,
608407 int SPAdj) const
609408 {
610409 assert(RS && "Register scavenging must be on");
3232
3333 public:
3434 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
35
35
3636 //! Translate a register's enum value to a register number
3737 /*!
3838 This method translates a register's enum value to it's regiser number,
6464 //! Convert frame indicies into machine operands
6565 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
6666 RegScavenger *RS = NULL) const;
67 //! Determine the frame's layour
68 void determineFrameLayout(MachineFunction &MF) const;
6967
7068 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
7169 RegScavenger *RS = NULL) const;
72 //! Emit the function prologue
73 void emitPrologue(MachineFunction &MF) const;
74 //! Emit the function epilogue
75 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
70
7671 //! Get return address register (LR, aka R0)
7772 unsigned getRARegister() const;
7873 //! Get the stack frame register (SP, aka R1)
3939 Subtarget(TT, FS),
4040 DataLayout(Subtarget.getTargetDataString()),
4141 InstrInfo(*this),
42 FrameInfo(*this),
42 FrameInfo(Subtarget),
4343 TLInfo(*this),
4444 TSInfo(*this),
4545 InstrItins(Subtarget.getInstrItineraryData()) {
0 //=======- MBlazeFrameInfo.cpp - MBlaze Frame Information ------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MBlaze implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MBlazeFrameInfo.h"
14 #include "MBlazeInstrInfo.h"
15 #include "MBlazeMachineFunction.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Support/CommandLine.h"
25
26 using namespace llvm;
27
28
29 //===----------------------------------------------------------------------===//
30 //
31 // Stack Frame Processing methods
32 // +----------------------------+
33 //
34 // The stack is allocated decrementing the stack pointer on
35 // the first instruction of a function prologue. Once decremented,
36 // all stack references are are done through a positive offset
37 // from the stack/frame pointer, so the stack is considered
38 // to grow up.
39 //
40 //===----------------------------------------------------------------------===//
41
42 void MBlazeFrameInfo::adjustMBlazeStackFrame(MachineFunction &MF) const {
43 MachineFrameInfo *MFI = MF.getFrameInfo();
44 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
45 const MBlazeRegisterInfo *RegInfo =
46 static_cast(MF.getTarget().getRegisterInfo());
47
48 // See the description at MicroBlazeMachineFunction.h
49 int TopCPUSavedRegOff = -1;
50
51 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
52 // be saved in this CPU Area there is the need. This whole Area must
53 // be aligned to the default Stack Alignment requirements.
54 unsigned StackOffset = MFI->getStackSize();
55 unsigned RegSize = 4;
56
57 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
58 // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
59 // the approach done by calculateFrameObjectOffsets to the stack frame.
60 MBlazeFI->adjustLoadArgsFI(MFI);
61 MBlazeFI->adjustStoreVarArgsFI(MFI);
62
63 if (RegInfo->hasFP(MF)) {
64 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
65 StackOffset);
66 MBlazeFI->setFPStackOffset(StackOffset);
67 TopCPUSavedRegOff = StackOffset;
68 StackOffset += RegSize;
69 }
70
71 if (MFI->adjustsStack()) {
72 MBlazeFI->setRAStackOffset(0);
73 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
74 StackOffset);
75 TopCPUSavedRegOff = StackOffset;
76 StackOffset += RegSize;
77 }
78
79 // Update frame info
80 MFI->setStackSize(StackOffset);
81
82 // Recalculate the final tops offset. The final values must be '0'
83 // if there isn't a callee saved register for CPU or FPU, otherwise
84 // a negative offset is needed.
85 if (TopCPUSavedRegOff >= 0)
86 MBlazeFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
87 }
88
89 void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const {
90 MachineBasicBlock &MBB = MF.front();
91 MachineFrameInfo *MFI = MF.getFrameInfo();
92 const MBlazeRegisterInfo *RegInfo =
93 static_cast(MF.getTarget().getRegisterInfo());
94 const MBlazeInstrInfo &TII =
95 *static_cast(MF.getTarget().getInstrInfo());
96 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
97 MachineBasicBlock::iterator MBBI = MBB.begin();
98 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
99
100 // Get the right frame order for MBlaze.
101 adjustMBlazeStackFrame(MF);
102
103 // Get the number of bytes to allocate from the FrameInfo.
104 unsigned StackSize = MFI->getStackSize();
105
106 // No need to allocate space on the stack.
107 if (StackSize == 0 && !MFI->adjustsStack()) return;
108 if (StackSize < 28 && MFI->adjustsStack()) StackSize = 28;
109
110 int FPOffset = MBlazeFI->getFPStackOffset();
111 int RAOffset = MBlazeFI->getRAStackOffset();
112
113 // Adjust stack : addi R1, R1, -imm
114 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
115 .addReg(MBlaze::R1).addImm(-StackSize);
116
117 // Save the return address only if the function isnt a leaf one.
118 // swi R15, R1, stack_loc
119 if (MFI->adjustsStack()) {
120 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
121 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset);
122 }
123
124 // if framepointer enabled, save it and set it
125 // to point to the stack pointer
126 if (RegInfo->hasFP(MF)) {
127 // swi R19, R1, stack_loc
128 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
129 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset);
130
131 // add R19, R1, R0
132 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
133 .addReg(MBlaze::R1).addReg(MBlaze::R0);
134 }
135 }
136
137 void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF,
138 MachineBasicBlock &MBB) const {
139 MachineBasicBlock::iterator MBBI = prior(MBB.end());
140 MachineFrameInfo *MFI = MF.getFrameInfo();
141 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
142 const MBlazeRegisterInfo *RegInfo =
143 static_cast(MF.getTarget().getRegisterInfo());
144 const MBlazeInstrInfo &TII =
145 *static_cast(MF.getTarget().getInstrInfo());
146
147 DebugLoc dl = MBBI->getDebugLoc();
148
149 // Get the FI's where RA and FP are saved.
150 int FPOffset = MBlazeFI->getFPStackOffset();
151 int RAOffset = MBlazeFI->getRAStackOffset();
152
153 // if framepointer enabled, restore it and restore the
154 // stack pointer
155 if (RegInfo->hasFP(MF)) {
156 // add R1, R19, R0
157 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1)
158 .addReg(MBlaze::R19).addReg(MBlaze::R0);
159
160 // lwi R19, R1, stack_loc
161 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19)
162 .addReg(MBlaze::R1).addImm(FPOffset);
163 }
164
165 // Restore the return address only if the function isnt a leaf one.
166 // lwi R15, R1, stack_loc
167 if (MFI->adjustsStack()) {
168 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15)
169 .addReg(MBlaze::R1).addImm(RAOffset);
170 }
171
172 // Get the number of bytes from FrameInfo
173 int StackSize = (int) MFI->getStackSize();
174 if (StackSize < 28 && MFI->adjustsStack()) StackSize = 28;
175
176 // adjust stack.
177 // addi R1, R1, imm
178 if (StackSize) {
179 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
180 .addReg(MBlaze::R1).addImm(StackSize);
181 }
182 }
0 //=-- MBlazeFrameInfo.h - Define TargetFrameInfo for MicroBlaze --*- C++ -*--=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ALPHA_FRAMEINFO_H
14 #define ALPHA_FRAMEINFO_H
15
16 #include "MBlaze.h"
17 #include "MBlazeSubtarget.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19
20 namespace llvm {
21 class MBlazeSubtarget;
22
23 class MBlazeFrameInfo : public TargetFrameInfo {
24 protected:
25 const MBlazeSubtarget &STI;
26
27 public:
28 explicit MBlazeFrameInfo(const MBlazeSubtarget &sti)
29 : TargetFrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0), STI(sti) {
30 }
31
32 void adjustMBlazeStackFrame(MachineFunction &MF) const;
33
34 /// targetHandlesStackFrameRounding - Returns true if the target is
35 /// responsible for rounding up the stack frame (probably at emitPrologue
36 /// time).
37 bool targetHandlesStackFrameRounding() const { return true; }
38
39 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
40 /// the function.
41 void emitPrologue(MachineFunction &MF) const;
42 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
43 };
44
45 } // End llvm namespace
46
47 #endif
163163 return Reserved;
164164 }
165165
166 //===----------------------------------------------------------------------===//
167 //
168 // Stack Frame Processing methods
169 // +----------------------------+
170 //
171 // The stack is allocated decrementing the stack pointer on
172 // the first instruction of a function prologue. Once decremented,
173 // all stack references are are done through a positive offset
174 // from the stack/frame pointer, so the stack is considered
175 // to grow up.
176 //
177 //===----------------------------------------------------------------------===//
178
179 void MBlazeRegisterInfo::adjustMBlazeStackFrame(MachineFunction &MF) const {
180 MachineFrameInfo *MFI = MF.getFrameInfo();
181 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
182
183 // See the description at MicroBlazeMachineFunction.h
184 int TopCPUSavedRegOff = -1;
185
186 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
187 // be saved in this CPU Area there is the need. This whole Area must
188 // be aligned to the default Stack Alignment requirements.
189 unsigned StackOffset = MFI->getStackSize();
190 unsigned RegSize = 4;
191
192 // Replace the dummy '0' SPOffset by the negative offsets, as explained on
193 // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
194 // the approach done by calculateFrameObjectOffsets to the stack frame.
195 MBlazeFI->adjustLoadArgsFI(MFI);
196 MBlazeFI->adjustStoreVarArgsFI(MFI);
197
198 if (hasFP(MF)) {
199 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
200 StackOffset);
201 MBlazeFI->setFPStackOffset(StackOffset);
202 TopCPUSavedRegOff = StackOffset;
203 StackOffset += RegSize;
204 }
205
206 if (MFI->adjustsStack()) {
207 MBlazeFI->setRAStackOffset(0);
208 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
209 StackOffset);
210 TopCPUSavedRegOff = StackOffset;
211 StackOffset += RegSize;
212 }
213
214 // Update frame info
215 MFI->setStackSize(StackOffset);
216
217 // Recalculate the final tops offset. The final values must be '0'
218 // if there isn't a callee saved register for CPU or FPU, otherwise
219 // a negative offset is needed.
220 if (TopCPUSavedRegOff >= 0)
221 MBlazeFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
222 }
223
224166 // hasFP - Return true if the specified function should have a dedicated frame
225167 // pointer register. This is true if the function has variable sized allocas or
226168 // if frame pointer elimination is disabled.
279221 }
280222
281223 void MBlazeRegisterInfo::
282 emitPrologue(MachineFunction &MF) const {
283 MachineBasicBlock &MBB = MF.front();
284 MachineFrameInfo *MFI = MF.getFrameInfo();
285 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
286 MachineBasicBlock::iterator MBBI = MBB.begin();
287 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
288
289 // Get the right frame order for MBlaze.
290 adjustMBlazeStackFrame(MF);
291
292 // Get the number of bytes to allocate from the FrameInfo.
293 unsigned StackSize = MFI->getStackSize();
294
295 // No need to allocate space on the stack.
296 if (StackSize == 0 && !MFI->adjustsStack()) return;
297 if (StackSize < 28 && MFI->adjustsStack()) StackSize = 28;
298
299 int FPOffset = MBlazeFI->getFPStackOffset();
300 int RAOffset = MBlazeFI->getRAStackOffset();
301
302 // Adjust stack : addi R1, R1, -imm
303 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
304 .addReg(MBlaze::R1).addImm(-StackSize);
305
306 // Save the return address only if the function isnt a leaf one.
307 // swi R15, R1, stack_loc
308 if (MFI->adjustsStack()) {
309 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
310 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset);
311 }
312
313 // if framepointer enabled, save it and set it
314 // to point to the stack pointer
315 if (hasFP(MF)) {
316 // swi R19, R1, stack_loc
317 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI))
318 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset);
319
320 // add R19, R1, R0
321 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
322 .addReg(MBlaze::R1).addReg(MBlaze::R0);
323 }
324 }
325
326 void MBlazeRegisterInfo::
327 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
328 MachineBasicBlock::iterator MBBI = prior(MBB.end());
329 MachineFrameInfo *MFI = MF.getFrameInfo();
330 MBlazeFunctionInfo *MBlazeFI = MF.getInfo();
331 DebugLoc dl = MBBI->getDebugLoc();
332
333 // Get the FI's where RA and FP are saved.
334 int FPOffset = MBlazeFI->getFPStackOffset();
335 int RAOffset = MBlazeFI->getRAStackOffset();
336
337 // if framepointer enabled, restore it and restore the
338 // stack pointer
339 if (hasFP(MF)) {
340 // add R1, R19, R0
341 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1)
342 .addReg(MBlaze::R19).addReg(MBlaze::R0);
343
344 // lwi R19, R1, stack_loc
345 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19)
346 .addReg(MBlaze::R1).addImm(FPOffset);
347 }
348
349 // Restore the return address only if the function isnt a leaf one.
350 // lwi R15, R1, stack_loc
351 if (MFI->adjustsStack()) {
352 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15)
353 .addReg(MBlaze::R1).addImm(RAOffset);
354 }
355
356 // Get the number of bytes from FrameInfo
357 int StackSize = (int) MFI->getStackSize();
358 if (StackSize < 28 && MFI->adjustsStack()) StackSize = 28;
359
360 // adjust stack.
361 // addi R1, R1, imm
362 if (StackSize) {
363 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
364 .addReg(MBlaze::R1).addImm(StackSize);
365 }
366 }
367
368
369 void MBlazeRegisterInfo::
370224 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
371225 // Set the stack offset where GP must be saved/loaded from.
372226 MachineFrameInfo *MFI = MF.getFrameInfo();
6767
6868 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
6969
70 void emitPrologue(MachineFunction &MF) const;
71 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
72
7370 /// Debug information queries.
7471 unsigned getRARegister() const;
7572 unsigned getFrameRegister(const MachineFunction &MF) const;
7875 unsigned getEHExceptionRegister() const;
7976 unsigned getEHHandlerRegister() const;
8077
81 /// targetHandlesStackFrameRounding - Returns true if the target is
82 /// responsible for rounding up the stack frame (probably at emitPrologue
83 /// time).
84 bool targetHandlesStackFrameRounding() const { return true; }
85
8678 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
8779 };
8880
8484 Subtarget(TT, FS),
8585 DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
8686 InstrInfo(*this),
87 FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
87 FrameInfo(Subtarget),
8888 TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this) {
8989 if (getRelocationModel() == Reloc::Default) {
9090 setRelocationModel(Reloc::Static);
1818 #include "MBlazeISelLowering.h"
1919 #include "MBlazeSelectionDAGInfo.h"
2020 #include "MBlazeIntrinsicInfo.h"
21 #include "MBlazeFrameInfo.h"
2122 #include "MBlazeELFWriterInfo.h"
2223 #include "llvm/MC/MCStreamer.h"
2324 #include "llvm/Target/TargetMachine.h"
3132 MBlazeSubtarget Subtarget;
3233 const TargetData DataLayout; // Calculates type size & alignment
3334 MBlazeInstrInfo InstrInfo;
34 TargetFrameInfo FrameInfo;
35 MBlazeFrameInfo FrameInfo;
3536 MBlazeTargetLowering TLInfo;
3637 MBlazeSelectionDAGInfo TSInfo;
3738 MBlazeIntrinsicInfo IntrinsicInfo;
0 //=======- MSP430FrameInfo.cpp - MSP430 Frame Information ------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MSP430 implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MSP430FrameInfo.h"
14 #include "MSP430InstrInfo.h"
15 #include "MSP430MachineFunctionInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Support/CommandLine.h"
25
26 using namespace llvm;
27
28 void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const {
29 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
30 MachineFrameInfo *MFI = MF.getFrameInfo();
31 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
32 const MSP430RegisterInfo *RegInfo =
33 static_cast(MF.getTarget().getRegisterInfo());
34 const MSP430InstrInfo &TII =
35 *static_cast(MF.getTarget().getInstrInfo());
36
37 MachineBasicBlock::iterator MBBI = MBB.begin();
38 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
39
40 // Get the number of bytes to allocate from the FrameInfo.
41 uint64_t StackSize = MFI->getStackSize();
42
43 uint64_t NumBytes = 0;
44 if (RegInfo->hasFP(MF)) {
45 // Calculate required stack adjustment
46 uint64_t FrameSize = StackSize - 2;
47 NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
48
49 // Get the offset of the stack slot for the EBP register... which is
50 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
51 // Update the frame offset adjustment.
52 MFI->setOffsetAdjustment(-NumBytes);
53
54 // Save FPW into the appropriate stack slot...
55 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
56 .addReg(MSP430::FPW, RegState::Kill);
57
58 // Update FPW with the new base value...
59 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
60 .addReg(MSP430::SPW);
61
62 // Mark the FramePtr as live-in in every block except the entry.
63 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
64 I != E; ++I)
65 I->addLiveIn(MSP430::FPW);
66
67 } else
68 NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
69
70 // Skip the callee-saved push instructions.
71 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
72 ++MBBI;
73
74 if (MBBI != MBB.end())
75 DL = MBBI->getDebugLoc();
76
77 if (NumBytes) { // adjust stack pointer: SPW -= numbytes
78 // If there is an SUB16ri of SPW immediately before this instruction, merge
79 // the two.
80 //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
81 // If there is an ADD16ri or SUB16ri of SPW immediately after this
82 // instruction, merge the two instructions.
83 // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
84
85 if (NumBytes) {
86 MachineInstr *MI =
87 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
88 .addReg(MSP430::SPW).addImm(NumBytes);
89 // The SRW implicit def is dead.
90 MI->getOperand(3).setIsDead();
91 }
92 }
93 }
94
95 void MSP430FrameInfo::emitEpilogue(MachineFunction &MF,
96 MachineBasicBlock &MBB) const {
97 const MachineFrameInfo *MFI = MF.getFrameInfo();
98 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
99 const MSP430RegisterInfo *RegInfo =
100 static_cast(MF.getTarget().getRegisterInfo());
101 const MSP430InstrInfo &TII =
102 *static_cast(MF.getTarget().getInstrInfo());
103
104 MachineBasicBlock::iterator MBBI = prior(MBB.end());
105 unsigned RetOpcode = MBBI->getOpcode();
106 DebugLoc DL = MBBI->getDebugLoc();
107
108 switch (RetOpcode) {
109 case MSP430::RET:
110 case MSP430::RETI: break; // These are ok
111 default:
112 llvm_unreachable("Can only insert epilog into returning blocks");
113 }
114
115 // Get the number of bytes to allocate from the FrameInfo
116 uint64_t StackSize = MFI->getStackSize();
117 unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
118 uint64_t NumBytes = 0;
119
120 if (RegInfo->hasFP(MF)) {
121 // Calculate required stack adjustment
122 uint64_t FrameSize = StackSize - 2;
123 NumBytes = FrameSize - CSSize;
124
125 // pop FPW.
126 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
127 } else
128 NumBytes = StackSize - CSSize;
129
130 // Skip the callee-saved pop instructions.
131 while (MBBI != MBB.begin()) {
132 MachineBasicBlock::iterator PI = prior(MBBI);
133 unsigned Opc = PI->getOpcode();
134 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
135 break;
136 --MBBI;
137 }
138
139 DL = MBBI->getDebugLoc();
140
141 // If there is an ADD16ri or SUB16ri of SPW immediately before this
142 // instruction, merge the two instructions.
143 //if (NumBytes || MFI->hasVarSizedObjects())
144 // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
145
146 if (MFI->hasVarSizedObjects()) {
147 BuildMI(MBB, MBBI, DL,
148 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
149 if (CSSize) {
150 MachineInstr *MI =
151 BuildMI(MBB, MBBI, DL,
152 TII.get(MSP430::SUB16ri), MSP430::SPW)
153 .addReg(MSP430::SPW).addImm(CSSize);
154 // The SRW implicit def is dead.
155 MI->getOperand(3).setIsDead();
156 }
157 } else {
158 // adjust stack pointer back: SPW += numbytes
159 if (NumBytes) {
160 MachineInstr *MI =
161 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
162 .addReg(MSP430::SPW).addImm(NumBytes);
163 // The SRW implicit def is dead.
164 MI->getOperand(3).setIsDead();
165 }
166 }
167 }
0 //===-- MSP430FrameInfo.h - Define TargetFrameInfo for MSP430 --*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef MSP430_FRAMEINFO_H
14 #define MSP430_FRAMEINFO_H
15
16 #include "MSP430.h"
17 #include "MSP430Subtarget.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19
20 namespace llvm {
21 class MSP430Subtarget;
22
23 class MSP430FrameInfo : public TargetFrameInfo {
24 protected:
25 const MSP430Subtarget &STI;
26
27 public:
28 explicit MSP430FrameInfo(const MSP430Subtarget &sti)
29 : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) {
30 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36 };
37
38 } // End llvm namespace
39
40 #endif
232232 }
233233 }
234234
235
236 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
237 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
238 MachineFrameInfo *MFI = MF.getFrameInfo();
239 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
240 MachineBasicBlock::iterator MBBI = MBB.begin();
241 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
242
243 // Get the number of bytes to allocate from the FrameInfo.
244 uint64_t StackSize = MFI->getStackSize();
245
246 uint64_t NumBytes = 0;
247 if (hasFP(MF)) {
248 // Calculate required stack adjustment
249 uint64_t FrameSize = StackSize - 2;
250 NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
251
252 // Get the offset of the stack slot for the EBP register... which is
253 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
254 // Update the frame offset adjustment.
255 MFI->setOffsetAdjustment(-NumBytes);
256
257 // Save FPW into the appropriate stack slot...
258 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
259 .addReg(MSP430::FPW, RegState::Kill);
260
261 // Update FPW with the new base value...
262 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
263 .addReg(MSP430::SPW);
264
265 // Mark the FramePtr as live-in in every block except the entry.
266 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
267 I != E; ++I)
268 I->addLiveIn(MSP430::FPW);
269
270 } else
271 NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
272
273 // Skip the callee-saved push instructions.
274 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
275 ++MBBI;
276
277 if (MBBI != MBB.end())
278 DL = MBBI->getDebugLoc();
279
280 if (NumBytes) { // adjust stack pointer: SPW -= numbytes
281 // If there is an SUB16ri of SPW immediately before this instruction, merge
282 // the two.
283 //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
284 // If there is an ADD16ri or SUB16ri of SPW immediately after this
285 // instruction, merge the two instructions.
286 // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
287
288 if (NumBytes) {
289 MachineInstr *MI =
290 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
291 .addReg(MSP430::SPW).addImm(NumBytes);
292 // The SRW implicit def is dead.
293 MI->getOperand(3).setIsDead();
294 }
295 }
296 }
297
298 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
299 MachineBasicBlock &MBB) const {
300 const MachineFrameInfo *MFI = MF.getFrameInfo();
301 MSP430MachineFunctionInfo *MSP430FI = MF.getInfo();
302 MachineBasicBlock::iterator MBBI = prior(MBB.end());
303 unsigned RetOpcode = MBBI->getOpcode();
304 DebugLoc DL = MBBI->getDebugLoc();
305
306 switch (RetOpcode) {
307 case MSP430::RET:
308 case MSP430::RETI: break; // These are ok
309 default:
310 llvm_unreachable("Can only insert epilog into returning blocks");
311 }
312
313 // Get the number of bytes to allocate from the FrameInfo
314 uint64_t StackSize = MFI->getStackSize();
315 unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
316 uint64_t NumBytes = 0;
317
318 if (hasFP(MF)) {
319 // Calculate required stack adjustment
320 uint64_t FrameSize = StackSize - 2;
321 NumBytes = FrameSize - CSSize;
322
323 // pop FPW.
324 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
325 } else
326 NumBytes = StackSize - CSSize;
327
328 // Skip the callee-saved pop instructions.
329 while (MBBI != MBB.begin()) {
330 MachineBasicBlock::iterator PI = prior(MBBI);
331 unsigned Opc = PI->getOpcode();
332 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
333 break;
334 --MBBI;
335 }
336
337 DL = MBBI->getDebugLoc();
338
339 // If there is an ADD16ri or SUB16ri of SPW immediately before this
340 // instruction, merge the two instructions.
341 //if (NumBytes || MFI->hasVarSizedObjects())
342 // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
343
344 if (MFI->hasVarSizedObjects()) {
345 BuildMI(MBB, MBBI, DL,
346 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
347 if (CSSize) {
348 MachineInstr *MI =
349 BuildMI(MBB, MBBI, DL,
350 TII.get(MSP430::SUB16ri), MSP430::SPW)
351 .addReg(MSP430::SPW).addImm(CSSize);
352 // The SRW implicit def is dead.
353 MI->getOperand(3).setIsDead();
354 }
355 } else {
356 // adjust stack pointer back: SPW += numbytes
357 if (NumBytes) {
358 MachineInstr *MI =
359 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
360 .addReg(MSP430::SPW).addImm(NumBytes);
361 // The SRW implicit def is dead.
362 MI->getOperand(3).setIsDead();
363 }
364 }
365 }
366
367235 unsigned MSP430RegisterInfo::getRARegister() const {
368236 return MSP430::PCW;
369237 }
4848 void eliminateFrameIndex(MachineBasicBlock::iterator II,
4949 int SPAdj, RegScavenger *RS = NULL) const;
5050
51 void emitPrologue(MachineFunction &MF) const;
52 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
53
5451 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
5552