llvm.org GIT mirror llvm / 3336cab
TableGen: Support physical register inputs > 255 This was truncating register value that didn't fit in unsigned char. Switch AMDGPU sendmsg intrinsics to using a tablegen pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366695 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 26 days ago
5 changed file(s) with 33 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
161161 OPC_EmitMergeInputChains1_1,
162162 OPC_EmitMergeInputChains1_2,
163163 OPC_EmitCopyToReg,
164 OPC_EmitCopyToReg2,
164165 OPC_EmitNodeXForm,
165166 OPC_EmitNode,
166167 // Space-optimized forms that implicitly encode number of result VTs.
33223322 continue;
33233323 }
33243324
3325 case OPC_EmitCopyToReg: {
3325 case OPC_EmitCopyToReg:
3326 case OPC_EmitCopyToReg2: {
33263327 unsigned RecNo = MatcherTable[MatcherIndex++];
33273328 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
33283329 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3330 if (Opcode == OPC_EmitCopyToReg2)
3331 DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
33293332
33303333 if (!InputChain.getNode())
33313334 InputChain = CurDAG->getEntryNode();
931931 ///
932932 class EmitCopyToRegMatcher : public Matcher {
933933 unsigned SrcSlot; // Value to copy into the physreg.
934 Record *DestPhysReg;
935 public:
936 EmitCopyToRegMatcher(unsigned srcSlot, Record *destPhysReg)
934 const CodeGenRegister *DestPhysReg;
935
936 public:
937 EmitCopyToRegMatcher(unsigned srcSlot,
938 const CodeGenRegister *destPhysReg)
937939 : Matcher(EmitCopyToReg), SrcSlot(srcSlot), DestPhysReg(destPhysReg) {}
938940
939941 unsigned getSrcSlot() const { return SrcSlot; }
940 Record *getDestPhysReg() const { return DestPhysReg; }
942 const CodeGenRegister *getDestPhysReg() const { return DestPhysReg; }
941943
942944 static bool classof(const Matcher *N) {
943945 return N->getKind() == EmitCopyToReg;
669669 OS << '\n';
670670 return 2+MN->getNumNodes();
671671 }
672 case Matcher::EmitCopyToReg:
673 OS << "OPC_EmitCopyToReg, "
674 << cast(N)->getSrcSlot() << ", "
675 << getQualifiedName(cast(N)->getDestPhysReg())
676 << ",\n";
677 return 3;
672 case Matcher::EmitCopyToReg: {
673 const auto *C2RMatcher = cast(N);
674 int Bytes = 3;
675 const CodeGenRegister *Reg = C2RMatcher->getDestPhysReg();
676 if (Reg->EnumValue > 255) {
677 assert(isUInt<16>(Reg->EnumValue) && "not handled");
678 OS << "OPC_EmitCopyToReg2, " << C2RMatcher->getSrcSlot() << ", "
679 << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
680 ++Bytes;
681 } else {
682 OS << "OPC_EmitCopyToReg, " << C2RMatcher->getSrcSlot() << ", "
683 << getQualifiedName(Reg->TheDef) << ",\n";
684 }
685
686 return Bytes;
687 }
678688 case Matcher::EmitNodeXForm: {
679689 const EmitNodeXFormMatcher *XF = cast(N);
680690 OS << "OPC_EmitNodeXForm, " << getNodeXFormID(XF->getNodeXForm()) << ", "
866866 if (isRoot && !PhysRegInputs.empty()) {
867867 // Emit all of the CopyToReg nodes for the input physical registers. These
868868 // occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
869 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
869 for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i) {
870 const CodeGenRegister *Reg =
871 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first);
870872 AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
871 PhysRegInputs[i].first));
873 Reg));
874 }
875
872876 // Even if the node has no other glue inputs, the resultant node must be
873877 // glued to the CopyFromReg nodes we just generated.
874878 TreeHasInGlue = true;