llvm.org GIT mirror llvm / 33242fd
Add an experimental early if-conversion pass, off by default. This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
7 changed file(s) with 649 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
391391 /// into tails of their predecessors.
392392 extern char &TailDuplicateID;
393393
394 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
395 /// inserting cmov instructions.
396 extern char &EarlyIfConverterID;
397
394398 /// IfConverter - This pass performs machine code if conversion.
395399 extern char &IfConverterID;
396400
9999 void initializeDomViewerPass(PassRegistry&);
100100 void initializeDominanceFrontierPass(PassRegistry&);
101101 void initializeDominatorTreePass(PassRegistry&);
102 void initializeEarlyIfConverterPass(PassRegistry&);
102103 void initializeEdgeBundlesPass(PassRegistry&);
103104 void initializeEdgeProfilerPass(PassRegistry&);
104105 void initializeExpandPostRAPass(PassRegistry&);
366366 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
367367 MachineBasicBlock &FMBB) const {
368368 return false;
369 }
370
371 /// canInsertSelect - Return true if it is possible to insert a select
372 /// instruction that chooses between TrueReg and FalseReg based on the
373 /// condition code in Cond.
374 ///
375 /// When successful, also return the latency in cycles from TrueReg,
376 /// FalseReg, and Cond to the destination register. The Cond latency should
377 /// compensate for a conditional branch being removed. For example, if a
378 /// conditional branch has a 3 cycle latency from the condition code read,
379 /// and a cmov instruction has a 2 cycle latency from the condition code
380 /// read, CondCycles should be returned as -1.
381 ///
382 /// @param MBB Block where select instruction would be inserted.
383 /// @param Cond Condition returned by AnalyzeBranch.
384 /// @param TrueReg Virtual register to select when Cond is true.
385 /// @param FalseReg Virtual register to select when Cond is false.
386 /// @param CondCycles Latency from Cond+Branch to select output.
387 /// @param TrueCycles Latency from TrueReg to select output.
388 /// @param FalseCycles Latency from FalseReg to select output.
389 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
390 const SmallVectorImpl &Cond,
391 unsigned TrueReg, unsigned FalseReg,
392 int &CondCycles,
393 int &TrueCycles, int &FalseCycles) const {
394 return false;
395 }
396
397 /// insertSelect - Insert a select instruction into MBB before I that will
398 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
399 /// Cond is false.
400 ///
401 /// This function can only be called after canInsertSelect() returned true.
402 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
403 /// that the same flags or registers required by Cond are available at the
404 /// insertion point.
405 ///
406 /// @param MBB Block where select instruction should be inserted.
407 /// @param I Insertion point.
408 /// @param DL Source location for debugging.
409 /// @param DstReg Virtual register to be defined by select instruction.
410 /// @param Cond Condition as computed by AnalyzeBranch.
411 /// @param TrueReg Virtual register to copy when Cond is true.
412 /// @param FalseReg Virtual register to copy when Cons is false.
413 virtual void insertSelect(MachineBasicBlock &MBB,
414 MachineBasicBlock::iterator I, DebugLoc DL,
415 unsigned DstReg,
416 const SmallVectorImpl &Cond,
417 unsigned TrueReg, unsigned FalseReg) const {
418 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
369419 }
370420
371421 /// copyPhysReg - Emit instructions to copy a pair of physical registers.
1010 DeadMachineInstructionElim.cpp
1111 DFAPacketizer.cpp
1212 DwarfEHPrepare.cpp
13 EarlyIfConversion.cpp
1314 EdgeBundles.cpp
1415 ExecutionDepsFix.cpp
1516 ExpandISelPseudos.cpp
2222 initializeCalculateSpillWeightsPass(Registry);
2323 initializeCodePlacementOptPass(Registry);
2424 initializeDeadMachineInstructionElimPass(Registry);
25 initializeEarlyIfConverterPass(Registry);
2526 initializeExpandPostRAPass(Registry);
2627 initializeExpandISelPseudosPass(Registry);
2728 initializeFinalizeMachineBundlesPass(Registry);
0 //===-- EarlyIfConversion.cpp - If-conversion on SSA form machine code ----===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Early if-conversion is for out-of-order CPUs that don't have a lot of
10 // predicable instructions. The goal is to eliminate conditional branches that
11 // may mispredict.
12 //
13 // Instructions from both sides of the branch are executed specutatively, and a
14 // cmov instruction selects the result.
15 //
16 //===----------------------------------------------------------------------===//
17
18 #define DEBUG_TYPE "early-ifcvt"
19 #include "llvm/Function.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SparseSet.h"
24 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34
35 using namespace llvm;
36
37 // Absolute maximum number of instructions allowed per speculated block.
38 // This bypasses all other heuristics, so it should be set fairly high.
39 static cl::opt
40 BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden,
41 cl::desc("Maximum number of instructions per speculated block."));
42
43 // Stress testing mode - disable heuristics.
44 static cl::opt Stress("stress-early-ifcvt", cl::Hidden,
45 cl::desc("Turn all knobs to 11"));
46
47 typedef SmallSetVector BlockSetVector;
48
49 //===----------------------------------------------------------------------===//
50 // SSAIfConv
51 //===----------------------------------------------------------------------===//
52 //
53 // The SSAIfConv class performs if-conversion on SSA form machine code after
54 // determining if it is possible. The class contains no heuristics, external
55 // code should be used to determine when if-conversion is a good idea.
56 //
57 // SSAIfConv con convert both triangles and diamonds:
58 //
59 // Triangle: Head Diamond: Head
60 // | \ / \
61 // | \ / \
62 // | [TF]BB FBB TBB
63 // | / \ /
64 // | / \ /
65 // Tail Tail
66 //
67 // Instructions in the conditional blocks TBB and/or FBB are spliced into the
68 // Head block, and phis in the Tail black are converted to select instruction.
69 //
70 namespace {
71 class SSAIfConv {
72 const TargetInstrInfo *TII;
73 const TargetRegisterInfo *TRI;
74 MachineRegisterInfo *MRI;
75
76 /// The block containing the conditional branch.
77 MachineBasicBlock *Head;
78
79 /// The block containing phis after the if-then-else.
80 MachineBasicBlock *Tail;
81
82 /// The 'true' conditional block as determined by AnalyzeBranch.
83 MachineBasicBlock *TBB;
84
85 /// The 'false' conditional block as determined by AnalyzeBranch.
86 MachineBasicBlock *FBB;
87
88 /// isTriangle - When there is no 'else' block, either TBB or FBB will be
89 /// equal to Tail.
90 bool isTriangle() const { return TBB == Tail || FBB == Tail; }
91
92 /// The branch condition determined by AnalyzeBranch.
93 SmallVector Cond;
94
95 /// Information about each phi in the Tail block.
96 struct PHIInfo {
97 MachineInstr *PHI;
98 unsigned TReg, FReg;
99 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
100 int CondCycles, TCycles, FCycles;
101
102 PHIInfo(MachineInstr *phi)
103 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
104 };
105
106 SmallVector PHIs;
107
108 /// Instructions in Head that define values used by the conditional blocks.
109 /// The hoisted instructions must be inserted after these instructions.
110 SmallPtrSet InsertAfter;
111
112 /// Register units clobbered by the conditional blocks.
113 BitVector ClobberedRegUnits;
114
115 // Scratch pad for findInsertionPoint.
116 SparseSet LiveRegUnits;
117
118 /// Insertion point in Head for speculatively executed instructions form TBB
119 /// and FBB.
120 MachineBasicBlock::iterator InsertionPoint;
121
122 /// Return true if all non-terminator instructions in MBB can be safely
123 /// speculated.
124 bool canSpeculateInstrs(MachineBasicBlock *MBB);
125
126 /// Find a valid insertion point in Head.
127 bool findInsertionPoint();
128
129 public:
130 /// runOnMachineFunction - Initialize per-function data structures.
131 void runOnMachineFunction(MachineFunction &MF) {
132 TII = MF.getTarget().getInstrInfo();
133 TRI = MF.getTarget().getRegisterInfo();
134 MRI = &MF.getRegInfo();
135 LiveRegUnits.clear();
136 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
137 ClobberedRegUnits.clear();
138 ClobberedRegUnits.resize(TRI->getNumRegUnits());
139 }
140
141 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
142 /// initialize the internal state, and return true.
143 bool canConvertIf(MachineBasicBlock *MBB);
144
145 /// convertIf - If-convert the last block passed to canConvertIf(), assuming
146 /// it is possible. Remove any erased blocks from WorkList
147 void convertIf(BlockSetVector &WorkList);
148 };
149 } // end anonymous namespace
150
151
152 /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
153 /// be speculated. The terminators are not considered.
154 ///
155 /// If instructions use any values that are defined in the head basic block,
156 /// the defining instructions are added to InsertAfter.
157 ///
158 /// Any clobbered regunits are added to ClobberedRegUnits.
159 ///
160 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
161 // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
162 // get right.
163 if (!MBB->livein_empty()) {
164 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
165 return false;
166 }
167
168 unsigned InstrCount = 0;
169 for (MachineBasicBlock::iterator I = MBB->begin(),
170 E = MBB->getFirstTerminator(); I != E; ++I) {
171 if (I->isDebugValue())
172 continue;
173
174 if (++InstrCount > BlockInstrLimit && !Stress) {
175 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
176 << BlockInstrLimit << " instructions.\n");
177 return false;
178 }
179
180 // There shouldn't normally be any phis in a single-predecessor block.
181 if (I->isPHI()) {
182 DEBUG(dbgs() << "Can't hoist: " << *I);
183 return false;
184 }
185
186 // Don't speculate loads. Note that it may be possible and desirable to
187 // speculate GOT or constant pool loads that are guaranteed not to trap,
188 // but we don't support that for now.
189 if (I->mayLoad()) {
190 DEBUG(dbgs() << "Won't speculate load: " << *I);
191 return false;
192 }
193
194 // We never speculate stores, so an AA pointer isn't necessary.
195 bool DontMoveAcrossStore = true;
196 if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) {
197 DEBUG(dbgs() << "Can't speculate: " << *I);
198 return false;
199 }
200
201 // Check for any dependencies on Head instructions.
202 for (MIOperands MO(I); MO.isValid(); ++MO) {
203 if (MO->isRegMask()) {
204 DEBUG(dbgs() << "Won't speculate regmask: " << *I);
205 return false;
206 }
207 if (!MO->isReg())
208 continue;
209 unsigned Reg = MO->getReg();
210
211 // Remember clobbered regunits.
212 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
213 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
214 ClobberedRegUnits.set(*Units);
215
216 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
217 continue;
218 MachineInstr *DefMI = MRI->getVRegDef(Reg);
219 if (!DefMI || DefMI->getParent() != Head)
220 continue;
221 if (InsertAfter.insert(DefMI))
222 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
223 if (DefMI->isTerminator()) {
224 DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
225 return false;
226 }
227 }
228 }
229 return true;
230 }
231
232
233 /// Find an insertion point in Head for the speculated instructions. The
234 /// insertion point must be:
235 ///
236 /// 1. Before any terminators.
237 /// 2. After any instructions in InsertAfter.
238 /// 3. Not have any clobbered regunits live.
239 ///
240 /// This function sets InsertionPoint and returns true when successful, it
241 /// returns false if no valid insertion point could be found.
242 ///
243 bool SSAIfConv::findInsertionPoint() {
244 // Keep track of live regunits before the current position.
245 // Only track RegUnits that are also in ClobberedRegUnits.
246 LiveRegUnits.clear();
247 SmallVector Reads;
248 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
249 MachineBasicBlock::iterator I = Head->end();
250 MachineBasicBlock::iterator B = Head->begin();
251 while (I != B) {
252 --I;
253 // Some of the conditional code depends in I.
254 if (InsertAfter.count(I)) {
255 DEBUG(dbgs() << "Can't insert code after " << *I);
256 return false;
257 }
258
259 // Update live regunits.
260 for (MIOperands MO(I); MO.isValid(); ++MO) {
261 // We're ignoring regmask operands. That is conservatively correct.
262 if (!MO->isReg())
263 continue;
264 unsigned Reg = MO->getReg();
265 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
266 continue;
267 // I clobbers Reg, so it isn't live before I.
268 if (MO->isDef())
269 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
270 LiveRegUnits.erase(*Units);
271 // Unless I reads Reg.
272 if (MO->readsReg())
273 Reads.push_back(Reg);
274 }
275 // Anything read by I is live before I.
276 while (!Reads.empty())
277 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
278 ++Units)
279 if (ClobberedRegUnits.test(*Units))
280 LiveRegUnits.insert(*Units);
281
282 // We can't insert before a terminator.
283 if (I != FirstTerm && I->isTerminator())
284 continue;
285
286 // Some of the clobbered registers are live before I, not a valid insertion
287 // point.
288 if (!LiveRegUnits.empty()) {
289 DEBUG({
290 dbgs() << "Would clobber";
291 for (SparseSet::const_iterator
292 i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
293 dbgs() << ' ' << PrintRegUnit(*i, TRI);
294 dbgs() << " live before " << *I;
295 });
296 continue;
297 }
298
299 // This is a valid insertion point.
300 InsertionPoint = I;
301 DEBUG(dbgs() << "Can insert before " << *I);
302 return true;
303 }
304 DEBUG(dbgs() << "No legal insertion point found.\n");
305 return false;
306 }
307
308
309
310 /// canConvertIf - analyze the sub-cfg rooted in MBB, and return true if it is
311 /// a potential candidate for if-conversion. Fill out the internal state.
312 ///
313 bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
314 Head = MBB;
315 TBB = FBB = Tail = 0;
316
317 if (Head->succ_size() != 2)
318 return false;
319 MachineBasicBlock *Succ0 = Head->succ_begin()[0];
320 MachineBasicBlock *Succ1 = Head->succ_begin()[1];
321
322 // Canonicalize so Succ0 has MBB as its single predecessor.
323 if (Succ0->pred_size() != 1)
324 std::swap(Succ0, Succ1);
325
326 if (Succ0->pred_size() != 1 || Succ0->succ_size() != 1)
327 return false;
328
329 // We could support additional Tail predecessors by updating phis instead of
330 // eliminating them. Let's see an example where it matters first.
331 Tail = Succ0->succ_begin()[0];
332 if (Tail->pred_size() != 2)
333 return false;
334
335 // This is not a triangle.
336 if (Tail != Succ1) {
337 // Check for a diamond. We won't deal with any critical edges.
338 if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
339 Succ1->succ_begin()[0] != Tail)
340 return false;
341 DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
342 << " -> BB#" << Succ0->getNumber()
343 << "/BB#" << Succ1->getNumber()
344 << " -> BB#" << Tail->getNumber() << '\n');
345
346 // Live-in physregs are tricky to get right when speculating code.
347 if (!Tail->livein_empty()) {
348 DEBUG(dbgs() << "Tail has live-ins.\n");
349 return false;
350 }
351 } else {
352 DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
353 << " -> BB#" << Succ0->getNumber()
354 << " -> BB#" << Tail->getNumber() << '\n');
355 }
356
357 // This is a triangle or a diamond.
358 // If Tail doesn't have any phis, there must be side effects.
359 if (Tail->empty() || !Tail->front().isPHI()) {
360 DEBUG(dbgs() << "No phis in tail.\n");
361 return false;
362 }
363
364 // The branch we're looking to eliminate must be analyzable.
365 Cond.clear();
366 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
367 DEBUG(dbgs() << "Branch not analyzable.\n");
368 return false;
369 }
370
371 // This is weird, probably some sort of degenerate CFG.
372 if (!TBB) {
373 DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
374 return false;
375 }
376
377 // AnalyzeBranch doesn't set FBB on a fall-through branch.
378 // Make sure it is always set.
379 FBB = TBB == Succ0 ? Succ1 : Succ0;
380
381 // Any phis in the tail block must be convertible to selects.
382 PHIs.clear();
383 MachineBasicBlock *TPred = TBB == Tail ? Head : TBB;
384 MachineBasicBlock *FPred = FBB == Tail ? Head : FBB;
385 for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();
386 I != E && I->isPHI(); ++I) {
387 PHIs.push_back(&*I);
388 PHIInfo &PI = PHIs.back();
389 // Find PHI operands corresponding to TPred and FPred.
390 for (unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
391 if (PI.PHI->getOperand(i+1).getMBB() == TPred)
392 PI.TReg = PI.PHI->getOperand(i).getReg();
393 if (PI.PHI->getOperand(i+1).getMBB() == FPred)
394 PI.FReg = PI.PHI->getOperand(i).getReg();
395 }
396 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
397 assert(TargetRegisterInfo::isVirtualRegister(PI.FReg) && "Bad PHI");
398
399 // Get target information.
400 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
401 PI.CondCycles, PI.TCycles, PI.FCycles)) {
402 DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
403 return false;
404 }
405 }
406
407 // Check that the conditional instructions can be speculated.
408 InsertAfter.clear();
409 ClobberedRegUnits.reset();
410 if (TBB != Tail && !canSpeculateInstrs(TBB))
411 return false;
412 if (FBB != Tail && !canSpeculateInstrs(FBB))
413 return false;
414
415 // Try to find a valid insertion point for the speculated instructions in the
416 // head basic block.
417 if (!findInsertionPoint())
418 return false;
419
420 return true;
421 }
422
423
424 static void eraseBlock(BlockSetVector &WorkList, MachineBasicBlock *MBB) {
425 WorkList.remove(MBB);
426 MBB->eraseFromParent();
427 }
428
429
430 /// convertIf - Execute the if conversion after canConvertIf has determined the
431 /// feasibility.
432 ///
433 /// Any basic blocks erased will also be removed from WorkList.
434 ///
435 void SSAIfConv::convertIf(BlockSetVector &WorkList) {
436 assert(Head && Tail && TBB && FBB && "Call canConvertIf first.");
437
438 // Move all instructions into Head, except for the terminators.
439 if (TBB != Tail)
440 Head->splice(InsertionPoint, TBB, TBB->begin(), TBB->getFirstTerminator());
441 if (FBB != Tail)
442 Head->splice(InsertionPoint, FBB, FBB->begin(), FBB->getFirstTerminator());
443
444 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
445 assert(FirstTerm != Head->end() && "No terminators");
446 DebugLoc HeadDL = FirstTerm->getDebugLoc();
447
448 // Convert all PHIs to select instructions inserted before FirstTerm.
449 for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
450 PHIInfo &PI = PHIs[i];
451 DEBUG(dbgs() << "If-converting " << *PI.PHI);
452 assert(PI.PHI->getNumOperands() == 5 && "Unexpected PHI operands.");
453 unsigned DstReg = PI.PHI->getOperand(0).getReg();
454 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
455 DEBUG(dbgs() << " --> " << *llvm::prior(FirstTerm));
456 PI.PHI->eraseFromParent();
457 PI.PHI = 0;
458 }
459
460 // Fix up the CFG, temporarily leave Head without any successors.
461 Head->removeSuccessor(TBB);
462 Head->removeSuccessor(FBB);
463 if (TBB != Tail)
464 TBB->removeSuccessor(Tail);
465 if (FBB != Tail)
466 FBB->removeSuccessor(Tail);
467
468 // Fix up Head's terminators.
469 // It should become a single branch or a fallthrough.
470 TII->RemoveBranch(*Head);
471
472 // Erase the now empty conditional blocks. It is likely that Head can fall
473 // through to Tail, and we can join the two blocks.
474 if (TBB != Tail)
475 eraseBlock(WorkList, TBB);
476 if (FBB != Tail)
477 eraseBlock(WorkList, FBB);
478
479 assert(Head->succ_empty() && "Additional head successors?");
480 if (Head->isLayoutSuccessor(Tail)) {
481 // Splice Tail onto the end of Head.
482 DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
483 << " into head BB#" << Head->getNumber() << '\n');
484 Head->splice(Head->end(), Tail,
485 Tail->begin(), Tail->end());
486 Head->transferSuccessorsAndUpdatePHIs(Tail);
487 eraseBlock(WorkList, Tail);
488
489 } else {
490 // We need a branch to Tail, let code placement work it out later.
491 DEBUG(dbgs() << "Converting to unconditional branch.\n");
492 SmallVector EmptyCond;
493 TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL);
494 Head->addSuccessor(Tail);
495 }
496 DEBUG(dbgs() << *Head);
497 }
498
499
500 //===----------------------------------------------------------------------===//
501 // EarlyIfConverter Pass
502 //===----------------------------------------------------------------------===//
503
504 namespace {
505 class EarlyIfConverter : public MachineFunctionPass {
506 const TargetInstrInfo *TII;
507 const TargetRegisterInfo *TRI;
508 MachineRegisterInfo *MRI;
509 SSAIfConv IfConv;
510
511 // Worklist of head blocks to try for if-conversion.
512 BlockSetVector WorkList;
513
514 public:
515 static char ID;
516 EarlyIfConverter() : MachineFunctionPass(ID) {}
517 void getAnalysisUsage(AnalysisUsage &AU) const;
518 bool runOnMachineFunction(MachineFunction &MF);
519
520 private:
521 bool tryConvertIf(MachineBasicBlock*);
522 };
523 } // end anonymous namespace
524
525 char EarlyIfConverter::ID = 0;
526 char &llvm::EarlyIfConverterID = EarlyIfConverter::ID;
527
528 INITIALIZE_PASS_BEGIN(EarlyIfConverter,
529 "early-ifcvt", "Early If Converter", false, false)
530 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
531 INITIALIZE_PASS_END(EarlyIfConverter,
532 "early-ifcvt", "Early If Converter", false, false)
533
534 void EarlyIfConverter::getAnalysisUsage(AnalysisUsage &AU) const {
535 AU.addRequired();
536 MachineFunctionPass::getAnalysisUsage(AU);
537 }
538
539 /// Attempt repeated if-conversion on MBB, return true if successful.
540 /// Update WorkList with new opportunities.
541 ///
542 bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
543 if (!IfConv.canConvertIf(MBB))
544 return false;
545
546 // Repeatedly if-convert MBB, joining Head and Tail may expose more
547 // opportunities.
548 do IfConv.convertIf(WorkList);
549 while (IfConv.canConvertIf(MBB));
550
551 // It is possible that MBB is now itself a conditional block that can be
552 // if-converted.
553 if (MBB->pred_size() == 1 && MBB->succ_size() == 1)
554 WorkList.insert(MBB->pred_begin()[0]);
555 WorkList.remove(MBB);
556 return true;
557 }
558
559
560 bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
561 DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
562 << "********** Function: "
563 << ((Value*)MF.getFunction())->getName() << '\n');
564 TII = MF.getTarget().getInstrInfo();
565 TRI = MF.getTarget().getRegisterInfo();
566 MRI = &MF.getRegInfo();
567
568 bool Changed = false;
569 IfConv.runOnMachineFunction(MF);
570
571 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
572 ++MFI)
573 if (tryConvertIf(MFI))
574 Changed = true;
575
576 DEBUG(dbgs() << "Revisiting " << WorkList.size() << " blocks.\n");
577 while (!WorkList.empty())
578 tryConvertIf(WorkList.pop_back_val());
579
580 MF.verify(this, "After early if-conversion");
581 return Changed;
582 }
4848 cl::desc("Disable Stack Slot Coloring"));
4949 static cl::opt DisableMachineDCE("disable-machine-dce", cl::Hidden,
5050 cl::desc("Disable Machine Dead Code Elimination"));
51 static cl::opt EnableEarlyIfConversion("enable-early-ifcvt", cl::Hidden,
52 cl::desc("Enable Early If-conversion"));
5153 static cl::opt DisableMachineLICM("disable-machine-licm", cl::Hidden,
5254 cl::desc("Disable Machine LICM"));
5355 static cl::opt DisableMachineCSE("disable-machine-cse", cl::Hidden,
153155 if (StandardID == &DeadMachineInstructionElimID)
154156 return applyDisable(TargetID, DisableMachineDCE);
155157
158 if (StandardID == &EarlyIfConverterID)
159 return applyDisable(TargetID, !EnableEarlyIfConversion);
160
156161 if (StandardID == &MachineLICMID)
157162 return applyDisable(TargetID, DisableMachineLICM);
158163
226231 // Substitute Pseudo Pass IDs for real ones.
227232 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
228233 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
234
235 // Disable early if-conversion. Targets that are ready can enable it.
236 disablePass(&EarlyIfConverterID);
229237
230238 // Temporarily disable experimental passes.
231239 substitutePass(&MachineSchedulerID, 0);
526534 addPass(&DeadMachineInstructionElimID);
527535 printAndVerify("After codegen DCE pass");
528536
537 addPass(&EarlyIfConverterID);
529538 addPass(&MachineLICMID);
530539 addPass(&MachineCSEID);
531540 addPass(&MachineSinkingID);