llvm.org GIT mirror llvm / 32bd5f4
initial implementation of addressing mode 5 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31002 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 13 years ago
4 changed file(s) with 63 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
5454 }
5555
5656 void printAddrMode1(const MachineInstr *MI, int opNum);
57 void printAddrMode5(const MachineInstr *MI, int opNum);
5758
5859 void printMemRegImm(const MachineInstr *MI, int opNum,
5960 const char *Modifier = NULL) {
192193 }
193194 }
194195
196 void ARMAsmPrinter::printAddrMode5(const MachineInstr *MI, int opNum) {
197 const MachineOperand &Arg = MI->getOperand(opNum);
198 const MachineOperand &Offset = MI->getOperand(opNum + 1);
199 assert(Offset.isImmediate());
200
201 if (Arg.isConstantPoolIndex()) {
202 assert(Offset.getImmedValue() == 0);
203 printOperand(MI, opNum);
204 } else {
205 assert(Arg.isRegister());
206 O << '[';
207 printOperand(MI, opNum);
208 O << ", ";
209 printOperand(MI, opNum + 1);
210 O << ']';
211 }
212 }
213
195214 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
196215 const MachineOperand &MO = MI->getOperand (opNum);
197216 const MRegisterInfo &RI = *TM.getRegisterInfo();
736736 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
737737 bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
738738 SDOperand &ShiftType);
739 bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset);
739740
740741 // Include the pieces autogenerated from the target description.
741742 #include "ARMGenDAGISel.inc"
834835 return true;
835836 }
836837
838 bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg,
839 SDOperand &Offset) {
840 //TODO: detect offset
841 Offset = CurDAG->getTargetConstant(0, MVT::i32);
842 Arg = N;
843 return true;
844 }
845
837846 //register plus/minus 12 bit offset
838847 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
839848 SDOperand &Base) {
1818 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
1919 }
2020
21 def op_addr_mode5 : Operand {
22 let PrintMethod = "printAddrMode5";
23 let NumMIOperands = 2;
24 let MIOperandInfo = (ops ptr_rc, i32imm);
25 }
26
2127 def memri : Operand {
2228 let PrintMethod = "printMemRegImm";
2329 let NumMIOperands = 2;
2834 //Addressing Mode 1: data processing operands
2935 def addr_mode1 : ComplexPattern
3036 []>;
37
38 //Addressing Mode 5: VFP load/store
39 def addr_mode5 : ComplexPattern;
3140
3241 //register plus/minus 12 bit offset
3342 def iaddr : ComplexPattern;
284293 def FDIVD : DFPBinOp<"fdivd", fdiv>;
285294
286295 // Floating Point Load
287 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
288 "flds $dst, [$addr]",
289 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
290
291 def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
292 "fldd $dst, [$addr]",
293 [(set DFPRegs:$dst, (load IntRegs:$addr))]>;
296 def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
297 "flds $dst, $addr",
298 [(set FPRegs:$dst, (load addr_mode5:$addr))]>;
299
300 def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
301 "fldd $dst, $addr",
302 [(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
294303
295304 // Floating Point Store
296 def FSTS : InstARM<(ops FPRegs:$src, IntRegs:$addr),
305 def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
297306 "fsts $src, [$addr]",
298 [(store FPRegs:$src, IntRegs:$addr)]>;
299
300 def FSTD : InstARM<(ops DFPRegs:$src, IntRegs:$addr),
307 [(store FPRegs:$src, addr_mode5:$addr)]>;
308
309 def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
301310 "fstd $src, [$addr]",
302 [(store DFPRegs:$src, IntRegs:$addr)]>;
311 [(store DFPRegs:$src, addr_mode5:$addr)]>;
303312
304313 def : Pat<(ARMcall tglobaladdr:$dst),
305314 (bl tglobaladdr:$dst)>;
0 ; RUN: llvm-as < %s | llc -march=arm &&
1 ; RUN: llvm-as < %s | llc -march=arm | grep flds | wc -l | grep 2 &&
2 ; RUN: llvm-as < %s | llc -march=arm | grep "flds.*\[" | wc -l | grep 1
3
4 float %g(float %a) {
5 entry:
6 ret float 0.000000e+00
7 }
8
9 float %g(float* %v) {
10 entry:
11 %tmp = load float* %v
12 ret float %tmp
13 }