llvm.org GIT mirror llvm / 32a1b25
2 more vdup.32 cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 11 years ago
3 changed file(s) with 34 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
17681768 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
17691769 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
17701770
1771 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1772 (outs DPR:$dst), (ins SPR:$src),
1773 "vdup.32\t$dst, ${src:lane}", "",
1774 [(set DPR:$dst, (v2f32 (splat_lo
1775 (scalar_to_vector SPR:$src),
1776 undef)))]>;
1777
1778 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1779 (outs QPR:$dst), (ins SPR:$src),
1780 "vdup.32\t$dst, ${src:lane}", "",
1781 [(set QPR:$dst, (v4f32 (splat_lo
1782 (scalar_to_vector SPR:$src),
1783 undef)))]>;
1784
17711785 // VMOVN : Vector Narrowing Move
17721786 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
17731787 int_arm_neon_vmovn>;
344344 O << '{'
345345 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
346346 << '}';
347 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
348 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
349 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
350 &ARM::DPRRegClass);
351 O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
347352 } else {
348353 O << TRI->getAsmName(Reg);
349354 }
0 ; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
11 ; RUN: grep vdup.8 %t | count 4
22 ; RUN: grep vdup.16 %t | count 4
3 ; RUN: grep vdup.32 %t | count 8
3 ; RUN: grep vdup.32 %t | count 10
44
55 define <8 x i8> @v_dup8(i8 %A) nounwind {
66 %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
131131 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
132132 ret <4 x float> %tmp2
133133 }
134
135 define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
136 %tmp0 = load float* %A
137 %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
138 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
139 ret <2 x float> %tmp2
140 }
141
142 define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind {
143 %tmp0 = load float* %A
144 %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
145 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
146 ret <4 x float> %tmp2
147 }