llvm.org GIT mirror llvm / 31f94c7
- Make the machine cse dumb coalescer (as opposed to the more awesome simple coalescer) handle sub-register classes. - Add heuristics to avoid non-profitable cse. Given the current lack of live range splitting, avoid cse when an expression has PHI use and the would be new use is in a BB where the expression wasn't already being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98043 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
2 changed file(s) with 59 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
327327 PM.add(createOptimizeExtsPass());
328328 if (!DisableMachineLICM)
329329 PM.add(createMachineLICMPass());
330 if (EnableMachineCSE)
330 //if (EnableMachineCSE)
331331 PM.add(createMachineCSEPass());
332332 if (!DisableMachineSink)
333333 PM.add(createMachineSinkingPass());
334 printAndVerify(PM, "After MachineLICM and MachineSinking",
334 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
335335 /* allowDoubleDefs= */ true);
336336 }
337337
3232 class MachineCSE : public MachineFunctionPass {
3333 const TargetInstrInfo *TII;
3434 const TargetRegisterInfo *TRI;
35 MachineRegisterInfo *MRI;
35 AliasAnalysis *AA;
3636 MachineDominatorTree *DT;
37 AliasAnalysis *AA;
37 MachineRegisterInfo *MRI;
3838 public:
3939 static char ID; // Pass identification
4040 MachineCSE() : MachineFunctionPass(&ID), CurrVN(0) {}
6060 MachineBasicBlock::const_iterator E);
6161 bool hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB);
6262 bool isCSECandidate(MachineInstr *MI);
63 bool isProfitableToCSE(unsigned Reg, MachineInstr *MI);
6364 bool ProcessBlock(MachineDomTreeNode *Node);
6465 };
6566 } // end anonymous namespace
9091 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
9192 if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
9293 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
93 MRI->getRegClass(SrcReg) == MRI->getRegClass(Reg) &&
9494 !SrcSubIdx && !DstSubIdx) {
95 DEBUG(dbgs() << "Coalescing: " << *DefMI);
96 DEBUG(dbgs() << "*** to: " << *MI);
97 MO.setReg(SrcReg);
98 DefMI->eraseFromParent();
99 ++NumCoalesces;
100 Changed = true;
95 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
96 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
97 if (SRC == RC || SRC->hasSubClass(RC) || RC->hasSubClass(SRC)) {
98 DEBUG(dbgs() << "Coalescing: " << *DefMI);
99 DEBUG(dbgs() << "*** to: " << *MI);
100 MO.setReg(SrcReg);
101 DefMI->eraseFromParent();
102 ++NumCoalesces;
103 Changed = true;
104 }
101105 }
102106 }
103107
200204 return true;
201205 }
202206
207 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
208 /// common expression that defines Reg.
209 bool MachineCSE::isProfitableToCSE(unsigned Reg, MachineInstr *MI) {
210 // FIXME: This "heuristic" works around the lack the live range splitting.
211 // If the common subexpression is used by PHIs, do not reuse it unless the
212 // defined value is already used in the BB of the new use.
213 bool HasPHI = false;
214 SmallPtrSet CSBBs;
215 for (MachineRegisterInfo::use_nodbg_iterator I =
216 MRI->use_nodbg_begin(Reg),
217 E = MRI->use_nodbg_end(); I != E; ++I) {
218 MachineInstr *Use = &*I;
219 HasPHI |= Use->isPHI();
220 CSBBs.insert(Use->getParent());
221 }
222
223 if (!HasPHI)
224 return true;
225 return CSBBs.count(MI->getParent());
226 }
227
203228 bool MachineCSE::ProcessBlock(MachineDomTreeNode *Node) {
204229 bool Changed = false;
205230
231 SmallVector, 8> CSEPairs;
206232 ScopedHashTableScope
207233 MachineInstrExpressionTrait> VNTS(VNT);
208234 MachineBasicBlock *MBB = Node->getBlock();
237263 MachineInstr *CSMI = Exps[CSVN];
238264 DEBUG(dbgs() << "Examining: " << *MI);
239265 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
266
267 // Check if it's profitable to perform this CSE.
268 bool DoCSE = true;
240269 unsigned NumDefs = MI->getDesc().getNumDefs();
241270 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
242271 MachineOperand &MO = MI->getOperand(i);
249278 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
250279 TargetRegisterInfo::isVirtualRegister(NewReg) &&
251280 "Do not CSE physical register defs!");
252 MRI->replaceRegWith(OldReg, NewReg);
281 if (!isProfitableToCSE(NewReg, MI)) {
282 DoCSE = false;
283 break;
284 }
285 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
253286 --NumDefs;
254287 }
255 MI->eraseFromParent();
256 ++NumCSEs;
288
289 // Actually perform the elimination.
290 if (DoCSE) {
291 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i)
292 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
293 MI->eraseFromParent();
294 ++NumCSEs;
295 } else {
296 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
297 VNT.insert(MI, CurrVN++);
298 Exps.push_back(MI);
299 }
300 CSEPairs.clear();
257301 }
258302
259303 // Recursively call ProcessBlock with childred.
268312 TII = MF.getTarget().getInstrInfo();
269313 TRI = MF.getTarget().getRegisterInfo();
270314 MRI = &MF.getRegInfo();
315 AA = &getAnalysis();
271316 DT = &getAnalysis();
272 AA = &getAnalysis();
273317 return ProcessBlock(DT->getRootNode());
274318 }