llvm.org GIT mirror llvm / 31d157a
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8 Jia Liu 7 years ago
293 changed file(s) with 387 addition(s) and 386 deletion(s). Raw diff Collapse all Expand all
None //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
0 //===-- ARM.h - Top-level interface for ARM representation-------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
0 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMAsmPrinter.h - Print machine code to an ARM .s file ------------===//
0 //===-- ARMAsmPrinter.h - Print machine code to an ARM .s file --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
0 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
0 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
0 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
0 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-------- ARMBuildAttrs.h - ARM Build Attributes ------------*- C++ -*-===//
0 //===-- ARMBuildAttrs.h - ARM Build Attributes ------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMCallingConv.h - ARM Custom Calling Convention Routines ---------===//
0 //=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMCallingConv.td - Calling Conventions for ARM -----*- tablegen -*-===//
0 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMConstantPoolValue.cpp - ARM constantpool value --------*- C++ -*-===//
0 //===-- ARMConstantPoolValue.cpp - ARM constantpool value -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMConstantPoolValue.h - ARM constantpool value ----------*- C++ -*-===//
0 //===-- ARMConstantPoolValue.h - ARM constantpool value ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
0 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
0 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
0 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
0 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
0 //===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
0 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
0 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
0 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
0 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMJITInfo.h - ARM implementation of the JIT interface --*- C++ -*-===//
0 //===-- ARMJITInfo.h - ARM implementation of the JIT interface -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
0 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- ARMMachineFuctionInfo.cpp - ARM machine function info ---*- C++ -*-===//
0 //===-- ARMMachineFuctionInfo.cpp - ARM machine function info -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
0 //===-- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table ------------------===//
0 //===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
0 //===-- ARMRegisterInfo.cpp - ARM Register Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
0 //===-- ARMRegisterInfo.h - ARM Register Information Impl -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
0 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMRelocations.h - ARM Code Relocations ------------------*- C++ -*-===//
0 //===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
1 //
0 //===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
1 //
0 //===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the itinerary class data for the ARM v6 processors.
None //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
0 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
0 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
0 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax ----------===//
0 //===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
0 //===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMMCAsmInfo.cpp - ARM asm properties -------------------*- C++ -*-===//
0 //===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- ARMMCAsmInfo.h - ARM asm properties -------------*- C++ -*--====//
0 //===-- ARMMCAsmInfo.h - ARM asm properties --------------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===//
0 //===-- ARMMCExpr.h - ARM specific MC expression classes --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
0 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ----------=//
0 //===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ---------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
0 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
0 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ------*- C++ -*-===//
0 //===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
0 //===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
0 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
0 //===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
0 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information ----*- C++ -*-===//
0 //===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
0 //===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
None //===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
0 //===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- SPU.h - Top-level interface for Cell SPU Target ----------*- C++ -*-==//
0 //===-- SPU.h - Top-level interface for Cell SPU Target ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
1 //
0 //===-- SPU.td - Describe the STI Cell SPU Target Machine --*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
None //===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
0 //===-- SPU128InstrInfo.td - Cell SPU 128-bit operations --*- tablegen -*--===//
11 //
22 // Cell SPU 128-bit operations
33 //
44 //===----------------------------------------------------------------------===//
5
5
66 // zext 32->128: Zero extend 32-bit to 128-bit
77 def : Pat<(i128 (zext R32C:$rSrc)),
88 (ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
None //====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
0 //====-- SPU64InstrInfo.td - Cell SPU 64-bit operations ---*- tablegen -*--===//
11 //
22 // Cell SPU 64-bit operations
33 //
None //===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -------=//
0 //===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -----===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
0 //===- SPUCallingConv.td - Calling Conventions for CellSPU -*- tablegen -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This describes the calling conventions for the STI Cell SPU architecture.
None //=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========//
0 //===-- SPUFrameLowering.h - SPU Frame Lowering stuff ----------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- SPUInstrBuilder.h - Aides for building Cell SPU insts -----*- C++ -*-==//
0 //===-- SPUInstrBuilder.h - Aides for building Cell SPU insts ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
1 //
0 //===-- SPUInstrFormats.td - Cell SPU Instruction Formats --*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
0 //===-- SPUInstrInfo.cpp - Cell SPU Instruction Information ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
0 //===-- SPUInstrInfo.h - Cell SPU Instruction Information -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU -*- C++ -*-=//
0 //==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU ---------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //======--- SPUMathInst.td - Cell SPU math operations -*- tablegen -*---======//
0 //===-- SPUMathInst.td - Cell SPU math operations ---------*- tablegen -*--===//
11 //
22 // Cell SPU math operations
33 //
None //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
0 //=== SPUNodes.td - Specialized SelectionDAG nodes by CellSPU -*- tablegen -*-//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines---===//
0 //===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines ----------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
1 //
0 //===-- SPUOperands.td - Cell SPU Instruction Operands -----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 // Cell SPU Instruction Operands:
99 //===----------------------------------------------------------------------===//
None //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
0 //===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
0 //===-- SPURegisterInfo.h - Cell SPU Register Information Impl --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===//
1 //
0 //===-- SPURegisterInfo.td - The Cell SPU Register File ----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 //
None //===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
1 //
0 //===-- SPUSchedule.td - Cell Scheduling Definitions -------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
0 //===-- SPUSubtarget.cpp - STI Cell SPU Subtarget Information -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU ----*- C++ -*-=//
0 //===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Hexagon.td - Describe the Hexagon Target Machine ---------*- C++ -*-===//
0 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This is the top level entry point for the Hexagon target.
910 //
1011 //===----------------------------------------------------------------------===//
1112
1718
1819 //===----------------------------------------------------------------------===//
1920 // Hexagon Subtarget features.
20 //
21
21 //===----------------------------------------------------------------------===//
2222
2323 // Hexagon Archtectures
2424 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
None //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ----=//
0 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===---- HexagonCFGOptimizer.cpp - CFG optimizations ---------------------===//
0 //===-- HexagonCFGOptimizer.cpp - CFG optimizations -----------------------===//
11 // The LLVM Compiler Infrastructure
22 //
33 // This file is distributed under the University of Illinois Open Source
None //===- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code -------===//
0 //===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===----------------------------------------------------------------------===////
7 //===----------------------------------------------------------------------===//
88 // The Hexagon processor has no instructions that load or store predicate
99 // registers directly. So, when these registers must be spilled a general
1010 // purpose register must be found and the value copied to/from it from/to
None //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
0 //===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon ----==//
0 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- HexagonISelLowering.h - Hexagon DAG Lowering Interface ----*- C++ -*-==//
0 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=- HexagonImmediates.td - Hexagon immediate processing --*- tablegen -*-=//
0 //===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88
9 //----------------------------------------------------------------------------//
9 //===----------------------------------------------------------------------===//
1010 // Hexagon Intruction Flags +
1111 //
1212 // *** Must match HexagonBaseInfo.h ***
13 //----------------------------------------------------------------------------//
14
15
16 //----------------------------------------------------------------------------//
13 //===----------------------------------------------------------------------===//
14
15
16 //===----------------------------------------------------------------------===//
1717 // Intruction Class Declaration +
18 //----------------------------------------------------------------------------//
18 //===----------------------------------------------------------------------===//
1919
2020 class InstHexagon pattern,
2121 string cstr, InstrItinClass itin> : Instruction {
3939 // *** The code above must match HexagonBaseInfo.h ***
4040 }
4141
42 //----------------------------------------------------------------------------//
42 //===----------------------------------------------------------------------===//
4343 // Intruction Classes Definitions +
44 //----------------------------------------------------------------------------//
44 //===----------------------------------------------------------------------===//
4545
4646 // LD Instruction Class in V2/V3/V4.
4747 // Definition of the instruction class NOT CHANGED.
187187 : InstHexagon;
188188
189189
190 //----------------------------------------------------------------------------//
190 //===----------------------------------------------------------------------===//
191191 // Intruction Classes Definitions -
192 //----------------------------------------------------------------------------//
192 //===----------------------------------------------------------------------===//
193193
194194
195195 //
None //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
0 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=//
0 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- HexagonIntrinsics.td - Instruction intrinsics -------*- tablegen -*-===//
0 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- HexagonRegisterInfo.cpp - Hexagon Register Information -------------===//
0 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- HexagonRegisterInfo.td - Hexagon Register defs ------*- tablegen -*-===//
0 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-HexagonSchedule.td - Hexagon Scheduling Definitions -------*- C++ -*-===//
0 //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=-HexagoSelectCCInfo.td - Selectcc mappings ----------------*- tablegen -*-=//
0 //===-- HexagoSelectCCInfo.td - Selectcc mappings ----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ------*- C++ -*-=//
0 //===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===---- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -----===//
0 //===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // License. See LICENSE.TXT for details.
66 //
77 //
8 //===----------------------------------------------------------------------===////
8 //===----------------------------------------------------------------------===//
99 // This pass tries to provide opportunities for better optimization of muxes.
1010 // The default code generated for something like: flag = (a == b) ? 1 : 3;
1111 // would be:
None //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
0 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-==//
0 //===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon --------===//
0 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // Implements the info about Hexagon target spec.
910 //
1011 //===----------------------------------------------------------------------===//
1112
None //===-- HexagonTargetObjectFile.cpp - Hexagon asm properties ----*- C++ -*-===//
0 //===-- HexagonTargetObjectFile.cpp - Hexagon asm properties --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==//
0 //===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- HexagonVarargsCallingConvention.h - Calling Conventions ---*- C++ -*-==//
0 //===-- HexagonVarargsCallingConvention.h - Calling Conventions -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- HexagonBaseInfo.h - Top level definitions for Hexagon -------------===//
0 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- HexagonMCAsmInfo.cpp - Hexagon asm properties -----------*- C++ -*-===//
0 //===-- HexagonMCAsmInfo.cpp - Hexagon asm properties ---------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==//
0 //===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- HexagonMCTargetDesc.cpp - Cell Hexagon Target Descriptions -----*- C++ -*-===//
0 //===-- HexagonMCTargetDesc.cpp - Cell Hexagon Target Descriptions --------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeDisassembler.cpp - Disassembler for MicroBlaze ----*- C++ -*-===//
0 //===-- MBlazeDisassembler.cpp - Disassembler for MicroBlaze -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeDisassembler.h - Disassembler for MicroBlaze ------*- C++ -*-===//
0 //===-- MBlazeDisassembler.h - Disassembler for MicroBlaze -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeInstPrinter.h - Convert MBlaze MCInst to assembly syntax ----===//
0 //= MBlazeInstPrinter.h - Convert MBlaze MCInst to assembly syntax -*- C++ -*-//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlaze.td - Describe the MBlaze Target Machine ------*- tablegen -*-===//
0 //===-- MBlaze.td - Describe the MBlaze Target Machine -----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeFrameLowering.cpp - MBlaze Frame Information ------*- C++ -*-====//
0 //===-- MBlazeFrameLowering.cpp - MBlaze Frame Information ---------------====//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===//
0 //===-- MBlazeInstrFPU.td - MBlaze FPU Instruction defs ----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrFSL.td - MBlaze FSL Instruction defs -----*- tablegen -*-===//
0 //===-- MBlazeInstrFSL.td - MBlaze FSL Instruction defs ----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrFormats.td - MB Instruction defs ---------*- tablegen -*-===//
0 //===-- MBlazeInstrFormats.td - MB Instruction defs --------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrInfo.cpp - MBlaze Instruction Information -----*- C++ -*-===//
0 //===-- MBlazeInstrInfo.cpp - MBlaze Instruction Information --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrInfo.h - MBlaze Instruction Information -------*- C++ -*-===//
0 //===-- MBlazeInstrInfo.h - MBlaze Instruction Information ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
0 //===-- MBlazeInstrInfo.td - MBlaze Instruction defs -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeIntrinsicInfo.cpp - Intrinsic Information -00-------*- C++ -*-===//
0 //===-- MBlazeIntrinsicInfo.cpp - Intrinsic Information -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeIntrinsicInfo.h - MBlaze Intrinsic Information -----*- C++ -*-===//
0 //===-- MBlazeIntrinsicInfo.h - MBlaze Intrinsic Information ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- IntrinsicsMBlaze.td - Defines MBlaze intrinsics -----*- tablegen -*-===//
0 //===-- IntrinsicsMBlaze.td - Defines MBlaze intrinsics ----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeMCInstLower.h - Lower MachineInstr to MCInst ----------------===//
0 //===-- MBlazeMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeMachineFunctionInfo.cpp - Private data --------------*- C++ -*-=//
0 //===-- MBlazeMachineFunctionInfo.cpp - Private data ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeMachineFunctionInfo.h - Private data ----------------*- C++ -*-=//
0 //===-- MBlazeMachineFunctionInfo.h - Private data --------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===//
0 //===-- MBlazeRegisterInfo.cpp - MBlaze Register Information --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeRegisterInfo.h - MBlaze Register Information Impl --*- C++ -*-===//
0 //===-- MBlazeRegisterInfo.h - MBlaze Register Information Impl -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeRegisterInfo.td - MBlaze Register defs --------*- tablegen -*-===//
0 //===-- MBlazeRegisterInfo.td - MBlaze Register defs -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeRelocations.h - MBlaze Code Relocations ------------*- C++ -*-===//
0 //===-- MBlazeRelocations.h - MBlaze Code Relocations -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeSchedule.td - MBlaze Scheduling Definitions ---*- tablegen -*-===//
0 //===-- MBlazeSchedule.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeSchedule3.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
0 //===-- MBlazeSchedule3.td - MBlaze Scheduling Definitions -*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeSchedule5.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
0 //===-- MBlazeSchedule5.td - MBlaze Scheduling Definitions -*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MBlazeSubtarget.cpp - MBlaze Subtarget Information -------*- C++ -*-===//
0 //===-- MBlazeSubtarget.cpp - MBlaze Subtarget Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- MBlazeSubtarget.h - Define Subtarget for the MBlaze -*- C++ -*--====//
0 //===-- MBlazeSubtarget.h - Define Subtarget for the MBlaze ----*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeTargetMachine.h - Define TargetMachine for MBlaze --- C++ ---===//
0 //===-- MBlazeTargetMachine.h - Define TargetMachine for MBlaze -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- MBlazeMCAsmInfo.h - MBlaze asm properties -----------*- C++ -*--====//
0 //===-- MBlazeMCAsmInfo.h - MBlaze asm properties --------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MBlazeMCTargetDesc.cpp - MBlaze Target Descriptions -----*- C++ -*-===//
0 //===-- MBlazeMCTargetDesc.cpp - MBlaze Target Descriptions ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MSP430InstPrinter.h - Convert MSP430 MCInst to assembly syntax ----===//
0 //= MSP430InstPrinter.h - Convert MSP430 MCInst to assembly syntax -*- C++ -*-//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- MSP430MCAsmInfo.h - MSP430 asm properties -----------*- C++ -*--====//
0 //===-- MSP430MCAsmInfo.h - MSP430 asm properties --------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions -----*- C++ -*-===//
0 //===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions ---------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430.td - Describe the MSP430 Target Machine ---------*- tblgen -*-==//
0 //===-- MSP430.td - Describe the MSP430 Target Machine -----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MSP430BranchSelector.cpp - Emit long conditional branches--*- C++ -*-=//
0 //===-- MSP430BranchSelector.cpp - Emit long conditional branches ---------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //======-- MSP430FrameLowering.cpp - MSP430 Frame Information -------=========//
0 //===-- MSP430FrameLowering.cpp - MSP430 Frame Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
0 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430InstrFormats.td - MSP430 Instruction Formats-----*- tblgen -*-===//
0 //===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
0 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430InstrInfo.h - MSP430 Instruction Information -------*- C++ -*-===//
0 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
0 //===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MSP430MCInstLower.cpp - Convert MSP430 MachineInstr to an MCInst---===//
0 //===-- MSP430MCInstLower.cpp - Convert MSP430 MachineInstr to an MCInst --===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- MSP430MCInstLower.h - Lower MachineInstr to MCInst ----------------===//
0 //===-- MSP430MCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==- MSP430MachineFuctionInfo.cpp - MSP430 machine function info -*- C++ -*-=//
0 //===-- MSP430MachineFuctionInfo.cpp - MSP430 machine function info -------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
0 //===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430RegisterInfo.h - MSP430 Register Information Impl --*- C++ -*-===//
0 //===-- MSP430RegisterInfo.h - MSP430 Register Information Impl -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
0 //===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- MSP430Subtarget.cpp - MSP430 Subtarget Information ---------*- C++ -*-=//
0 //===-- MSP430Subtarget.cpp - MSP430 Subtarget Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====-- MSP430Subtarget.h - Define Subtarget for the MSP430 ---*- C++ -*--===//
0 //===-- MSP430Subtarget.h - Define Subtarget for the MSP430 ----*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- MSP430TargetMachine.h - Define TargetMachine for MSP430 ---*- C++ -*-==//
0 //===-- MSP430TargetMachine.h - Define TargetMachine for MSP430 -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PTXInstPrinter.h - Convert PTX MCInst to assembly syntax ----------===//
0 //===- PTXInstPrinter.h - Convert PTX MCInst to assembly syntax -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- PTXMCAsmInfo.h - PTX asm properties -----------------*- C++ -*--====//
0 //===-- PTXMCAsmInfo.h - PTX asm properties --------------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PTXMCTargetDesc.cpp - PTX Target Descriptions -----------*- C++ -*-===//
0 //===-- PTXMCTargetDesc.cpp - PTX Target Descriptions ---------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTX.td - Describe the PTX Target Machine ---------------*- tblgen -*-==//
0 //===-- PTX.td - Describe the PTX Target Machine -----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PTXAsmPrinter.h - Print machine code to a PTX file ----------------===//
0 //===-- PTXAsmPrinter.h - Print machine code to a PTX file ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=======- PTXFrameLowering.cpp - PTX Frame Information -------*- C++ -*-=====//
0 //===-- PTXFrameLowering.cpp - PTX Frame Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===--- PTXFrameLowering.h - Define frame lowering for PTX --*- C++ -*----===//
0 //===-- PTXFrameLowering.h - Define frame lowering for PTX -----*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- PTXISelLowering.h - PTX DAG Lowering Interface ------------*- C++ -*-==//
0 //===-- PTXISelLowering.h - PTX DAG Lowering Interface ----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXInstrFormats.td - PTX Instruction Formats ----------*- tblgen -*-===//
0 //===-- PTXInstrFormats.td - PTX Instruction Formats -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXInstrInfo.cpp - PTX Instruction Information ---------------------===//
0 //===-- PTXInstrInfo.cpp - PTX Instruction Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXInstrInfo.h - PTX Instruction Information -------------*- C++ -*-===//
0 //===-- PTXInstrInfo.h - PTX Instruction Information ------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
0 //===-- PTXInstrInfo.td - PTX Instruction defs --------------*- tablegen-*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXInstrLoadStore.td - PTX Load/Store Instruction Defs -*- tblgen-*-===//
0 //===- PTXInstrLoadStore.td - PTX Load/Store Instruction Defs -*- tablegen-*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXIntrinsicInstrInfo.td - Defines PTX intrinsics ---*- tablegen -*-===//
0 //===-- PTXIntrinsicInstrInfo.td - Defines PTX intrinsics --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- lib/Target/PTX/PTXMCAsmStreamer.cpp - PTX Text Assembly Output -----===//
0 //===-- PTXMCAsmStreamer.cpp - PTX Text Assembly Output -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXMachineFuctionInfo.cpp - PTX machine function info -----*- C++ -*-==//
0 //===-- PTXMachineFuctionInfo.cpp - PTX machine function info -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXMachineFuctionInfo.h - PTX machine function info -------*- C++ -*-==//
0 //===-- PTXMachineFuctionInfo.h - PTX machine function info ------*- C++ -*-==//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXParamManager.cpp - Manager for .param variables -------*- C++ -*-===//
0 //===-- PTXParamManager.cpp - Manager for .param variables ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXParamManager.h - Manager for .param variables ----------*- C++ -*-==//
0 //===-- PTXParamManager.h - Manager for .param variables --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXRegisterInfo.cpp - PTX Register Information ---------------------===//
0 //===-- PTXRegisterInfo.cpp - PTX Register Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PTXRegisterInfo.h - PTX Register Information Impl --------*- C++ -*-===//
0 //===-- PTXRegisterInfo.h - PTX Register Information Impl -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None
1 //===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
0 //===-- PTXRegisterInfo.td - PTX Register defs -------------*- tablegen -*-===//
21 //
32 // The LLVM Compiler Infrastructure
43 //
None //===- PTXSubtarget.cpp - PTX Subtarget Information ---------------*- C++ -*-=//
0 //===-- PTXSubtarget.cpp - PTX Subtarget Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====-- PTXSubtarget.h - Define Subtarget for the PTX ---------*- C++ -*--===//
0 //===-- PTXSubtarget.h - Define Subtarget for the PTX -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax ----------===//
0 //===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCBaseInfo.h - Top level definitions for PPC -------- --*- C++ -*-===//
0 //===-- PPCBaseInfo.h - Top level definitions for PPC -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCMCAsmInfo.cpp - PPC asm properties -------------------*- C++ -*-===//
0 //===-- PPCMCAsmInfo.cpp - PPC asm properties -----------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- PPCMCAsmInfo.h - PPC asm properties -----------------*- C++ -*--====//
0 //===-- PPCMCAsmInfo.h - PPC asm properties --------------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -------*- C++ -*-===//
0 //===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
1 //
0 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This is the top level entry point for the PowerPC target.
None //===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --------=//
0 //===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly ------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCBranchSelector.cpp - Emit long conditional branches-----*- C++ -*-=//
0 //===-- PPCBranchSelector.cpp - Emit long conditional branches ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
0 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This describes the calling conventions for the PowerPC 32- and 64-bit
None //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=//
0 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===//
0 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //==-- PPCFrameLowering.h - Define frame lowering for PowerPC ----*- C++ -*-==//
0 //===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
1 //
0 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the PowerPC 64-bit instructions. These patterns are used
None //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
1 //
0 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the Altivec extension to the PowerPC instruction set.
0 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
0 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
0 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef POWERPC32_INSTRUCTIONINFO_H
14 #define POWERPC32_INSTRUCTIONINFO_H
13 #ifndef POWERPC_INSTRUCTIONINFO_H
14 #define POWERPC_INSTRUCTIONINFO_H
1515
1616 #include "PPC.h"
1717 #include "llvm/Target/TargetInstrInfo.h"
None //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
1 //
0 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the subset of the 32-bit PowerPC instruction set, as used
None //===- PPCJITInfo.h - PowerPC impl. of the JIT interface --------*- C++ -*-===//
0 //===-- PPCJITInfo.h - PowerPC impl. of the JIT interface -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=-- PPCMachineFunctionInfo.cpp - Private data used for PowerPC --*- C++ -*-=//
0 //===-- PPCMachineFunctionInfo.cpp - Private data used for PowerPC --------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table ---------------===//
0 //===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
0 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPCRegisterInfo.h - PowerPC Register Information Impl -----*- C++ -*-==//
0 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
1 //
0 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 //
None //===- PPCRelocations.h - PPC32 Code Relocations ----------------*- C++ -*-===//
0 //===-- PPCRelocations.h - PPC Code Relocations -----------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef PPC32RELOCATIONS_H
14 #define PPC32RELOCATIONS_H
13 #ifndef PPCRELOCATIONS_H
14 #define PPCRELOCATIONS_H
1515
1616 #include "llvm/CodeGen/MachineRelocation.h"
1717
None //===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===//
1 //
0 //===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- PPCSchedule440.td - PPC 440 Scheduling Definitions --*- tablegen -*-===//
1 //
0 //===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 // Primary reference:
None //===- PPCScheduleG3.td - PPC G3 Scheduling Definitions ----*- tablegen -*-===//
1 //
0 //===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the itinerary class data for the G3 (750) processor.
None //===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===//
1 //
0 //===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the itinerary class data for the G4 (7400) processor.
None //===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
1 //
0 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the itinerary class data for the G4+ (7450) processor.
None //===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===//
1 //
0 //===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file defines the itinerary class data for the G5 (970) processor.
None //===- PowerPCSubtarget.cpp - PPC Subtarget Information -------------------===//
0 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- PPCSubtarget.h - Define Subtarget for the PPC -------*- C++ -*--====//
0 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=//
0 //===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- SparcMCAsmInfo.h - Sparc asm properties -------------*- C++ -*--====//
0 //===-- SparcMCAsmInfo.h - Sparc asm properties ----------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions --------*- C++ -*-===//
0 //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- Sparc.td - Describe the Sparc Target Machine --------*- tablegen -*-===//
1 //
0 //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 //
None //===- SparcCallingConv.td - Calling Conventions Sparc -----*- tablegen -*-===//
1 //
0 //===-- SparcCallingConv.td - Calling Conventions Sparc ----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This describes the calling conventions for the Sparc architectures.
None //====- SparcFrameLowering.cpp - Sparc Frame Information -------*- C++ -*-====//
0 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*--===//
0 //===-- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
1 //
0 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 class InstSP pattern> : Instruction {
None //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
0 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
0 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
1 //
0 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the Sparc instructions in TableGen format.
None //==- SparcMachineFunctionInfo.cpp - Sparc Machine Function Info -*- C++ -*-==//
0 //===-- SparcMachineFunctionInfo.cpp - Sparc Machine Function Info --------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
0 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcRegisterInfo.h - Sparc Register Information Impl ----*- C++ -*-===//
0 //===-- SparcRegisterInfo.h - Sparc Register Information Impl ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===//
1 //
0 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //===- SparcSubtarget.cpp - SPARC Subtarget Information -------------------===//
0 //===-- SparcSubtarget.cpp - SPARC Subtarget Information ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- SparcSubtarget.h - Define Subtarget for the SPARC ----*- C++ -*-====//
0 //===-- SparcSubtarget.h - Define Subtarget for the SPARC -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
0 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86Disassembler.h - Disassembler for x86 and x86_64 ------*- C++ -*-===//
0 //===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None /*===- X86DisassemblerDecoder.c - Disassembler decoder -------------*- C -*-==*
0 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
11 *
22 * The LLVM Compiler Infrastructure
33 *
None /*===- X86DisassemblerDecoderInternal.h - Disassembler decoder -----*- C -*-==*
0 /*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===*
11 *
22 * The LLVM Compiler Infrastructure
33 *
None /*===- X86DisassemblerDecoderCommon.h - Disassembler decoder -------*- C -*-==*
0 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
11 *
22 * The LLVM Compiler Infrastructure
33 *
None //===-- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax -------===//
0 //==- X86ATTInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86InstComments.h - Generate verbose-asm comments for instrs ------===//
0 //=- X86InstComments.h - Generate verbose-asm comments for instrs -*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -----===//
0 //= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86/X86FixupKinds.h - X86 Specific Fixup Entries --------*- C++ -*-===//
0 //===-- X86FixupKinds.h - X86 Specific Fixup Entries ------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- X86MCAsmInfo.h - X86 asm properties -----------------*- C++ -*--====//
0 //===-- X86MCAsmInfo.h - X86 asm properties --------------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
0 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
0 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
0 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- llvm/CodeGen/X86COFFMachineModuleInfo.cpp -------------------------===//
0 //===-- X86COFFMachineModuleInfo.cpp --------------------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- llvm/CodeGen/X86COFFMachineModuleInfo.h -----------------*- C++ -*-===//
0 //===-- X86COFFMachineModuleInfo.h ------------------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
1 //
0 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This describes the calling conventions for the X86-32 and X86-64
None //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
0 //===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====//
0 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=-- X86TargetFrameLowering.h - Define frame lowering for X86 ---*- C++ -*-===//
0 //===-- X86TargetFrameLowering.h - Define frame lowering for X86 -*- C++ -*-==//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
0 //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
1 //
0 //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the integer arithmetic instructions in the X86
None //===- X86InstrCMovSetCC.td - Conditional Move and SetCC ---*- tablegen -*-===//
1 //
0 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the X86 conditional move and set on condition
None //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
0 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86InstrExtension.td - Sign and Zero Extensions -----*- tablegen -*-===//
1 //
0 //===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the sign and zero extension operations.
None //====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
0 //===-- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
0 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the X86 x87 FPU instruction set, defining the
None //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
1 //
0 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
None //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
0 //===-- X86InstrFragmentsSIMD.td - x86 ISA -----------------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file provides pattern fragments useful for SIMD instructions.
None //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
0 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
0 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
0 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
0 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
0 //===-- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86InstrSVM.td - SVM Instruction Set Extension ------*- tablegen -*-===//
1 //
0 //===-- X86InstrSVM.td - SVM Instruction Set Extension -----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the instructions that make up the AMD SVM instruction
None //===- X86InstrShiftRotate.td - Shift and Rotate Instrs ----*- tablegen -*-===//
1 //
0 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the shift and rotate instructions.
None //===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
1 //
0 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the X86 instructions that are generally used in
None //===- X86InstrVMX.td - VMX Instruction Set Extension ------*- tablegen -*-===//
1 //
0 //===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file describes the instructions that make up the Intel VMX instruction
None //====- X86InstrXOP.td - Describe the X86 Instruction Set --*- tablegen -*-====//
0 //===-- X86InstrXOP.td - Describe the X86 Instruction Set --*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
66 //
7 //===-----------------------------------------------------------------------===//
7 //===----------------------------------------------------------------------===//
88 //
99 // This file describes XOP (eXtended OPerations)
1010 //
11 //===-----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
1212
1313 multiclass xop2op opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
1414 def rr : IXOP
None //===- X86JITInfo.h - X86 implementation of the JIT interface --*- C++ -*-===//
0 //===-- X86JITInfo.h - X86 implementation of the JIT interface --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- X86MCInstLower.h - Lower MachineInstr to MCInst -------------------===//
0 //===-- X86MCInstLower.h - Lower MachineInstr to MCInst ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- X86MachineFuctionInfo.cpp - X86 machine function info ---*- C++ -*-===//
1 //
0 //===-- X86MachineFuctionInfo.cpp - X86 machine function info -------------===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88
99 #include "X86MachineFunctionInfo.h"
None //====- X86MachineFuctionInfo.h - X86 machine function info -----*- C++ -*-===//
1 //
0 //===-- X86MachineFuctionInfo.h - X86 machine function info -----*- C++ -*-===//
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file declares X86-specific per-machine-function information.
None //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
0 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
0 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86Relocations.h - X86 Code Relocations ------------------*- C++ -*-===//
0 //===-- X86Relocations.h - X86 Code Relocations -----------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- X86Schedule.td - X86 Scheduling Definitions ---------*- tablegen -*-===//
0 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-=//
0 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
0 //===---- X86Subtarget.h - Define Subtarget for the X86 --------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- llvm/Target/X86/X86TargetObjectFile.cpp - X86 Object Info ---------===//
0 //===-- X86TargetObjectFile.cpp - X86 Object Info -------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- llvm/Target/X86/X86TargetObjectFile.h - X86 Object Info -*- C++ -*-===//
0 //===-- X86TargetObjectFile.h - X86 Object Info -----------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- XCoreMCAsmInfo.h - XCore asm properties -------------*- C++ -*--====//
0 //===-- XCoreMCAsmInfo.h - XCore asm properties ----------------*- C++ -*--===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -------*- C++ -*-===//
0 //===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
0 //===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This is the top level entry point for the XCore target.
910 //
1011 //===----------------------------------------------------------------------===//
1112
None //===-- XCoreFrameLowering.cpp - Frame info for XCore Target -----*- C++ -*-==//
0 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- XCoreFrameLowering.h - Frame info for XCore Target -------*- C++ -*-==//
0 //===-- XCoreFrameLowering.h - Frame info for XCore Target ------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
0 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreInstrFormats.td - XCore Instruction Formats ----*- tablegen -*-===//
0 //===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
0 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
0 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===//
0 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreMachineFuctionInfo.cpp - XCore machine function info -*- C++ -*-==//
0 //===-- XCoreMachineFuctionInfo.cpp - XCore machine function info ---------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //====- XCoreMachineFuctionInfo.h - XCore machine function info -*- C++ -*-===//
0 //===-- XCoreMachineFuctionInfo.h - XCore machine function info -*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
0 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreRegisterInfo.h - XCore Register Information Impl ----*- C++ -*-===//
0 //===-- XCoreRegisterInfo.h - XCore Register Information Impl ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===//
0 //===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===- XCoreSubtarget.cpp - XCore Subtarget Information -----------*- C++ -*-=//
0 //===-- XCoreSubtarget.cpp - XCore Subtarget Information ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //=====-- XCoreSubtarget.h - Define Subtarget for the XCore -----*- C++ -*--==//
0 //===-- XCoreSubtarget.h - Define Subtarget for the XCore -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
None //===-- llvm/Target/XCoreTargetObjectFile.h - XCore Object Info -*- C++ -*-===//
0 //===-- XCoreTargetObjectFile.h - XCore Object Info -------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //