llvm.org GIT mirror llvm / 31cbac1
Allow vector shifts (shl,lshr,ashr) on SPU. There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8 Kalle Raiskila 9 years ago
2 changed file(s) with 71 addition(s) and 54 deletion(s). Raw diff Collapse all Expand all
20142014 RotShiftVec, pattern>;
20152015
20162016 class SHLHVecInst:
2017 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2017 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
20182018 [(set (vectype VECREG:$rT),
2019 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
2019 (SPUvec_shl (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
20202020
20212021 multiclass ShiftLeftHalfword
20222022 {
20642064 multiclass ShiftLeftWord
20652065 {
20662066 def v4i32:
2067 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2067 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
20682068 [(set (v4i32 VECREG:$rT),
2069 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
2069 (SPUvec_shl (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
20702070 def r32:
20712071 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
20722072 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
25122512 RotShiftVec, pattern>;
25132513
25142514 def ROTHMv8i16:
2515 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2515 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
25162516 [/* see patterns below - $rB must be negated */]>;
25172517
2518 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2519 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2520
2521 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2522 (ROTHMv8i16 VECREG:$rA,
2523 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2524
2525 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2526 (ROTHMv8i16 VECREG:$rA,
2527 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2518 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
2519 (ROTHMv8i16 VECREG:$rA, (SFHIvec VECREG:$rB, 0))>;
25282520
25292521 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
25302522 // Note: This instruction doesn't match a pattern because rB must be negated
25852577 RotShiftVec, pattern>;
25862578
25872579 def ROTMv4i32:
2588 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2580 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
25892581 [/* see patterns below - $rB must be negated */]>;
25902582
2591 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB),
2592 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2593
2594 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB),
2595 (ROTMv4i32 VECREG:$rA,
2596 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2597
2598 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB),
2599 (ROTMv4i32 VECREG:$rA,
2600 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2583 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
2584 (ROTMv4i32 VECREG:$rA, (SFIvec VECREG:$rB, 0))>;
26012585
26022586 def ROTMr32:
26032587 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
28032787 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
28042788
28052789 def ROTMAHv8i16:
2806 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2790 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
28072791 "rotmah\t$rT, $rA, $rB", RotShiftVec,
28082792 [/* see patterns below - $rB must be negated */]>;
28092793
2810 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB),
2811 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2812
2813 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB),
2814 (ROTMAHv8i16 VECREG:$rA,
2815 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2816
2817 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB),
2818 (ROTMAHv8i16 VECREG:$rA,
2819 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2794 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
2795 (ROTMAHv8i16 VECREG:$rA, (SFHIvec VECREG:$rB, 0))>;
28202796
28212797 def ROTMAHr16:
28222798 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
28582834 (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
28592835
28602836 def ROTMAv4i32:
2861 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2837 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
28622838 "rotma\t$rT, $rA, $rB", RotShiftVec,
28632839 [/* see patterns below - $rB must be negated */]>;
28642840
2865 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB),
2866 (ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2867
2868 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB),
2869 (ROTMAv4i32 VECREG:$rA,
2870 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2871
2872 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB),
2873 (ROTMAv4i32 VECREG:$rA,
2874 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2841 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
2842 (ROTMAv4i32 VECREG:$rA, (SFIvec (v4i32 VECREG:$rB), 0))>;
28752843
28762844 def ROTMAr32:
28772845 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
0 ; RUN: llc < %s -march=cellspu > %t1.s
1 ; RUN: grep {shlh } %t1.s | count 9
1 ; RUN: grep {shlh } %t1.s | count 10
22 ; RUN: grep {shlhi } %t1.s | count 3
3 ; RUN: grep {shl } %t1.s | count 9
3 ; RUN: grep {shl } %t1.s | count 11
44 ; RUN: grep {shli } %t1.s | count 3
55 ; RUN: grep {xshw } %t1.s | count 5
66 ; RUN: grep {and } %t1.s | count 14
1313 ; RUN: grep {rotqbyi } %t1.s | count 1
1414 ; RUN: grep {rotqbii } %t1.s | count 2
1515 ; RUN: grep {rotqbybi } %t1.s | count 1
16 ; RUN: grep {sfi } %t1.s | count 4
16 ; RUN: grep {sfi } %t1.s | count 6
1717 ; RUN: cat %t1.s | FileCheck %s
1818
1919 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
2020 target triple = "spu"
21
22 ; Vector shifts are not currently supported in gcc or llvm assembly. These are
23 ; not tested.
2421
2522 ; Shift left i16 via register, note that the second operand to shl is promoted
2623 ; to a 32-bit type:
292289 %rv = lshr i128 %val, 64
293290 ret i128 %rv
294291 }
292
293 ;Vector shifts
294 define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) {
295 ;CHECK: shl
296 ;CHECK: bi $lr
297 %rv = shl <2 x i32> %val, %sh
298 ret <2 x i32> %rv
299 }
300
301 define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) {
302 ;CHECK: shl
303 ;CHECK: bi $lr
304 %rv = shl <4 x i32> %val, %sh
305 ret <4 x i32> %rv
306 }
307
308 define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) {
309 ;CHECK: shlh
310 ;CHECK: bi $lr
311 %rv = shl <8 x i16> %val, %sh
312 ret <8 x i16> %rv
313 }
314
315 define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
316 ;CHECK: rotm
317 ;CHECK: bi $lr
318 %rv = lshr <4 x i32> %val, %sh
319 ret <4 x i32> %rv
320 }
321
322 define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
323 ;CHECK: sfhi
324 ;CHECK: rothm
325 ;CHECK: bi $lr
326 %rv = lshr <8 x i16> %val, %sh
327 ret <8 x i16> %rv
328 }
329
330 define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) {
331 ;CHECK: rotma
332 ;CHECK: bi $lr
333 %rv = ashr <4 x i32> %val, %sh
334 ret <4 x i32> %rv
335 }
336
337 define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) {
338 ;CHECK: sfhi
339 ;CHECK: rotmah
340 ;CHECK: bi $lr
341 %rv = ashr <8 x i16> %val, %sh
342 ret <8 x i16> %rv
343 }