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Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
7 changed file(s) with 135 addition(s) and 142 deletion(s). Raw diff Collapse all Expand all
308308 Src1Name = getRegName(MI->getOperand(1).getReg());
309309 // FALL THROUGH.
310310 case X86::VPERMILPSmi:
311 DecodeVPERMILPSMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
312 ShuffleMask);
311 DecodeVPERMILPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
312 ShuffleMask);
313313 DestName = getRegName(MI->getOperand(0).getReg());
314314 break;
315315 case X86::VPERMILPSYri:
316316 Src1Name = getRegName(MI->getOperand(1).getReg());
317317 // FALL THROUGH.
318318 case X86::VPERMILPSYmi:
319 DecodeVPERMILPSMask(8, MI->getOperand(MI->getNumOperands()-1).getImm(),
320 ShuffleMask);
319 DecodeVPERMILPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
320 ShuffleMask);
321321 DestName = getRegName(MI->getOperand(0).getReg());
322322 break;
323323 case X86::VPERMILPDri:
324324 Src1Name = getRegName(MI->getOperand(1).getReg());
325325 // FALL THROUGH.
326326 case X86::VPERMILPDmi:
327 DecodeVPERMILPDMask(2, MI->getOperand(MI->getNumOperands()-1).getImm(),
328 ShuffleMask);
327 DecodeVPERMILPMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
328 ShuffleMask);
329329 DestName = getRegName(MI->getOperand(0).getReg());
330330 break;
331331 case X86::VPERMILPDYri:
332332 Src1Name = getRegName(MI->getOperand(1).getReg());
333333 // FALL THROUGH.
334334 case X86::VPERMILPDYmi:
335 DecodeVPERMILPDMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
336 ShuffleMask);
335 DecodeVPERMILPMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
336 ShuffleMask);
337337 DestName = getRegName(MI->getOperand(0).getReg());
338338 break;
339339 case X86::VPERM2F128rr:
192192 }
193193 }
194194
195 // DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
196 // elements. For 256-bit vectors, it's considered as two 128 lanes, the
197 // referenced elements can't cross lanes and the mask of the first lane must
198 // be the same of the second.
199 void DecodeVPERMILPSMask(unsigned NumElts, unsigned Imm,
200 SmallVectorImpl &ShuffleMask) {
201 unsigned NumLanes = (NumElts*32)/128;
202 unsigned LaneSize = NumElts/NumLanes;
195 // DecodeVPERMILPMask - Decodes VPERMILPS/ VPERMILPD permutes for any 128-bit
196 // 32-bit or 64-bit elements. For 256-bit vectors, it's considered as two 128
197 // lanes. For VPERMILPS, referenced elements can't cross lanes and the mask of
198 // the first lane must be the same of the second.
199 void DecodeVPERMILPMask(EVT VT, unsigned Imm,
200 SmallVectorImpl &ShuffleMask) {
201 unsigned NumElts = VT.getVectorNumElements();
202
203 unsigned NumLanes = VT.getSizeInBits() / 128;
204 unsigned NumLaneElts = NumElts / NumLanes;
203205
204206 for (unsigned l = 0; l != NumLanes; ++l) {
205 for (unsigned i = 0; i != LaneSize; ++i) {
206 unsigned Idx = (Imm >> (i*2)) & 0x3 ;
207 ShuffleMask.push_back(Idx+(l*LaneSize));
208 }
209 }
210 }
211
212 // DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
213 // elements. For 256-bit vectors, it's considered as two 128 lanes, the
214 // referenced elements can't cross lanes but the mask of the first lane can
215 // be the different of the second (not like VPERMILPS).
216 void DecodeVPERMILPDMask(unsigned NumElts, unsigned Imm,
217 SmallVectorImpl &ShuffleMask) {
218 unsigned NumLanes = (NumElts*64)/128;
219 unsigned LaneSize = NumElts/NumLanes;
220
221 for (unsigned l = 0; l < NumLanes; ++l) {
222 for (unsigned i = l*LaneSize; i < LaneSize*(l+1); ++i) {
223 unsigned Idx = (Imm >> i) & 0x1;
224 ShuffleMask.push_back(Idx+(l*LaneSize));
207 unsigned LaneStart = l*NumLaneElts;
208 for (unsigned i = 0; i != NumLaneElts; ++i) {
209 unsigned Idx = NumLaneElts == 4 ? (Imm >> (i*2)) & 0x3
210 : (Imm >> (i+LaneStart)) & 0x1;
211 ShuffleMask.push_back(Idx+LaneStart);
225212 }
226213 }
227214 }
7777 void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl &ShuffleMask);
7878
7979
80 // DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
81 // elements. For 256-bit vectors, it's considered as two 128 lanes, the
82 // referenced elements can't cross lanes and the mask of the first lane must
83 // be the same of the second.
84 void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
85 SmallVectorImpl &ShuffleMask);
86
87 // DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
88 // elements. For 256-bit vectors, it's considered as two 128 lanes, the
89 // referenced elements can't cross lanes but the mask of the first lane can
90 // be the different of the second (not like VPERMILPS).
91 void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
80 // DecodeVPERMILPMask - Decodes VPERMILPS/ VPERMILPD permutes for any 128-bit
81 // 32-bit or 64-bit elements. For 256-bit vectors, it's considered as two 128
82 // lanes. For VPERMILPS, referenced elements can't cross lanes and the mask of
83 // the first lane must be the same of the second.
84 void DecodeVPERMILPMask(EVT VT, unsigned Imm,
9285 SmallVectorImpl &ShuffleMask);
9386
9487 void DecodeVPERM2F128Mask(unsigned Imm,
28462846 case X86ISD::PUNPCKL:
28472847 case X86ISD::UNPCKHP:
28482848 case X86ISD::PUNPCKH:
2849 case X86ISD::VPERMILPS:
2850 case X86ISD::VPERMILPD:
2849 case X86ISD::VPERMILP:
28512850 case X86ISD::VPERM2F128:
28522851 case X86ISD::VPERM2I128:
28532852 return true;
28752874 case X86ISD::PSHUFD:
28762875 case X86ISD::PSHUFHW:
28772876 case X86ISD::PSHUFLW:
2878 case X86ISD::VPERMILPS:
2879 case X86ISD::VPERMILPD:
2877 case X86ISD::VPERMILP:
28802878 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
28812879 }
28822880
46124610 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
46134611 Depth+1);
46144612 }
4615 case X86ISD::VPERMILPS:
4613 case X86ISD::VPERMILP:
46164614 ImmN = N->getOperand(N->getNumOperands()-1);
4617 DecodeVPERMILPSMask(NumElems, cast(ImmN)->getZExtValue(),
4618 ShuffleMask);
4619 break;
4620 case X86ISD::VPERMILPD:
4621 ImmN = N->getOperand(N->getNumOperands()-1);
4622 DecodeVPERMILPDMask(NumElems, cast(ImmN)->getZExtValue(),
4615 DecodeVPERMILPMask(VT, cast(ImmN)->getZExtValue(),
46234616 ShuffleMask);
46244617 break;
46254618 case X86ISD::VPERM2F128:
65276520 return 0;
65286521 }
65296522
6530 static inline unsigned getVPERMILOpcode(EVT VT) {
6531 switch(VT.getSimpleVT().SimpleTy) {
6532 case MVT::v4i32:
6533 case MVT::v4f32:
6534 case MVT::v8i32:
6535 case MVT::v8f32: return X86ISD::VPERMILPS;
6536 case MVT::v2i64:
6537 case MVT::v2f64:
6538 case MVT::v4i64:
6539 case MVT::v4f64: return X86ISD::VPERMILPD;
6540 default:
6541 llvm_unreachable("Unknown type for vpermil");
6542 }
6543 return 0;
6544 }
6545
65466523 static inline unsigned getVPERM2X128Opcode(EVT VT, bool HasAVX2) {
65476524 switch(VT.getSimpleVT().SimpleTy) {
65486525 case MVT::v32i8:
68756852
68766853 // Handle VPERMILPS/D* permutations
68776854 if (isVPERMILPMask(M, VT, Subtarget->hasAVX()))
6878 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6855 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
68796856 getShuffleVPERMILPImmediate(SVOp), DAG);
68806857
68816858 // Handle VPERM2F128/VPERM2I128 permutations
1117811155 case X86ISD::PUNPCKL: return "X86ISD::PUNPCKL";
1117911156 case X86ISD::PUNPCKH: return "X86ISD::PUNPCKH";
1118011157 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11181 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
11182 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
11158 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
1118311159 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
1118411160 case X86ISD::VPERM2I128: return "X86ISD::VPERM2I128";
1118511161 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
1476614742 case X86ISD::PSHUFLW:
1476714743 case X86ISD::MOVSS:
1476814744 case X86ISD::MOVSD:
14769 case X86ISD::VPERMILPS:
14770 case X86ISD::VPERMILPD:
14745 case X86ISD::VPERMILP:
1477114746 case X86ISD::VPERM2F128:
1477214747 case X86ISD::VPERM2I128:
1477314748 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
276276 UNPCKHP,
277277 PUNPCKL,
278278 PUNPCKH,
279 VPERMILPS,
280 VPERMILPD,
279 VPERMILP,
281280 VPERM2F128,
282281 VPERM2I128,
283282 VBROADCAST,
135135 def X86Punpckl : SDNode<"X86ISD::PUNPCKL", SDTShuff2Op>;
136136 def X86Punpckh : SDNode<"X86ISD::PUNPCKH", SDTShuff2Op>;
137137
138 def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>;
139 def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>;
138 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
140139
141140 def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
142141 def X86VPerm2i128 : SDNode<"X86ISD::VPERM2I128", SDTShuff3OpI>;
71637163 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
71647164 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
71657165
7166 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7167 (i32 imm)),
7168 (VINSERTF128rr VR256:$src1, VR128:$src2,
7169 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7170 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7171 (i32 imm)),
7172 (VINSERTF128rr VR256:$src1, VR128:$src2,
7173 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7174 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7175 (i32 imm)),
7176 (VINSERTF128rr VR256:$src1, VR128:$src2,
7177 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7178 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7179 (i32 imm)),
7180 (VINSERTF128rr VR256:$src1, VR128:$src2,
7181 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7182 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7183 (i32 imm)),
7184 (VINSERTF128rr VR256:$src1, VR128:$src2,
7185 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7186 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7187 (i32 imm)),
7188 (VINSERTF128rr VR256:$src1, VR128:$src2,
7189 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7190
71917166 //===----------------------------------------------------------------------===//
71927167 // VEXTRACTF128 - Extract packed floating-point values
71937168 //
72097184 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
72107185 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
72117186 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7212
7213 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7214 (v4f32 (VEXTRACTF128rr
7215 (v8f32 VR256:$src1),
7216 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7217 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7218 (v2f64 (VEXTRACTF128rr
7219 (v4f64 VR256:$src1),
7220 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7221 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7222 (v4i32 (VEXTRACTF128rr
7223 (v8i32 VR256:$src1),
7224 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7225 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7226 (v2i64 (VEXTRACTF128rr
7227 (v4i64 VR256:$src1),
7228 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7229 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7230 (v8i16 (VEXTRACTF128rr
7231 (v16i16 VR256:$src1),
7232 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7233 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7234 (v16i8 (VEXTRACTF128rr
7235 (v32i8 VR256:$src1),
7236 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
72377187
72387188 //===----------------------------------------------------------------------===//
72397189 // VMASKMOV - Conditional SIMD Packed Loads and Stores
73217271 int_x86_avx_vpermil_pd_256>;
73227272 }
73237273
7324 def : Pat<(v8f32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
7274 def : Pat<(v8f32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
73257275 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7326 def : Pat<(v4f64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
7276 def : Pat<(v4f64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
73277277 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7328 def : Pat<(v8i32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
7278 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
73297279 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7330 def : Pat<(v4i64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
7280 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
73317281 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7332 def : Pat<(v8f32 (X86VPermilps (memopv8f32 addr:$src1), (i8 imm:$imm))),
7282 def : Pat<(v8f32 (X86VPermilp (memopv8f32 addr:$src1), (i8 imm:$imm))),
73337283 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7334 def : Pat<(v4f64 (X86VPermilpd (memopv4f64 addr:$src1), (i8 imm:$imm))),
7284 def : Pat<(v4f64 (X86VPermilp (memopv4f64 addr:$src1), (i8 imm:$imm))),
73357285 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7336 def : Pat<(v8i32 (X86VPermilps (bc_v8i32 (memopv4i64 addr:$src1)),
7286 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
73377287 (i8 imm:$imm))),
73387288 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7339 def : Pat<(v4i64 (X86VPermilpd (memopv4i64 addr:$src1), (i8 imm:$imm))),
7289 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
73407290 (VPERMILPDYmi addr:$src1, imm:$imm)>;
73417291
73427292 //===----------------------------------------------------------------------===//
76557605 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
76567606 imm:$src3))]>, VEX_4V;
76577607
7608 let Predicates = [HasAVX2] in {
7609 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7610 (i32 imm)),
7611 (VINSERTI128rr VR256:$src1, VR128:$src2,
7612 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7613 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7614 (i32 imm)),
7615 (VINSERTI128rr VR256:$src1, VR128:$src2,
7616 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7617 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7618 (i32 imm)),
7619 (VINSERTI128rr VR256:$src1, VR128:$src2,
7620 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7621 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7622 (i32 imm)),
7623 (VINSERTI128rr VR256:$src1, VR128:$src2,
7624 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7625 }
7626
7627 // AVX1 patterns
7628 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7629 (i32 imm)),
7630 (VINSERTF128rr VR256:$src1, VR128:$src2,
7631 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7632 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7633 (i32 imm)),
7634 (VINSERTF128rr VR256:$src1, VR128:$src2,
7635 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7636 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7637 (i32 imm)),
7638 (VINSERTF128rr VR256:$src1, VR128:$src2,
7639 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7640 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7641 (i32 imm)),
7642 (VINSERTF128rr VR256:$src1, VR128:$src2,
7643 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7644 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7645 (i32 imm)),
7646 (VINSERTF128rr VR256:$src1, VR128:$src2,
7647 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7648 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7649 (i32 imm)),
7650 (VINSERTF128rr VR256:$src1, VR128:$src2,
7651 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7652
76587653 //===----------------------------------------------------------------------===//
76597654 // VEXTRACTI128 - Extract packed integer values
76607655 //
76687663 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
76697664 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
76707665 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7666
7667 let Predicates = [HasAVX2] in {
7668 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7669 (v2i64 (VEXTRACTI128rr
7670 (v4i64 VR256:$src1),
7671 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7672 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7673 (v4i32 (VEXTRACTI128rr
7674 (v8i32 VR256:$src1),
7675 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7676 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7677 (v8i16 (VEXTRACTI128rr
7678 (v16i16 VR256:$src1),
7679 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7680 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7681 (v16i8 (VEXTRACTI128rr
7682 (v32i8 VR256:$src1),
7683 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7684 }
7685
7686 // AVX1 patterns
7687 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7688 (v4f32 (VEXTRACTF128rr
7689 (v8f32 VR256:$src1),
7690 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7691 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7692 (v2f64 (VEXTRACTF128rr
7693 (v4f64 VR256:$src1),
7694 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7695 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7696 (v2i64 (VEXTRACTF128rr
7697 (v4i64 VR256:$src1),
7698 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7699 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7700 (v4i32 (VEXTRACTF128rr
7701 (v8i32 VR256:$src1),
7702 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7703 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7704 (v8i16 (VEXTRACTF128rr
7705 (v16i16 VR256:$src1),
7706 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7707 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7708 (v16i8 (VEXTRACTF128rr
7709 (v32i8 VR256:$src1),
7710 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
76717711
76727712 //===----------------------------------------------------------------------===//
76737713 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores