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[ARM] Add diagnostics for SPR/DPR lists Differential revision: https://reviews.llvm.org/D39195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318766 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 2 years ago
3 changed file(s) with 55 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
525525
526526 def GPRPairOp : RegisterOperand;
527527
528 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
528 def DPRRegListAsmOperand : AsmOperandClass {
529 let Name = "DPRRegList";
530 let DiagnosticType = "DPR_RegList";
531 }
529532 def dpr_reglist : Operand {
530533 let EncoderMethod = "getRegisterListOpValue";
531534 let ParserMatchClass = DPRRegListAsmOperand;
533536 let DecoderMethod = "DecodeDPRRegListOperand";
534537 }
535538
536 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
539 def SPRRegListAsmOperand : AsmOperandClass {
540 let Name = "SPRRegList";
541 let DiagnosticString = "operand must be a list of registers in range [s0, s31]";
542 }
537543 def spr_reglist : Operand {
538544 let EncoderMethod = "getRegisterListOpValue";
539545 let ParserMatchClass = SPRRegListAsmOperand;
1013610136 case Match_DPR:
1013710137 return hasD16() ? "operand must be a register in range [d0, d15]"
1013810138 : "operand must be a register in range [d0, d31]";
10139 case Match_DPR_RegList:
10140 return hasD16() ? "operand must be a list of registers in range [d0, d15]"
10141 : "operand must be a list of registers in range [d0, d31]";
1013910142
1014010143 // For all other diags, use the static string from tablegen.
1014110144 default:
0 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D32
1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null -mattr=+d16 %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-D16
2
3 // First operand must be a GPR
4 vldm s0, {s1, s2}
5 // CHECK: error: operand must be a register in range [r0, r15]
6 // CHECK-NEXT: vldm s0, {s1, s2}
7
8 vstm s0, {s1, s2}
9 // CHECK: error: operand must be a register in range [r0, r15]
10 // CHECK-NEXT: vstm s0, {s1, s2}
11
12
13 // Second operand must be a list of SPRs or DPRs
14 vldm r0, {r1, r2}
15 // CHECK: error: invalid instruction, any one of the following would fix this:
16 // CHECK-NEXT: vldm r0, {r1, r2}
17 // CHECK: note: operand must be a list of registers in range [s0, s31]
18 // CHECK-D32: note: operand must be a list of registers in range [d0, d31]
19 // CHECK-D16: note: operand must be a list of registers in range [d0, d15]
20 vldm r0, #42
21 // CHECK: error: invalid instruction, any one of the following would fix this:
22 // CHECK-NEXT: vldm r0, #42
23 // CHECK: note: operand must be a list of registers in range [s0, s31]
24 // CHECK-D32: note: operand must be a list of registers in range [d0, d31]
25 // CHECK-D16: note: operand must be a list of registers in range [d0, d15]
26 vldm r0, {s1, d2}
27 // CHECK: error: invalid register in register list
28 // CHECK-NEXT: vldm r0, {s1, d2}
29 vstm r0, {r1, r2}
30 // CHECK: error: invalid instruction, any one of the following would fix this:
31 // CHECK-NEXT: vstm r0, {r1, r2}
32 // CHECK: note: operand must be a list of registers in range [s0, s31]
33 // CHECK-D32: note: operand must be a list of registers in range [d0, d31]
34 // CHECK-D16: note: operand must be a list of registers in range [d0, d15]
35 vstm r0, #42
36 // CHECK: error: invalid instruction, any one of the following would fix this:
37 // CHECK-NEXT: vstm r0, #42
38 // CHECK: note: operand must be a list of registers in range [s0, s31]
39 // CHECK-D32: note: operand must be a list of registers in range [d0, d31]
40 // CHECK-D16: note: operand must be a list of registers in range [d0, d15]
41 vstm r0, {s1, d2}
42 // CHECK: error: invalid register in register list
43 // CHECK-NEXT: vstm r0, {s1, d2}