llvm.org GIT mirror llvm / 3143430
[AArch64] Refactor LSE support as feature separate from V8.1a support. Summary: This is preparation for ThunderX processors that have Large System Extension (LSE) atomic instructions, but not the other instructions introduced by V8.1a. This will mimic changes to GCC as described here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html LSE instructions are: LD/ST<op>, CAS*, SWP Reviewers: t.p.northover, echristo, jmolloy, rengolin Subscribers: aemerson, mehdi_amini Differential Revision: https://reviews.llvm.org/D26621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288279 91177308-0d34-0410-b5e6-96231b3b80d8 Joel Jones 3 years ago
10 changed file(s) with 47 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
2020 AARCH64_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
2121 FK_CRYPTO_NEON_FP_ARMV8,
2222 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
23 AArch64::AEK_SIMD))
23 AArch64::AEK_SIMD | AArch64::AEK_LSE))
2424 AARCH64_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
2525 ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
2626 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
27 AArch64::AEK_SIMD))
27 AArch64::AEK_SIMD | AArch64::AEK_LSE))
2828 AARCH64_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a",
2929 ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
3030 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
31 AArch64::AEK_SIMD | AArch64::AEK_RAS))
31 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
3232 #undef AARCH64_ARCH
3333
3434 #ifndef AARCH64_ARCH_EXT_NAME
3838 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
3939 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
4040 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
41 AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")
4142 AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")
4243 AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
4344 AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
161161 AEK_SIMD = 0x10,
162162 AEK_FP16 = 0x20,
163163 AEK_PROFILE = 0x40,
164 AEK_RAS = 0x80
164 AEK_RAS = 0x80,
165 AEK_LSE = 0x100
165166 };
166167
167168 StringRef getCanonicalArchName(StringRef Arch);
3333
3434 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
3535 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
36
37 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
38 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
3639
3740 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
3841 "Enable ARMv8 PMUv3 Performance Monitors extension">;
110113 //
111114
112115 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
113 "Support ARM v8.1a instructions", [FeatureCRC]>;
116 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
114117
115118 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
116119 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
93479347 // ST{}[] , []
93489348 // ST{} , []
93499349
9350 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
9350 let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
93519351 class BaseCASEncoding
93529352 string cstr, list pattern>
93539353 : I {
93689368 let Inst{14-10} = 0b11111;
93699369 let Inst{9-5} = Rn;
93709370 let Inst{4-0} = Rt;
9371 let Predicates = [HasLSE];
93719372 }
93729373
93739374 class BaseCAS
94009401 def d : BaseCASP;
94019402 }
94029403
9403 let Predicates = [HasV8_1a] in
9404 let Predicates = [HasLSE] in
94049405 class BaseSWP
94059406 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size,
94069407 "\t$Rs, $Rt, [$Rn]","",[]>,
94239424 let Inst{11-10} = 0b00;
94249425 let Inst{9-5} = Rn;
94259426 let Inst{4-0} = Rt;
9427 let Predicates = [HasLSE];
94269428 }
94279429
94289430 multiclass Swap Acq, bits<1> Rel, string order> {
94329434 let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP;
94339435 }
94349436
9435 let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
9437 let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
94369438 class BaseLDOPregister
94379439 : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size,
94389440 "\t$Rs, $Rt, [$Rn]","",[]>,
94559457 let Inst{11-10} = 0b00;
94569458 let Inst{9-5} = Rn;
94579459 let Inst{4-0} = Rt;
9460 let Predicates = [HasLSE];
94589461 }
94599462
94609463 multiclass LDOPregister opc, string op, bits<1> Acq, bits<1> Rel,
94699472 def d : BaseLDOPregister;
94709473 }
94719474
9472 let Predicates = [HasV8_1a] in
9475 let Predicates = [HasLSE] in
94739476 class BaseSTOPregister
94749477 Instruction inst> :
94759478 InstAlias;
2525 AssemblerPredicate<"FeatureCrypto", "crypto">;
2626 def HasCRC : Predicate<"Subtarget->hasCRC()">,
2727 AssemblerPredicate<"FeatureCRC", "crc">;
28 def HasLSE : Predicate<"Subtarget->hasLSE()">,
29 AssemblerPredicate<"FeatureLSE", "lse">;
2830 def HasRAS : Predicate<"Subtarget->hasRAS()">,
2931 AssemblerPredicate<"FeatureRAS", "ras">;
3032 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
5858 bool HasNEON = false;
5959 bool HasCrypto = false;
6060 bool HasCRC = false;
61 bool HasLSE = false;
6162 bool HasRAS = false;
6263 bool HasPerfMon = false;
6364 bool HasFullFP16 = false;
179180 bool hasNEON() const { return HasNEON; }
180181 bool hasCrypto() const { return HasCrypto; }
181182 bool hasCRC() const { return HasCRC; }
183 bool hasLSE() const { return HasLSE; }
182184 bool hasRAS() const { return HasRAS; }
183185 bool balanceFPOps() const { return BalanceFPOps; }
184186 bool predictableSelectIsExpensive() const {
41364136 { "fp", {AArch64::FeatureFPARMv8} },
41374137 { "simd", {AArch64::FeatureNEON} },
41384138 { "ras", {AArch64::FeatureRAS} },
4139 { "lse", {AArch64::FeatureLSE} },
41394140
41404141 // FIXME: Unsupported extensions
4141 { "lse", {} },
41424142 { "pan", {} },
41434143 { "lor", {} },
41444144 { "rdma", {} },
0 // RUN: not llvm-mc -triple=arm64-linux-gnu -mattr=armv8.1a -mattr=-lse < %s 2> %t
1 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
2
3 casa w5, w7, [x20]
4 // CHECK-ERROR: error: instruction requires: lse
5 // CHECK-ERROR-NEXT: casa w5, w7, [x20]
6 // CHECK-ERROR-NEXT: ^
7
3434
3535 # CHECK: error: instruction requires: ras
3636 # CHECK: esb
37
38 .arch armv8.1-a+nolse
39 casa w5, w7, [x20]
40
41 # CHECK: error: instruction requires: lse
42 # CHECK: casa w5, w7, [x20]
3535
3636 aesd v0.16b, v2.16b
3737
38 .cpu generic+v8.1a+nolse
39 casa w5, w7, [x20]
40
41 .cpu generic+v8.1a+lse
42 casa w5, w7, [x20]
43
3844 // NOTE: the errors precede the actual output! The errors appear in order
3945 // though, so validate by hoisting them to the top and preservering relative
4046 // ordering
5561 // CHECK: aesd v0.16b, v2.16b
5662 // CHECK: ^
5763
64 // CHECK: error: instruction requires: lse
65 // CHECK: casa w5, w7, [x20]
66 // CHECK: ^
67
5868 // CHECK: fminnm d0, d0, d1
5969 // CHECK: fminnm d0, d0, d1
6070 // CHECK: addp v0.4s, v0.4s, v0.4s
6171 // CHECK: crc32cx w0, w1, x3
6272 // CHECK: aesd v0.16b, v2.16b
73 // CHECK: casa w5, w7, [x20]