llvm.org GIT mirror llvm / 3139422
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced some infinite loop and select failures. - Apologies for eager reverting, but its branch day. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113000 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 10 years ago
2 changed file(s) with 16 addition(s) and 133 deletion(s). Raw diff Collapse all Expand all
1414 #define DEBUG_TYPE "x86-isel"
1515 #include "X86.h"
1616 #include "X86InstrBuilder.h"
17 #include "X86ShuffleDecode.h"
1817 #include "X86ISelLowering.h"
1918 #include "X86TargetMachine.h"
2019 #include "X86TargetObjectFile.h"
26022601 case X86ISD::MOVSS:
26032602 case X86ISD::MOVSD:
26042603 case X86ISD::UNPCKLPS:
2605 case X86ISD::UNPCKLPD:
26062604 case X86ISD::PUNPCKLWD:
26072605 case X86ISD::PUNPCKLBW:
26082606 case X86ISD::PUNPCKLDQ:
2609 case X86ISD::PUNPCKLQDQ:
26102607 case X86ISD::UNPCKHPS:
26112608 case X86ISD::PUNPCKHWD:
26122609 case X86ISD::PUNPCKHBW:
26652662 case X86ISD::MOVSS:
26662663 case X86ISD::MOVSD:
26672664 case X86ISD::UNPCKLPS:
2668 case X86ISD::UNPCKLPD:
26692665 case X86ISD::PUNPCKLWD:
26702666 case X86ISD::PUNPCKLBW:
26712667 case X86ISD::PUNPCKLDQ:
2672 case X86ISD::PUNPCKLQDQ:
26732668 case X86ISD::UNPCKHPS:
26742669 case X86ISD::PUNPCKHWD:
26752670 case X86ISD::PUNPCKHBW:
37023697
37033698 // Recurse into target specific vector shuffles to find scalars.
37043699 if (isTargetShuffle(Opcode)) {
3705 int NumElems = VT.getVectorNumElements();
3706 SmallVector ShuffleMask;
3707 SDValue ImmN;
3708
37093700 switch(Opcode) {
3710 case X86ISD::SHUFPS:
3711 case X86ISD::SHUFPD:
3712 ImmN = N->getOperand(N->getNumOperands()-1);
3713 DecodeSHUFPSMask(NumElems,
3714 cast(ImmN)->getZExtValue(),
3715 ShuffleMask);
3716 break;
3717 case X86ISD::PUNPCKHBW:
3718 case X86ISD::PUNPCKHWD:
3719 case X86ISD::PUNPCKHDQ:
3720 case X86ISD::PUNPCKHQDQ:
3721 DecodePUNPCKHMask(NumElems, ShuffleMask);
3722 break;
3723 case X86ISD::UNPCKHPS:
3724 case X86ISD::UNPCKHPD:
3725 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3726 break;
3727 case X86ISD::PUNPCKLBW:
3728 case X86ISD::PUNPCKLWD:
3729 case X86ISD::PUNPCKLDQ:
3730 case X86ISD::PUNPCKLQDQ:
3731 DecodePUNPCKLMask(NumElems, ShuffleMask);
3732 break;
3733 case X86ISD::UNPCKLPS:
3734 case X86ISD::UNPCKLPD:
3735 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3736 break;
3737 case X86ISD::MOVHLPS:
3738 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3739 break;
3740 case X86ISD::MOVLHPS:
3741 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3742 break;
3743 case X86ISD::PSHUFD:
3744 ImmN = N->getOperand(N->getNumOperands()-1);
3745 DecodePSHUFMask(NumElems,
3746 cast(ImmN)->getZExtValue(),
3747 ShuffleMask);
3748 break;
3749 case X86ISD::PSHUFHW:
3750 ImmN = N->getOperand(N->getNumOperands()-1);
3751 DecodePSHUFHWMask(cast(ImmN)->getZExtValue(),
3752 ShuffleMask);
3753 break;
3754 case X86ISD::PSHUFLW:
3755 ImmN = N->getOperand(N->getNumOperands()-1);
3756 DecodePSHUFLWMask(cast(ImmN)->getZExtValue(),
3757 ShuffleMask);
3758 break;
37593701 case X86ISD::MOVSS:
37603702 case X86ISD::MOVSD: {
37613703 // The index 0 always comes from the first element of the second source,
37683710 assert("not implemented for target shuffle node");
37693711 return SDValue();
37703712 }
3771
3772 Index = ShuffleMask[Index];
3773 if (Index < 0)
3774 return DAG.getUNDEF(VT.getVectorElementType());
3775
3776 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3777 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG);
37783713 }
37793714
37803715 // Actual nodes that may contain scalar elements
51135048 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
51145049 }
51155050
5116 static bool MayFoldVectorLoad(SDValue V) {
5117 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5118 V = V.getOperand(0);
5119 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5120 V = V.getOperand(0);
5121 if (MayFoldLoad(V))
5122 return true;
5123 return false;
5124 }
5125
51265051 static
51275052 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
51285053 bool HasSSE2) {
51675092 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
51685093 // same masks.
51695094 bool CanFoldLoad = false;
5095 SDValue TmpV1 = V1;
5096 SDValue TmpV2 = V2;
51705097
51715098 // Trivial case, when V2 comes from a load.
5172 if (MayFoldVectorLoad(V2))
5099 if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT)
5100 TmpV2 = TmpV2.getOperand(0);
5101 if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR)
5102 TmpV2 = TmpV2.getOperand(0);
5103 if (MayFoldLoad(TmpV2))
51735104 CanFoldLoad = true;
51745105
51755106 // When V1 is a load, it can be folded later into a store in isel, example:
51775108 // turns into:
51785109 // (MOVLPSmr addr:$src1, VR128:$src2)
51795110 // So, recognize this potential and also use MOVLPS or MOVLPD
5180 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5111 if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT)
5112 TmpV1 = TmpV1.getOperand(0);
5113 if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op))
51815114 CanFoldLoad = true;
51825115
51835116 if (CanFoldLoad) {
52065139 // Invert the operand order and use SHUFPS to match it.
52075140 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
52085141 X86::getShuffleSHUFImmediate(SVOp), DAG);
5209 }
5210
5211 static unsigned getUNPCKLOpcode(EVT VT) {
5212 switch(VT.getSimpleVT().SimpleTy) {
5213 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5214 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5215 case MVT::v4f32: return X86ISD::UNPCKLPS;
5216 case MVT::v2f64: return X86ISD::UNPCKLPD;
5217 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5218 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5219 default:
5220 llvm_unreachable("Unknow type for unpckl");
5221 }
5222 return 0;
52235142 }
52245143
52255144 SDValue
53525271
53535272 // FIXME: fold these into legal mask.
53545273 if (!isMMX) {
5355 if (X86::isMOVLHPSMask(SVOp) &&
5356 (!X86::isUNPCKLMask(SVOp) || MayFoldVectorLoad(V2)))
5274 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
53575275 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
53585276
53595277 if (X86::isMOVHLPSMask(SVOp))
54075325 return getMOVL(DAG, dl, VT, V2, V1);
54085326 }
54095327
5410 if (X86::isUNPCKLMask(SVOp))
5411 return (isMMX) ?
5412 Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5413
5414 if (X86::isUNPCKHMask(SVOp))
5328 if (X86::isUNPCKLMask(SVOp) ||
5329 X86::isUNPCKHMask(SVOp))
54155330 return Op;
54165331
54175332 if (V2IsSplat) {
54345349 // FIXME: this seems wrong.
54355350 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
54365351 ShuffleVectorSDNode *NewSVOp = cast(NewOp);
5437
5438 if (X86::isUNPCKLMask(NewSVOp))
5439 return (isMMX) ?
5440 Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5441
5442 if (X86::isUNPCKHMask(NewSVOp))
5352 if (X86::isUNPCKLMask(NewSVOp) ||
5353 X86::isUNPCKHMask(NewSVOp))
54435354 return NewOp;
54445355 }
54455356
1070910620 SelectionDAG &DAG = DCI.DAG;
1071010621 switch (N->getOpcode()) {
1071110622 default: break;
10623 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
1071210624 case ISD::EXTRACT_VECTOR_ELT:
1071310625 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
1071410626 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
1072510637 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
1072610638 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
1072710639 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10728 case X86ISD::SHUFPS: // Handle all target specific shuffles
10729 case X86ISD::SHUFPD:
10730 case X86ISD::PUNPCKHBW:
10731 case X86ISD::PUNPCKHWD:
10732 case X86ISD::PUNPCKHDQ:
10733 case X86ISD::PUNPCKHQDQ:
10734 case X86ISD::UNPCKHPS:
10735 case X86ISD::UNPCKHPD:
10736 case X86ISD::PUNPCKLBW:
10737 case X86ISD::PUNPCKLWD:
10738 case X86ISD::PUNPCKLDQ:
10739 case X86ISD::PUNPCKLQDQ:
10740 case X86ISD::UNPCKLPS:
10741 case X86ISD::UNPCKLPD:
10742 case X86ISD::MOVHLPS:
10743 case X86ISD::MOVLHPS:
10744 case X86ISD::PSHUFD:
10745 case X86ISD::PSHUFHW:
10746 case X86ISD::PSHUFLW:
10747 case X86ISD::MOVSS:
10748 case X86ISD::MOVSD:
10749 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
1075010640 }
1075110641
1075210642 return SDValue();
58185818 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
58195819 (scalar_to_vector (loadf64 addr:$src2)))),
58205820 (MOVHPDrm VR128:$src1, addr:$src2)>;
5821 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5822 // is during lowering, where it's not possible to recognize the load fold cause
5823 // it has two uses through a bitcast. One use disappears at isel time and the
5824 // fold opportunity reappears.
5825 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5826 (scalar_to_vector (loadf64 addr:$src2)))),
5827 (MOVHPDrm VR128:$src1, addr:$src2)>;
58285821
58295822 // Shuffle with MOVSS
58305823 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),