llvm.org GIT mirror llvm / 3116dce
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 9 years ago
6 changed file(s) with 57 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
311311 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
312312 const { return 0; }
313313
314 unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op)
315 const { return 0; }
316 unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op)
317 const { return 0; }
318 unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op)
314 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
315 const { return 0; }
316 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
317 const { return 0; }
318 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
319 const { return 0; }
320 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
319321 const { return 0; }
320322
321323 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
220220 let PrintMethod = "printNegZeroOperand";
221221 }
222222
223 // Narrow Shift Right Immediate - A narrow shift right immediate is encoded
224 // differently from other shift immediates. The imm6 field is encoded like so:
223 // Shift Right Immediate - A shift right immediate is encoded differently from
224 // other shift immediates. The imm6 field is encoded like so:
225225 //
226 // 16-bit: imm6<5:3> = '001', 8 - is encded in imm6<2:0>
227 // 32-bit: imm6<5:4> = '01',16 - is encded in imm6<3:0>
228 // 64-bit: imm6<5> = '1', 32 - is encded in imm6<4:0>
229 def nsr16_imm : Operand {
230 let EncoderMethod = "getNarrowShiftRight16Imm";
231 }
232 def nsr32_imm : Operand {
233 let EncoderMethod = "getNarrowShiftRight32Imm";
234 }
235 def nsr64_imm : Operand {
236 let EncoderMethod = "getNarrowShiftRight64Imm";
226 // Offset Encoding
227 // 8 imm6<5:3> = '001', 8 - is encoded in imm6<2:0>
228 // 16 imm6<5:4> = '01', 16 - is encoded in imm6<3:0>
229 // 32 imm6<5> = '1', 32 - is encoded in imm6<4:0>
230 // 64 64 - is encoded in imm6<5:0>
231 def shr_imm8 : Operand {
232 let EncoderMethod = "getShiftRight8Imm";
233 }
234 def shr_imm16 : Operand {
235 let EncoderMethod = "getShiftRight16Imm";
236 }
237 def shr_imm32 : Operand {
238 let EncoderMethod = "getShiftRight32Imm";
239 }
240 def shr_imm64 : Operand {
241 let EncoderMethod = "getShiftRight64Imm";
237242 }
238243
239244 //===----------------------------------------------------------------------===//
31533153 SDNode OpNode> {
31543154 def v8i8 : N2VNSh
31553155 OpcodeStr, !strconcat(Dt, "16"),
3156 v8i8, v8i16, nsr16_imm, OpNode> {
3156 v8i8, v8i16, shr_imm8, OpNode> {
31573157 let Inst{21-19} = 0b001; // imm6 = 001xxx
31583158 }
31593159 def v4i16 : N2VNSh
31603160 OpcodeStr, !strconcat(Dt, "32"),
3161 v4i16, v4i32, nsr32_imm, OpNode> {
3161 v4i16, v4i32, shr_imm16, OpNode> {
31623162 let Inst{21-20} = 0b01; // imm6 = 01xxxx
31633163 }
31643164 def v2i32 : N2VNSh
31653165 OpcodeStr, !strconcat(Dt, "64"),
3166 v2i32, v2i64, nsr64_imm, OpNode> {
3166 v2i32, v2i64, shr_imm32, OpNode> {
31673167 let Inst{21} = 0b1; // imm6 = 1xxxxx
31683168 }
31693169 }
277277 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
278278 SmallVectorImpl &Fixups) const;
279279
280 unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
281 SmallVectorImpl &Fixups) const;
282 unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
283 SmallVectorImpl &Fixups) const;
284 unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
285 SmallVectorImpl &Fixups) const;
280 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
281 SmallVectorImpl &Fixups) const;
282 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
283 SmallVectorImpl &Fixups) const;
284 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
285 SmallVectorImpl &Fixups) const;
286 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
287 SmallVectorImpl &Fixups) const;
286288
287289 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
288290 unsigned EncodedValue) const;
12081210 }
12091211
12101212 unsigned ARMMCCodeEmitter::
1211 getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
1212 SmallVectorImpl &Fixups) const {
1213 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1214 SmallVectorImpl &Fixups) const {
12131215 return 8 - MI.getOperand(Op).getImm();
12141216 }
12151217
12161218 unsigned ARMMCCodeEmitter::
1217 getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
1218 SmallVectorImpl &Fixups) const {
1219 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1220 SmallVectorImpl &Fixups) const {
12191221 return 16 - MI.getOperand(Op).getImm();
12201222 }
12211223
12221224 unsigned ARMMCCodeEmitter::
1223 getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
1224 SmallVectorImpl &Fixups) const {
1225 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1226 SmallVectorImpl &Fixups) const {
12251227 return 32 - MI.getOperand(Op).getImm();
1228 }
1229
1230 unsigned ARMMCCodeEmitter::
1231 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1232 SmallVectorImpl &Fixups) const {
1233 return 64 - MI.getOperand(Op).getImm();
12261234 }
12271235
12281236 void ARMMCCodeEmitter::
157157 vrshrn.i32 d16, q8, #16
158158 @ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
159159 vrshrn.i64 d16, q8, #32
160
161 @ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
162 vqrshrn.s16 d16, q8, #4
160163 @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
161164 vqrshrn.s32 d16, q8, #13
165 @ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
166 vqrshrn.s64 d16, q8, #13
597597 IMM("t2adrlabel");
598598 IMM("shift_imm");
599599 IMM("neon_vcvt_imm32");
600 IMM("nsr16_imm");
601 IMM("nsr32_imm");
602 IMM("nsr64_imm");
600 IMM("shr_imm8");
601 IMM("shr_imm16");
602 IMM("shr_imm32");
603 IMM("shr_imm64");
603604
604605 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
605606 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?