llvm.org GIT mirror llvm / 308c60d
Implement LaneBitmask::any(), use it to replace !none(), NFCI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289974 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 3 years ago
25 changed file(s) with 73 addition(s) and 72 deletion(s). Raw diff Collapse all Expand all
314314 void appendTo(ContainerT &To) const {
315315 for (const IndexMaskPair &P : Regs) {
316316 unsigned Reg = getRegFromSparseIndex(P.Index);
317 if (!P.LaneMask.none())
317 if (P.LaneMask.any())
318318 To.push_back(RegisterMaskPair(Reg, P.LaneMask));
319319 }
320320 }
4747 constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
4848 constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
4949 constexpr bool none() const { return Mask == 0; }
50 constexpr bool any() const { return Mask != 0; }
5051 constexpr bool all() const { return ~Mask == 0; }
5152
5253 constexpr LaneBitmask operator~() const {
481481
482482 const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
483483 LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
484 if (!UsedLanes.none())
484 if (UsedLanes.any())
485485 return false;
486486
487487 unsigned MOReg = MO.getReg();
875875 const SlotIndexes &Indexes) const {
876876 assert(TargetRegisterInfo::isVirtualRegister(reg));
877877 LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg);
878 assert(!(VRegMask & LaneMask).none());
878 assert((VRegMask & LaneMask).any());
879879 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
880880 for (const MachineOperand &MO : MRI.def_operands(reg)) {
881881 if (!MO.isUndef())
884884 assert(SubReg != 0 && "Undef should only be set on subreg defs");
885885 LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg);
886886 LaneBitmask UndefMask = VRegMask & ~DefMask;
887 if (!(UndefMask & LaneMask).none()) {
887 if ((UndefMask & LaneMask).any()) {
888888 const MachineInstr &MI = *MO.getParent();
889889 bool EarlyClobber = MO.isEarlyClobber();
890890 SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber);
739739 if (MO.isUse()) {
740740 // Reading any undefined lanes?
741741 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
742 if (!(UseMask & ~DefinedLanesMask).none())
742 if ((UseMask & ~DefinedLanesMask).any())
743743 goto CancelKill;
744744 } else if (MO.getSubReg() == 0) {
745745 // Writing to the full register?
979979 dbgs() << " ";
980980 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
981981 dbgs() << PrintReg(Reg);
982 if (!LaneMask.none())
982 if (LaneMask.any())
983983 dbgs() << " L" << PrintLaneMask(LaneMask);
984984 } else {
985985 dbgs() << PrintRegUnit(Reg, &TRI);
13131313 if (MO.isUndef())
13141314 continue;
13151315 unsigned SubReg = MO.getSubReg();
1316 if (SubReg != 0 && !LaneMask.none()
1316 if (SubReg != 0 && LaneMask.any()
13171317 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
13181318 continue;
13191319
143143 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
144144 for (const auto &LI : MBB.liveins()) {
145145 MCSubRegIndexIterator S(LI.PhysReg, TRI);
146 if (LI.LaneMask.all() || (!LI.LaneMask.none() && !S.isValid())) {
146 if (LI.LaneMask.all() || (LI.LaneMask.any() && !S.isValid())) {
147147 addReg(LI.PhysReg);
148148 continue;
149149 }
150150 for (; S.isValid(); ++S) {
151151 unsigned SI = S.getSubRegIndex();
152 if (!(LI.LaneMask & TRI->getSubRegIndexLaneMask(SI)).none())
152 if ((LI.LaneMask & TRI->getSubRegIndexLaneMask(SI)).any())
153153 addReg(S.getSubReg());
154154 }
155155 }
8383 LiveInterval::SubRange *CommonRange;
8484 // A Mask for subregs covered by the subrange but not the current def.
8585 LaneBitmask RM = S.LaneMask & ~Mask;
86 if (!RM.none()) {
86 if (RM.any()) {
8787 // Split the subrange S into two parts: one covered by the current
8888 // def (CommonRange), and the one not affected by it (updated S).
8989 S.LaneMask = RM;
9797 Mask &= ~Common;
9898 }
9999 // Create a new SubRange for subregs we did not cover yet.
100 if (!Mask.none()) {
100 if (Mask.any()) {
101101 LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask);
102102 if (MO.isDef())
103103 createDeadDef(*Indexes, *Alloc, *NewRange, MO);
235235 unsigned SubReg = MO.getSubReg();
236236 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
237237 for (const LiveInterval::SubRange &S : LI.subranges()) {
238 if (!(S.LaneMask & LaneMask).none() && S.Query(Idx).isKill())
238 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
239239 return true;
240240 }
241241 return false;
7878 unsigned Unit = (*Units).first;
7979 LaneBitmask Mask = (*Units).second;
8080 for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
81 if (!(S.LaneMask & Mask).none()) {
81 if ((S.LaneMask & Mask).any()) {
8282 if (Func(Unit, S))
8383 return true;
8484 break;
345345 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
346346 livein_iterator I = find_if(
347347 LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
348 return I != livein_end() && !(I->LaneMask & LaneMask).none();
348 return I != livein_end() && (I->LaneMask & LaneMask).any();
349349 }
350350
351351 void MachineBasicBlock::sortUniqueLiveIns() {
10391039 // this fact anymore => decrement pressure.
10401040 // If the register has just become dead then other uses make it come
10411041 // back to life => increment pressure.
1042 bool Decrement = !P.LaneMask.none();
1042 bool Decrement = P.LaneMask.any();
10431043
10441044 for (const VReg2SUnit &V2SU
10451045 : make_range(VRegUses.find(Reg), VRegUses.end())) {
10581058 );
10591059 }
10601060 } else {
1061 assert(!P.LaneMask.none());
1061 assert(P.LaneMask.any());
10621062 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
10631063 // This may be called before CurrentBottom has been initialized. However,
10641064 // BotRPTracker must have a valid position. We want the value live into the
481481 LaneBitmask LaneMask) const {
482482 report_context_liverange(LR);
483483 report_context_vreg_regunit(VRegUnit);
484 if (!LaneMask.none())
484 if (LaneMask.any())
485485 report_context_lanemask(LaneMask);
486486 }
487487
11711171 report("Live range continues after kill flag", MO, MONum);
11721172 report_context_liverange(LR);
11731173 report_context_vreg_regunit(VRegOrUnit);
1174 if (!LaneMask.none())
1174 if (LaneMask.any())
11751175 report_context_lanemask(LaneMask);
11761176 report_context(UseIdx);
11771177 }
11861186 report("Inconsistent valno->def", MO, MONum);
11871187 report_context_liverange(LR);
11881188 report_context_vreg_regunit(VRegOrUnit);
1189 if (!LaneMask.none())
1189 if (LaneMask.any())
11901190 report_context_lanemask(LaneMask);
11911191 report_context(*VNI);
11921192 report_context(DefIdx);
11951195 report("No live segment at def", MO, MONum);
11961196 report_context_liverange(LR);
11971197 report_context_vreg_regunit(VRegOrUnit);
1198 if (!LaneMask.none())
1198 if (LaneMask.any())
11991199 report_context_lanemask(LaneMask);
12001200 report_context(DefIdx);
12011201 }
12251225 report("Live range continues after dead def flag", MO, MONum);
12261226 report_context_liverange(LR);
12271227 report_context_vreg_regunit(VRegOrUnit);
1228 if (!LaneMask.none())
1228 if (LaneMask.any())
12291229 report_context_lanemask(LaneMask);
12301230 }
12311231 }
16881688 !TRI->hasRegUnit(MOI->getReg(), Reg))
16891689 continue;
16901690 }
1691 if (!LaneMask.none() &&
1691 if (LaneMask.any() &&
16921692 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
16931693 continue;
16941694 hasDef = true;
18341834 if (MOI->isDead())
18351835 hasDeadDef = true;
18361836 }
1837 if (!LaneMask.none() && (LaneMask & SLM).none())
1837 if (LaneMask.any() && (LaneMask & SLM).none())
18381838 continue;
18391839 if (MOI->readsReg())
18401840 hasRead = true;
18531853 if (!hasRead) {
18541854 // When tracking subregister liveness, the main range must start new
18551855 // values on partial register writes, even if there is no read.
1856 if (!MRI->shouldTrackSubRegLiveness(Reg) || !LaneMask.none() ||
1856 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
18571857 !hasSubRegDef) {
18581858 report("Instruction ending live segment doesn't read the register",
18591859 MI);
19401940 LaneBitmask Mask;
19411941 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
19421942 for (const LiveInterval::SubRange &SR : LI.subranges()) {
1943 if (!(Mask & SR.LaneMask).none()) {
1943 if ((Mask & SR.LaneMask).any()) {
19441944 report("Lane masks of sub ranges overlap in live interval", MF);
19451945 report_context(LI);
19461946 }
1947 if (!(SR.LaneMask & ~MaxMask).none()) {
1947 if ((SR.LaneMask & ~MaxMask).any()) {
19481948 report("Subrange lanemask is invalid", MF);
19491949 report_context(LI);
19501950 }
821821 << " into " << PrintLaneMask(Common) << '\n');
822822 LaneBitmask BRest = BMask & ~AMask;
823823 LiveInterval::SubRange *CommonRange;
824 if (!BRest.none()) {
824 if (BRest.any()) {
825825 SB.LaneMask = BRest;
826826 DEBUG(dbgs() << "\t\tReduce Lane to " << PrintLaneMask(BRest)
827827 << '\n');
840840 addSegmentsWithValNo(*CommonRange, BSubValNo, SA, ASubValNo);
841841 AMask &= ~BMask;
842842 }
843 if (!AMask.none()) {
843 if (AMask.any()) {
844844 DEBUG(dbgs() << "\t\tNew Lane " << PrintLaneMask(AMask) << '\n');
845845 LiveRange *NewRange = IntB.createSubRange(Allocator, AMask);
846846 VNInfo *BSubValNo = NewRange->getNextValue(CopyIdx, Allocator);
10601060 SR.createDeadDef(DefIndex, Alloc);
10611061 MaxMask &= ~SR.LaneMask;
10621062 }
1063 if (!MaxMask.none()) {
1063 if (MaxMask.any()) {
10641064 LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);
10651065 SR->createDeadDef(DefIndex, Alloc);
10661066 }
15151515 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
15161516
15171517 // Shrink subregister ranges if necessary.
1518 if (!ShrinkMask.none()) {
1518 if (ShrinkMask.any()) {
15191519 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
15201520 for (LiveInterval::SubRange &S : LI.subranges()) {
15211521 if ((S.LaneMask & ShrinkMask).none())
18201820 RedefVNI(nullptr), OtherVNI(nullptr), ErasableImplicitDef(false),
18211821 Pruned(false), PrunedComputed(false) {}
18221822
1823 bool isAnalyzed() const { return !WriteLanes.none(); }
1823 bool isAnalyzed() const { return WriteLanes.any(); }
18241824 };
18251825
18261826 /// One entry per value number in LI.
21062106 // predecessor, the PHI itself can't introduce any conflicts.
21072107 if (VNI->isPHIDef())
21082108 return CR_Merge;
2109 if (!(V.ValidLanes & OtherV.ValidLanes).none())
2109 if ((V.ValidLanes & OtherV.ValidLanes).any())
21102110 // Overlapping lanes can't be resolved.
21112111 return CR_Impossible;
21122112 else
22602260 Val &OtherV = Other.Vals[V.OtherVNI->id];
22612261 // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
22622262 // its lanes.
2263 if (!(OtherV.WriteLanes & ~V.ValidLanes).none() && TrackSubRegLiveness)
2263 if ((OtherV.WriteLanes & ~V.ValidLanes).any() && TrackSubRegLiveness)
22642264 OtherV.ErasableImplicitDef = false;
22652265 OtherV.Pruned = true;
22662266 LLVM_FALLTHROUGH;
23212321 TaintedLanes &= ~OV.WriteLanes;
23222322 if (!OV.RedefVNI)
23232323 break;
2324 } while (!TaintedLanes.none());
2324 } while (TaintedLanes.any());
23252325 return true;
23262326 }
23272327
23352335 if (!MO.readsReg())
23362336 continue;
23372337 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
2338 if (!(Lanes & TRI->getSubRegIndexLaneMask(S)).none())
2338 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
23392339 return true;
23402340 }
23412341 return false;
27312731 // they have to split into their own subrange.
27322732 LaneBitmask LRest = RMask & ~LaneMask;
27332733 LiveInterval::SubRange *CommonRange;
2734 if (!LRest.none()) {
2734 if (LRest.any()) {
27352735 R.LaneMask = LRest;
27362736 DEBUG(dbgs() << "\t\tReduce Lane to " << PrintLaneMask(LRest) << '\n');
27372737 // Duplicate SubRange for newly merged common stuff.
27462746 LaneMask &= ~RMask;
27472747 }
27482748
2749 if (!LaneMask.none()) {
2749 if (LaneMask.any()) {
27502750 DEBUG(dbgs() << "\t\tNew Lane " << PrintLaneMask(LaneMask) << '\n');
27512751 LI.createSubRangeFrom(Allocator, LaneMask, ToMerge);
27522752 }
27862786 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
27872787 : TRI->getSubRegIndexLaneMask(DstIdx);
27882788 // LHS must support subregs or we wouldn't be in this codepath.
2789 assert(!Mask.none());
2789 assert(Mask.any());
27902790 LHS.createSubRangeFrom(Allocator, Mask, LHS);
27912791 } else if (DstIdx != 0) {
27922792 // Transform LHS lanemasks to new register class if necessary.
2626 const MachineRegisterInfo &MRI, unsigned Reg,
2727 LaneBitmask PrevMask, LaneBitmask NewMask) {
2828 assert((PrevMask & ~NewMask).none() && "Must not remove bits");
29 if (!PrevMask.none() || NewMask.none())
29 if (PrevMask.any() || NewMask.none())
3030 return;
3131
3232 PSetIterator PSetI = MRI.getPressureSets(Reg);
4040 const MachineRegisterInfo &MRI, unsigned Reg,
4141 LaneBitmask PrevMask, LaneBitmask NewMask) {
4242 //assert((NewMask & !PrevMask) == 0 && "Must not add bits");
43 if (!NewMask.none() || PrevMask.none())
43 if (NewMask.any() || PrevMask.none())
4444 return;
4545
4646 PSetIterator PSetI = MRI.getPressureSets(Reg);
111111 void RegPressureTracker::increaseRegPressure(unsigned RegUnit,
112112 LaneBitmask PreviousMask,
113113 LaneBitmask NewMask) {
114 if (!PreviousMask.none() || NewMask.none())
114 if (PreviousMask.any() || NewMask.none())
115115 return;
116116
117117 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
338338 static void addRegLanes(SmallVectorImpl &RegUnits,
339339 RegisterMaskPair Pair) {
340340 unsigned RegUnit = Pair.RegUnit;
341 assert(!Pair.LaneMask.none());
341 assert(Pair.LaneMask.any());
342342 auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
343343 return Other.RegUnit == RegUnit;
344344 });
364364 static void removeRegLanes(SmallVectorImpl &RegUnits,
365365 RegisterMaskPair Pair) {
366366 unsigned RegUnit = Pair.RegUnit;
367 assert(!Pair.LaneMask.none());
367 assert(Pair.LaneMask.any());
368368 auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
369369 return Other.RegUnit == RegUnit;
370370 });
670670
671671 void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
672672 SmallVectorImpl &LiveInOrOut) {
673 assert(!Pair.LaneMask.none());
673 assert(Pair.LaneMask.any());
674674
675675 unsigned RegUnit = Pair.RegUnit;
676676 auto I = find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
734734 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
735735
736736 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
737 if (!LiveOut.none()) {
737 if (LiveOut.any()) {
738738 discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
739739 // Retroactively model effects on pressure of the live out lanes.
740740 increaseSetPressure(CurrSetPressure, *MRI, Reg, LaneBitmask::getNone(),
759759 // Generate liveness for uses.
760760 for (const RegisterMaskPair &Use : RegOpers.Uses) {
761761 unsigned Reg = Use.RegUnit;
762 assert(!Use.LaneMask.none());
762 assert(Use.LaneMask.any());
763763 LaneBitmask PreviousMask = LiveRegs.insert(Use);
764764 LaneBitmask NewMask = PreviousMask | Use.LaneMask;
765765 if (NewMask == PreviousMask)
788788 // Discover live outs if this may be the first occurance of this register.
789789 if (RequireIntervals) {
790790 LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
791 if (!LiveOut.none())
791 if (LiveOut.any())
792792 discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
793793 }
794794 }
865865 unsigned Reg = Use.RegUnit;
866866 LaneBitmask LiveMask = LiveRegs.contains(Reg);
867867 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
868 if (!LiveIn.none()) {
868 if (LiveIn.any()) {
869869 discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
870870 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
871871 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
873873 // Kill liveness at last uses.
874874 if (RequireIntervals) {
875875 LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
876 if (!LastUseMask.none()) {
876 if (LastUseMask.any()) {
877877 LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
878878 decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
879879 }
3333 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
3434 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
3535 LaneBitmask UnitMask = (*RUI).second;
36 if (UnitMask.none() || !(LaneMask & UnitMask).none())
36 if (UnitMask.none() || (LaneMask & UnitMask).any())
3737 RegUnitsAvailable.reset((*RUI).first);
3838 }
3939 }
448448 continue;
449449 }
450450
451 if (!(LaneMask & DefLaneMask).none()) {
451 if ((LaneMask & DefLaneMask).any()) {
452452 SUnit *UseSU = I->SU;
453453 MachineInstr *Use = UseSU->getInstr();
454454 SDep Dep(SU, SDep::Data, Reg);
460460
461461 LaneMask &= ~KillLaneMask;
462462 // If we found a Def for all lanes of this use, remove it from the list.
463 if (!LaneMask.none()) {
463 if (LaneMask.any()) {
464464 I->LaneMask = LaneMask;
465465 ++I;
466466 } else
506506 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
507507 V2SU.SU = SU;
508508 V2SU.LaneMask = OverlapMask;
509 if (!NonOverlapMask.none())
509 if (NonOverlapMask.any())
510510 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
511511 }
512512 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
513 if (!LaneMask.none())
513 if (LaneMask.any())
514514 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
515515 }
516516
424424 }
425425 }
426426 for (LiveInterval::SubRange &S : LI.subranges())
427 if (!(S.LaneMask & LM).none())
427 if ((S.LaneMask & LM).any())
428428 S.createDeadDef(Def, LIS.getVNInfoAllocator());
429429 }
430430 }
341341 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
342342 // See if any of the relevant subregister liveranges is defined at this point.
343343 for (const LiveInterval::SubRange &SR : LI.subranges()) {
344 if (!(SR.LaneMask & UseMask).none() && SR.liveAt(BaseIndex))
344 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
345345 return false;
346346 }
347347 return true;
239239 }
240240 for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
241241 LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
242 if (!(M & I.LaneMask).none())
242 if ((M & I.LaneMask).any())
243243 Tmp.insert({S.getSubReg(), 0});
244244 }
245245 }
368368 if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
369369 return false;
370370 LaneBitmask SLM = getLaneMask(DR, DSR);
371 return !(SLM & LM).none();
371 return (SLM & LM).any();
372372 };
373373
374374 // The splitting step will create pairs of predicated definitions without
661661 RegisterRef NR = normalize(RR);
662662 auto F = Masks.find(NR.Reg);
663663 if (F != Masks.end()) {
664 if (!(F->second & NR.Mask).none())
664 if ((F->second & NR.Mask).any())
665665 return true;
666666 }
667667 if (CheckUnits) {
10881088 RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
10891089 if (AR.Reg == BR.Reg) {
10901090 LaneBitmask M = AR.Mask & BR.Mask;
1091 return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
1091 return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
10921092 }
10931093 #ifndef NDEBUG
10941094 RegisterRef NAR = normalizeRef(AR);
12201220 // while the lane mask of r2 in d1 may be 0b0001.
12211221 LaneBitmask LA = PA.second & RA.Mask;
12221222 LaneBitmask LB = PB.second & RB.Mask;
1223 if (!LA.none() && !LB.none()) {
1223 if (LA.any() && LB.any()) {
12241224 unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
12251225 // If register units were guaranteed to only have 1 bit in any lane
12261226 // mask, the code below would not be necessary. This is because LA
12311231 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
12321232 LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
12331233 LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
1234 if (!(MaskA & MaskB & RC.LaneMask).none())
1234 if ((MaskA & MaskB & RC.LaneMask).any())
12351235 return true;
12361236 }
12371237
404404 RegisterRef() : RegisterRef(0) {}
405405 explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
406406 : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
407 operator bool() const { return Reg != 0 && !Mask.none(); }
407 operator bool() const { return Reg != 0 && Mask.any(); }
408408 bool operator== (const RegisterRef &RR) const {
409409 return Reg == RR.Reg && Mask == RR.Mask;
410410 }
470470 return K == 0 ? LaneBitmask::getAll() : get(K);
471471 }
472472 uint32_t getIndexForLaneMask(LaneBitmask LM) {
473 assert(!LM.none());
473 assert(LM.any());
474474 return LM.all() ? 0 : insert(LM);
475475 }
476476 uint32_t getIndexForLaneMask(LaneBitmask LM) const {
477 assert(!LM.none());
477 assert(LM.any());
478478 return LM.all() ? 0 : find(LM);
479479 }
480480 PackedRegisterRef pack(RegisterRef RR) {
709709 }
710710 do {
711711 LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
712 if (!(M & P.second).none())
712 if ((M & P.second).any())
713713 LV.push_back(RegisterRef(S.getSubReg()));
714714 ++S;
715715 } while (S.isValid());
758758 }
759759 do {
760760 LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
761 if (!(M & I.LaneMask).none())
761 if ((M & I.LaneMask).any())
762762 LV.set(S.getSubReg());
763763 ++S;
764764 } while (S.isValid());
103103
104104 LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
105105 // Already computed?
106 if (!LaneMask.none())
106 if (LaneMask.any())
107107 return LaneMask;
108108
109109 // Recursion guard, shouldn't be required.
113113 LaneBitmask M;
114114 for (const auto &C : Composed)
115115 M |= C.second->computeLaneMask();
116 assert(!M.none() && "Missing lane mask, sub-register cycle?");
116 assert(M.any() && "Missing lane mask, sub-register cycle?");
117117 LaneMask = M;
118118 return LaneMask;
119119 }
12661266 SrcMask = LaneBitmask::getNone();
12671267 }
12681268 }
1269 if (!SrcMask.none()) {
1269 if (SrcMask.any()) {
12701270 MaskRolPair MaskRol = { SrcMask, RotateLeft };
12711271 LaneTransforms.push_back(MaskRol);
12721272 }
775775 " --IdxA; assert(IdxA < " << SubRegIndices.size()
776776 << " && \"Subregister index out of bounds\");\n"
777777 " LaneBitmask Result;\n"
778 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
778 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
779779 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n"
780780 " if (unsigned S = Ops->RotateLeft)\n"
781781 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n"
792792 " --IdxA; assert(IdxA < " << SubRegIndices.size()
793793 << " && \"Subregister index out of bounds\");\n"
794794 " LaneBitmask Result;\n"
795 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
795 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
796796 " LaneBitmask::Type M = LaneMask.getAsInteger();\n"
797797 " if (unsigned S = Ops->RotateLeft)\n"
798798 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n"