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PR32288: More efficient encoding for DWARF expr subregister access. Citing http://bugs.llvm.org/show_bug.cgi?id=32288 The DWARF generated by LLVM includes this location: 0x55 0x93 0x04 DW_OP_reg5 DW_OP_piece(4) When GCC's DWARF is simply 0x55 (DW_OP_reg5) without the DW_OP_piece. I believe it's reasonable to assume the DWARF consumer knows which part of a register logically holds the value (low bytes, high bytes, how many bytes, etc) for a primitive value like an integer. This patch gets rid of the redundant DW_OP_piece when a subregister is at offset 0. It also adds previously missing subregister masking when a subregister is followed by another operation. (This reapplies r297960 with two additional testcase updates). rdar://problem/31069390 https://reviews.llvm.org/D31010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297965 91177308-0d34-0410-b5e6-96231b3b80d8 Adrian Prantl 3 years ago
13 changed file(s) with 56 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
6363 EmitOp(dwarf::DW_OP_constu);
6464 EmitUnsigned(ShiftBy);
6565 EmitOp(dwarf::DW_OP_shr);
66 }
67
68 void DwarfExpression::AddAnd(unsigned Mask) {
69 EmitOp(dwarf::DW_OP_constu);
70 EmitUnsigned(Mask);
71 EmitOp(dwarf::DW_OP_and);
6672 }
6773
6874 bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI,
229235 unsigned FragmentOffsetInBits) {
230236 while (ExprCursor) {
231237 auto Op = ExprCursor.take();
238
239 // If we need to mask out a subregister, do it now, unless the next
240 // operation would emit an OpPiece anyway.
241 if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
242 maskSubRegister();
243
232244 switch (Op->getOp()) {
233245 case dwarf::DW_OP_LLVM_fragment: {
234246 unsigned SizeInBits = Op->getArg(1);
284296 }
285297 }
286298
299 /// Add masking operations to stencil out a subregister.
300 void DwarfExpression::maskSubRegister() {
301 assert(SubRegisterSizeInBits && "no subregister was registered");
302 if (SubRegisterOffsetInBits > 0)
303 AddShr(SubRegisterOffsetInBits);
304 uint64_t Mask = (1UL << SubRegisterSizeInBits) - 1;
305 AddAnd(Mask);
306 }
307
308
287309 void DwarfExpression::finalize() {
288 if (SubRegisterSizeInBits)
289 AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
310 // Emit any outstanding DW_OP_piece operations to mask out subregisters.
311 if (SubRegisterSizeInBits == 0)
312 return;
313 // Don't emit a DW_OP_piece for a subregister at offset 0.
314 if (SubRegisterOffsetInBits == 0)
315 return;
316 AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
290317 }
291318
292319 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
9797 SubRegisterSizeInBits = SizeInBits;
9898 SubRegisterOffsetInBits = OffsetInBits;
9999 }
100
101 /// Add masking operations to stencil out a subregister.
102 void maskSubRegister();
100103
101104 public:
102105 DwarfExpression(unsigned DwarfVersion) : DwarfVersion(DwarfVersion) {}
125128 /// is at the top of the DWARF stack.
126129 void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0);
127130
128 /// Emit a shift-right dwarf expression.
131 /// Emit a shift-right dwarf operation.
129132 void AddShr(unsigned ShiftBy);
133 /// Emit a bitwise and dwarf operation.
134 void AddAnd(unsigned Mask);
130135
131136 /// Emit a DW_OP_stack_value, if supported.
132137 ///
22 ; Test dwarf reg no for s16
33 ;CHECK: super-register DW_OP_regx
44 ;CHECK-NEXT: 264
5 ;CHECK-NEXT: DW_OP_piece
6 ;CHECK-NEXT: 4
75
86 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
97 target triple = "thumbv7-apple-macosx10.6.7"
99
1010 ; CHECK: 0x00000000: Beginning address offset:
1111 ; CHECK-NEXT: Ending address offset:
12 ; CHECK-NEXT: Location description: 90 {{.. .. .. .. $}}
12 ; CHECK-NEXT: Location description: 90 {{.. .. $}}
1313
1414 define void @_Z3foov() optsize ssp !dbg !1 {
1515 entry:
44 ; The S registers on ARM are expressed as pieces of their super-registers in DWARF.
55 ;
66 ; 0x90 DW_OP_regx of super-register
7 ; 0x93 DW_OP_piece
8 ; 0x9d DW_OP_bit_piece
9 ; CHECK: Location description: 90 {{.. .. ((93 ..)|(9d .. ..)) $}}
7 ; CHECK: Location description: 90
108
119 define void @_Z3foov() optsize ssp !dbg !1 {
1210 entry:
1818 ; AS in 26163, we expect two ranges (as opposed to one), the first one being zero sized
1919 ;
2020 ;
21 ; CHECK: 0x00000025: Beginning address offset: 0x0000000000000004
21 ; CHECK: Beginning address offset: 0x0000000000000004
2222 ; CHECK: Ending address offset: 0x0000000000000004
2323 ; CHECK: Location description: 10 03 93 04 55 93 02
2424 ; constu 0x00000003, piece 0x00000004, rdi, piece 0x00000002
3333 ; CHECK: Beginning address offset: [[C1]]
3434 ; CHECK: Ending address offset: [[C2:.*]]
3535 ; CHECK: Location description: 11 07
36 ; rax, piece 0x00000004
36 ; rax
3737 ; CHECK: Beginning address offset: [[C2]]
3838 ; CHECK: Ending address offset: [[R1:.*]]
39 ; CHECK: Location description: 50 93 04
39 ; CHECK: Location description: 50
4040 ; rdi+0
4141 ; CHECK: Beginning address offset: [[R1]]
4242 ; CHECK: Ending address offset: [[R2:.*]]
1515 ; ASM: .Ldebug_loc1:
1616 ; ASM-NEXT: .quad .Lfunc_begin0-.Lfunc_begin0
1717 ; ASM-NEXT: .quad [[argc_range_end]]-.Lfunc_begin0
18 ; ASM-NEXT: .short 3 # Loc expr size
18 ; ASM-NEXT: .short 1 # Loc expr size
1919 ; ASM-NEXT: .byte 82 # super-register DW_OP_reg2
20 ; ASM-NEXT: .byte 147 # DW_OP_piece
21 ; ASM-NEXT: .byte 4 # 4
2220
2321 ; argc is the first formal parameter.
2422 ; DWARF: .debug_info contents:
2927 ; DWARF: .debug_loc contents:
3028 ; DWARF: [[argc_loc_offset]]: Beginning address offset: 0x0000000000000000
3129 ; DWARF-NEXT: Ending address offset: 0x0000000000000013
32 ; DWARF-NEXT: Location description: 52 93 04
30 ; DWARF-NEXT: Location description: 52
3331
3432 ; ModuleID = 't.cpp'
3533 source_filename = "test/DebugInfo/X86/dbg-value-regmask-clobber.ll"
77
88 ; CHECK: Beginning address offset: 0x0000000000000000
99 ; CHECK: Ending address offset: 0x0000000000000004
10 ; CHECK: Location description: 50 10 01 1c 93 04
11 ; rax, constu 0x00000001, minus, piece 0x00000004
10 ; CHECK: Location description: 50 10 ff ff ff ff 0f 1a 10 01 1c
11 ; rax, constu 0xffffffff, and, constu 0x00000001, minus
1212 source_filename = "minus.c"
1313 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
1414 target triple = "x86_64-apple-macosx10.12.0"
2929 ; CHECK-NEXT: {{^$}}
3030 ; CHECK-NEXT: Beginning address index: 3
3131 ; CHECK-NEXT: Length: 25
32 ; CHECK-NEXT: Location description: 50 93 04
32 ; CHECK-NEXT: Location description: 50
3333 ; CHECK: [[E]]: Beginning address index: 4
3434 ; CHECK-NEXT: Length: 19
35 ; CHECK-NEXT: Location description: 50 93 04
35 ; CHECK-NEXT: Location description: 50
3636 ; CHECK: [[B]]: Beginning address index: 5
3737 ; CHECK-NEXT: Length: 17
38 ; CHECK-NEXT: Location description: 50 93 04
38 ; CHECK-NEXT: Location description: 50
3939 ; CHECK: [[D]]: Beginning address index: 6
4040 ; CHECK-NEXT: Length: 17
41 ; CHECK-NEXT: Location description: 50 93 04
41 ; CHECK-NEXT: Location description: 50
4242
4343 ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo)
4444 ; HDR-NOT: .rela.{{.*}}.dwo
77 ; CHECK-NEXT: DW_AT_location [DW_FORM_data4]
88 ; CHECK-NEXT: DW_AT_name{{.*}}"a"
99 ; CHECK: .debug_loc contents:
10 ; rax, piece 0x00000004
11 ; CHECK: Location description: 50 93 04
10 ; rax
11 ; CHECK: Location description: 50
1212 ; SANITY: DBG_VALUE
1313 ; SANITY-NOT: DBG_VALUE
1414 ; ModuleID = 'test.ll'
33 ; being in its superregister.
44
55 ; CHECK: .byte 80 # super-register DW_OP_reg0
6 ; CHECK-NEXT: .byte 147 # DW_OP_piece
7 ; CHECK-NEXT: .byte 2 # 2
6 ; No need to a piece at offset 0.
7 ; CHECK-NOT: DW_OP_piece
8 ; CHECK-NOT: DW_OP_bit_piece
89
910 define i16 @f(i16 signext %zzz) nounwind !dbg !1 {
1011 entry:
11 ; RUN: llvm-dwarfdump %t.o | FileCheck %s
22 ;
33 ; Test that on x86_64, the 32-bit subregister esi is emitted as
4 ; DW_OP_piece 32 of the 64-bit rsi.
4 ; subregister of the 64-bit rsi.
55 ;
66 ; rdar://problem/16015314
77 ;
1010 ; CHECK-NEXT: DW_AT_location [DW_FORM_data4] (0x00000000)
1111 ; CHECK-NEXT: DW_AT_name [DW_FORM_strp]{{.*}} "a"
1212 ; CHECK: .debug_loc contents:
13 ; rsi, piece 0x00000004
14 ; CHECK: Location description: 54 93 04
13 ; rsi
14 ; CHECK: Location description: 54
1515 ;
1616 ; struct bar {
1717 ; int a;