llvm.org GIT mirror llvm / 307e97d
[AArch64] Normalize all constants to build a vector. The value of constant operands will be truncated to fit element width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212428 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Qin 6 years ago
2 changed file(s) with 28 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
51805180 return Op;
51815181 }
51825182
5183 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5184 // be truncated to fit element width.
5185 static SDValue NormalizeBuildVector(SDValue Op,
5186 SelectionDAG &DAG) {
5187 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5188 SDLoc dl(Op);
5189 EVT VT = Op.getValueType();
5190 EVT EltTy= VT.getVectorElementType();
5191
5192 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5193 return Op;
5194
5195 SmallVector Ops;
5196 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5197 SDValue Lane = Op.getOperand(I);
5198 if (Lane.getOpcode() == ISD::Constant) {
5199 APInt LowBits(EltTy.getSizeInBits(),
5200 cast(Lane)->getZExtValue());
5201 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5202 }
5203 Ops.push_back(Lane);
5204 }
5205 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5206 }
5207
51835208 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
51845209 SelectionDAG &DAG) const {
5185 BuildVectorSDNode *BVN = cast(Op.getNode());
51865210 SDLoc dl(Op);
51875211 EVT VT = Op.getValueType();
5212 Op = NormalizeBuildVector(Op, DAG);
5213 BuildVectorSDNode *BVN = cast(Op.getNode());
51885214
51895215 APInt CnstBits(VT.getSizeInBits(), 0);
51905216 APInt UndefBits(VT.getSizeInBits(), 0);
3535
3636 define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
3737 ; CHECK-LABEL: build_all_zero:
38 ; CHECK: movn w[[GREG:[0-9]+]], #0x517f
38 ; CHECK: movz w[[GREG:[0-9]+]], #0xae80
3939 ; CHECK-NEXT: fmov s[[FREG:[0-9]+]], w[[GREG]]
4040 ; CHECK-NEXT: mul.8h v0, v0, v[[FREG]]
4141 %b = add <8 x i16> %a,