llvm.org GIT mirror llvm / 3062a31
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp Printing rounding control. Enncoding for EVEX_RC (rounding control). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 6 years ago
12 changed file(s) with 426 addition(s) and 141 deletion(s). Raw diff Collapse all Expand all
27112711
27122712 // Vector convert
27132713 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
2714 def int_x86_avx512_cvt_ps2dq_512 : GCCBuiltin<"__builtin_ia32_cvtps2dq512">,
2715 Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty], [IntrNoMem]>;
2716 def int_x86_avx512_cvtdq2_ps_512 : GCCBuiltin<"__builtin_ia32_cvtdq2ps512">,
2717 Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty], [IntrNoMem]>;
2714 def int_x86_avx512_mask_cvttps2dq_512: GCCBuiltin<"__builtin_ia32_cvttps2dq512_mask">,
2715 Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
2716 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2717 def int_x86_avx512_mask_cvttps2udq_512: GCCBuiltin<"__builtin_ia32_cvttps2udq512_mask">,
2718 Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
2719 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2720 def int_x86_avx512_mask_cvttpd2dq_512: GCCBuiltin<"__builtin_ia32_cvttpd2dq512_mask">,
2721 Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
2722 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
2723 def int_x86_avx512_mask_cvttpd2udq_512: GCCBuiltin<"__builtin_ia32_cvttpd2udq512_mask">,
2724 Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
2725 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
2726 def int_x86_avx512_mask_rndscale_ps_512: GCCBuiltin<"__builtin_ia32_rndscaleps_mask">,
2727 Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty,
2728 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2729 def int_x86_avx512_mask_rndscale_pd_512: GCCBuiltin<"__builtin_ia32_rndscalepd_mask">,
2730 Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty,
2731 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
2732 def int_x86_avx512_mask_cvtps2dq_512: GCCBuiltin<"__builtin_ia32_cvtps2dq512_mask">,
2733 Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
2734 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2735 def int_x86_avx512_mask_cvtpd2dq_512: GCCBuiltin<"__builtin_ia32_cvtpd2dq512_mask">,
2736 Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
2737 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
2738 def int_x86_avx512_mask_cvtps2udq_512: GCCBuiltin<"__builtin_ia32_cvtps2udq512_mask">,
2739 Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
2740 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2741 def int_x86_avx512_mask_cvtpd2udq_512: GCCBuiltin<"__builtin_ia32_cvtpd2udq512_mask">,
2742 Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
2743 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
2744 def int_x86_avx512_mask_cvtdq2ps_512 : GCCBuiltin<"__builtin_ia32_cvtdq2ps512_mask">,
2745 Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_v16f32_ty,
2746 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
2747 def int_x86_avx512_mask_cvtdq2pd_512 : GCCBuiltin<"__builtin_ia32_cvtdq2pd512_mask">,
2748 Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_v8f64_ty,
2749 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
27182750 }
27192751
27202752 // Vector load with broadcast
28192851 Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
28202852 [IntrNoMem]>;
28212853
2822 def int_x86_avx512_rndscale_ps_512 : GCCBuiltin<"__builtin_ia32_rndscaleps512">,
2823 Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
2824 llvm_i32_ty], [IntrNoMem]>;
2825 def int_x86_avx512_rndscale_pd_512 : GCCBuiltin<"__builtin_ia32_rndscalepd512">,
2826 Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
2827 llvm_i32_ty], [IntrNoMem]>;
2828
28292854 def int_x86_avx512_sqrt_pd_512 : GCCBuiltin<"__builtin_ia32_sqrtpd512">,
28302855 Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty], [IntrNoMem]>;
28312856 def int_x86_avx512_sqrt_ps_512 : GCCBuiltin<"__builtin_ia32_sqrtps512">,
30743099
30753100 // Misc.
30763101 let TargetPrefix = "x86" in {
3077 def int_x86_avx512_cmpeq_pi_512 : GCCBuiltin<"__builtin_ia32_cmpeqpi512">,
3078 Intrinsic<[llvm_i16_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
3102 def int_x86_avx512_mask_cmp_ps_512 : GCCBuiltin<"__builtin_ia32_cmpps512_mask">,
3103 Intrinsic<[llvm_i16_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty,
3104 llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
3105 def int_x86_avx512_mask_cmp_pd_512 : GCCBuiltin<"__builtin_ia32_cmppd512_mask">,
3106 Intrinsic<[llvm_i8_ty], [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i32_ty,
3107 llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
3108
3109 def int_x86_avx512_mask_pcmpeq_d_512 : GCCBuiltin<"__builtin_ia32_pcmpeqd512_mask">,
3110 Intrinsic<[llvm_i16_ty], [llvm_v16i32_ty, llvm_v16i32_ty, llvm_i16_ty],
30793111 [IntrNoMem]>;
3080 def int_x86_avx512_and_pi : GCCBuiltin<"__builtin_ia32_andpi512">,
3081 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
3082 [IntrNoMem]>;
3112 def int_x86_avx512_mask_pcmpeq_q_512 : GCCBuiltin<"__builtin_ia32_pcmpeqq512_mask">,
3113 Intrinsic<[llvm_i8_ty], [llvm_v8i64_ty, llvm_v8i64_ty, llvm_i8_ty],
3114 [IntrNoMem]>;
3115 def int_x86_avx512_mask_pand_d_512 : GCCBuiltin<"__builtin_ia32_pandd512_mask">,
3116 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
3117 llvm_v16i32_ty, llvm_i16_ty],
3118 [IntrNoMem]>;
3119 def int_x86_avx512_mask_pand_q_512 : GCCBuiltin<"__builtin_ia32_pandq512_mask">,
3120 Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
3121 llvm_v8i64_ty, llvm_i8_ty],
3122 [IntrNoMem]>;
30833123 }
30843124
30853125 //===----------------------------------------------------------------------===//
122122 }
123123 }
124124
125 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
126 raw_ostream &O) {
127 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
128 switch (Imm) {
129 case 0: O << "{rn-sae}"; break;
130 case 1: O << "{rd-sae}"; break;
131 case 2: O << "{ru-sae}"; break;
132 case 3: O << "{rz-sae}"; break;
133
134 default: llvm_unreachable("Invalid AVX-512 rounding control argument!");
135 }
136 }
125137 /// printPCRelImm - This is used to print an immediate value that ends up
126138 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
127139 /// print slightly differently than normal immediates. For example, a $ is not
4242 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
4343 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4444 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4546
4647 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
4748 printMemReference(MI, OpNo, O);
112112 }
113113 }
114114
115 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
116 raw_ostream &O) {
117 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
118 switch (Imm) {
119 case 0: O << "{rn-sae}"; break;
120 case 1: O << "{rd-sae}"; break;
121 case 2: O << "{ru-sae}"; break;
122 case 3: O << "{rz-sae}"; break;
123
124 default: llvm_unreachable("Invalid AVX-512 rounding control argument!");
125 }
126 }
127
115128 /// printPCRelImm - This is used to print an immediate value that ends up
116129 /// being encoded as a pc-relative value.
117130 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
3939 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
4040 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4141 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4243
4344 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
4445 O << "opaque ptr ";
534534 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
535535 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
536536 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
537 bool HasEVEX_RC = false;
537538
538539 // VEX_R: opcode externsion equivalent to REX.R in
539540 // 1's complement (inverted) form
609610 // EVEX_b
610611 unsigned char EVEX_b = 0;
611612
613 // EVEX_rc
614 unsigned char EVEX_rc = 0;
615
612616 // EVEX_aaa
613617 unsigned char EVEX_aaa = 0;
614618
675679
676680 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
677681 unsigned NumOps = Desc.getNumOperands();
682 unsigned RcOperand = NumOps-1;
678683 unsigned CurOp = 0;
679684 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
680685 ++CurOp;
833838 VEX_X = 0x0;
834839 CurOp++;
835840 if (HasVEX_4VOp3)
836 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
841 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
842 if (EVEX_b) {
843 assert(RcOperand >= CurOp);
844 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
845 HasEVEX_RC = true;
846 }
837847 break;
838848 case X86II::MRMDestReg:
839849 // MRMDestReg instructions forms:
933943 (VEX_4V << 3) |
934944 (EVEX_U << 2) |
935945 VEX_PP, CurByte, OS);
936 EmitByte((EVEX_z << 7) |
937 (EVEX_L2 << 6) |
938 (VEX_L << 5) |
939 (EVEX_b << 4) |
940 (EVEX_V2 << 3) |
941 EVEX_aaa, CurByte, OS);
946 if (HasEVEX_RC)
947 EmitByte((EVEX_z << 7) |
948 (EVEX_rc << 5) |
949 (EVEX_b << 4) |
950 (EVEX_V2 << 3) |
951 EVEX_aaa, CurByte, OS);
952 else
953 EmitByte((EVEX_z << 7) |
954 (EVEX_L2 << 6) |
955 (VEX_L << 5) |
956 (EVEX_b << 4) |
957 (EVEX_V2 << 3) |
958 EVEX_aaa, CurByte, OS);
942959 }
943960 }
944961
12051222 // It uses the EVEX.aaa field?
12061223 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
12071224 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1208
1225 bool HasEVEX_B = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B);
1226
12091227 // Determine where the memory operand starts, if present.
12101228 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
12111229 if (MemoryOperand != -1) MemoryOperand += CurOp;
13011319 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
13021320 if (HasVEX_4VOp3)
13031321 ++CurOp;
1322 // do not count the rounding control operand
1323 if (HasEVEX_B)
1324 NumOps--;
13041325 break;
13051326
13061327 case X86II::MRMSrcMem: {
801801
802802 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
803803 multiclass avx512_cmp_packed
804 X86MemOperand x86memop, Operand CC,
805 SDNode OpNode, ValueType vt, string asm,
806 string asm_alt, Domain d> {
804 X86MemOperand x86memop, ValueType vt,
805 string suffix, Domain d> {
807806 def rri : AVX512PIi8<0xC2, MRMSrcReg,
808 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
809 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
807 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
808 !strconcat("vcmp${cc}", suffix,
809 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
812 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc, i32imm:$sae),
813 !strconcat("vcmp${cc}", suffix,
814 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
815 [], d>, EVEX_B;
810816 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
811 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
817 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
818 !strconcat("vcmp", suffix,
819 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
812820 [(set KRC:$dst,
813 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
821 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
814822
815823 // Accept explicit immediate argument form instead of comparison code.
816824 let neverHasSideEffects = 1 in {
817825 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
818826 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
819 asm_alt, [], d>;
827 !strconcat("vcmp", suffix,
828 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
820829 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
821830 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
822 asm_alt, [], d>;
831 !strconcat("vcmp", suffix,
832 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
823833 }
824834 }
825835
826 defm VCMPPSZ : avx512_cmp_packed
827 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
828 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
829 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
830 defm VCMPPDZ : avx512_cmp_packed
831 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
832 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
833 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
836 defm VCMPPSZ : avx512_cmp_packed2,
837 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
838 defm VCMPPDZ : avx512_cmp_packed
839 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
834840 EVEX_CD8<64, CD8VF>;
835841
836842 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
848854 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
849855 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
850856 imm:$cc), VK8)>;
851
857
858 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
859 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
860 FROUND_NO_EXC)),
861 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
862 (I8Imm imm:$cc), (i32 0)), GR16)>;
863
864 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
865 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
866 FROUND_NO_EXC)),
867 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
868 (I8Imm imm:$cc), (i32 0)), GR8)>;
869
870 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
871 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
872 FROUND_CURRENT)),
873 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
874 (I8Imm imm:$cc)), GR16)>;
875
876 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
877 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
878 FROUND_CURRENT)),
879 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
880 (I8Imm imm:$cc)), GR8)>;
881
852882 // Mask register copy, including
853883 // - copy between mask registers
854884 // - load/store mask registers
27032733 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
27042734 [(set DstRC:$dst,
27052735 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2736 def rrb : AVX512PI
2737 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2738 [], d>, EVEX, EVEX_B;
27062739 let mayLoad = 1 in
27072740 def rm : AVX512PI
27082741 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
27112744 } // neverHasSideEffects = 1
27122745 }
27132746
2747 multiclass avx512_vcvtt_fp opc, string asm, RegisterClass SrcRC,
2748 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2749 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2750 Domain d> {
2751 let neverHasSideEffects = 1 in {
2752 def rr : AVX512PI
2753 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2754 [(set DstRC:$dst,
2755 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2756 let mayLoad = 1 in
2757 def rm : AVX512PI
2758 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2759 [(set DstRC:$dst,
2760 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2761 } // neverHasSideEffects = 1
2762 }
2763
2764
27142765 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
27152766 memopv8f64, f512mem, v8f32, v8f64,
27162767 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
27352786 SSEPackedDouble>, EVEX_V512, XS,
27362787 EVEX_CD8<32, CD8VH>;
27372788
2738 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2789 defm VCVTTPS2DQZ : avx512_vcvtt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
27392790 memopv16f32, f512mem, v16i32, v16f32,
27402791 SSEPackedSingle>, EVEX_V512, XS,
27412792 EVEX_CD8<32, CD8VF>;
27422793
2743 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2794 defm VCVTTPD2DQZ : avx512_vcvtt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
27442795 memopv8f64, f512mem, v8i32, v8f64,
27452796 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
27462797 EVEX_CD8<64, CD8VF>;
27472798
2748 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2799 defm VCVTTPS2UDQZ : avx512_vcvtt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
27492800 memopv16f32, f512mem, v16i32, v16f32,
27502801 SSEPackedSingle>, EVEX_V512,
27512802 EVEX_CD8<32, CD8VF>;
27522803
2753 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2804 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2805 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2806 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2807 (VCVTTPS2UDQZrr VR512:$src)>;
2808
2809 defm VCVTTPD2UDQZ : avx512_vcvtt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
27542810 memopv8f64, f512mem, v8i32, v8f64,
27552811 SSEPackedDouble>, EVEX_V512, VEX_W,
27562812 EVEX_CD8<64, CD8VF>;
27572813
2814 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2815 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2816 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2817 (VCVTTPD2UDQZrr VR512:$src)>;
2818
27582819 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
27592820 memopv4i64, f256mem, v8f64, v8i32,
27602821 SSEPackedDouble>, EVEX_V512, XS,
27702831 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
27712832
27722833
2773 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2774 (VCVTDQ2PSZrr VR512:$src)>;
2775 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2776 (VCVTDQ2PSZrm addr:$src)>;
2777
2778 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2779 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2780 [(set VR512:$dst,
2781 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2782 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2783 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2784 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2785 [(set VR512:$dst,
2786 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2787 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2788
2834 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2835 (v16f32 immAllZerosV), (i16 -1), imm:$rc)),
2836 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2837
2838
2839 multiclass avx512_vcvt_fp2int opc, string asm, RegisterClass SrcRC,
2840 RegisterClass DstRC, PatFrag mem_frag,
2841 X86MemOperand x86memop, Domain d> {
2842 let neverHasSideEffects = 1 in {
2843 def rr : AVX512PI
2844 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2845 [], d>, EVEX;
2846 def rrb : AVX512PI
2847 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2848 [], d>, EVEX, EVEX_B;
2849 let mayLoad = 1 in
2850 def rm : AVX512PI
2851 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2852 [], d>, EVEX;
2853 } // neverHasSideEffects = 1
2854 }
2855
2856 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2857 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2858 EVEX_V512, EVEX_CD8<32, CD8VF>;
2859 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2860 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2861 EVEX_V512, EVEX_CD8<64, CD8VF>;
2862
2863 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2864 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2865 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2866
2867 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2868 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2869 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2870
2871 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2872 memopv16f32, f512mem, SSEPackedSingle>,
2873 EVEX_V512, EVEX_CD8<32, CD8VF>;
2874 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2875 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2876 EVEX_V512, EVEX_CD8<64, CD8VF>;
2877
2878 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2879 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2880 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2881
2882 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2883 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2884 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
27892885
27902886 let Predicates = [HasAVX512] in {
27912887 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
32503346 } // ExeDomain = GenericDomain
32513347 }
32523348
3253 let Predicates = [HasAVX512] in {
3254 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3255 int_x86_avx512_rndscale_ss,
3256 int_x86_avx512_rndscale_sd>, EVEX_4V;
3257
3258 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3259 memopv16f32, memopv8f64,
3260 int_x86_avx512_rndscale_ps_512,
3261 int_x86_avx512_rndscale_pd_512, CD8VF>,
3262 EVEX, EVEX_V512;
3263 }
3349 multiclass avx512_rndscale opc, string OpcodeStr,
3350 X86MemOperand x86memop, RegisterClass RC,
3351 PatFrag mem_frag, Domain d> {
3352 let ExeDomain = d in {
3353 // Intrinsic operation, reg.
3354 // Vector intrinsic operation, reg
3355 def r : AVX512AIi8
3356 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3357 !strconcat(OpcodeStr,
3358 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3359 []>, EVEX;
3360
3361 // Vector intrinsic operation, mem
3362 def m : AVX512AIi8
3363 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3364 !strconcat(OpcodeStr,
3365 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3366 []>, EVEX;
3367 } // ExeDomain
3368 }
3369
3370
3371 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3372 memopv16f32, SSEPackedSingle>, EVEX_V512,
3373 EVEX_CD8<32, CD8VF>;
3374
3375 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3376 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3377 FROUND_CURRENT)),
3378 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3379
3380
3381 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3382 memopv8f64, SSEPackedDouble>, EVEX_V512,
3383 VEX_W, EVEX_CD8<64, CD8VF>;
3384
3385 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3386 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3387 FROUND_CURRENT)),
3388 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3389
3390 multiclass avx512_rndscale_scalar opc, string OpcodeStr,
3391 Operand x86memop, RegisterClass RC, Domain d> {
3392 let ExeDomain = d in {
3393 def r : AVX512AIi8
3394 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3395 !strconcat(OpcodeStr,
3396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3397 []>, EVEX_4V;
3398
3399 def m : AVX512AIi8
3400 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3401 !strconcat(OpcodeStr,
3402 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3403 []>, EVEX_4V;
3404 } // ExeDomain
3405 }
3406
3407 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3408 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3409
3410 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3411 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
32643412
32653413 def : Pat<(ffloor FR32X:$src),
32663414 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
32843432 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
32853433
32863434 def : Pat<(v16f32 (ffloor VR512:$src)),
3287 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3435 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
32883436 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3289 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3437 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
32903438 def : Pat<(v16f32 (fceil VR512:$src)),
3291 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3439 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
32923440 def : Pat<(v16f32 (frint VR512:$src)),
3293 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3441 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
32943442 def : Pat<(v16f32 (ftrunc VR512:$src)),
3295 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3443 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
32963444
32973445 def : Pat<(v8f64 (ffloor VR512:$src)),
3298 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3446 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
32993447 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3300 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3448 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
33013449 def : Pat<(v8f64 (fceil VR512:$src)),
3302 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3450 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
33033451 def : Pat<(v8f64 (frint VR512:$src)),
3304 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3452 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
33053453 def : Pat<(v8f64 (ftrunc VR512:$src)),
3306 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3454 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
33073455
33083456 //-------------------------------------------------
33093457 // Integer truncate and extend operations
469469 // 512-bit bitconvert pattern fragments
470470 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
471471 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
472 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
473 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
472474
473475 def vzmovl_v2i64 : PatFrag<(ops node:$src),
474476 (bitconvert (v2i64 (X86vzmovl
485487 return N->isExactlyValue(+0.0);
486488 }]>;
487489
490 def I8Imm : SDNodeXForm
491 // Transformation function: get the low 8 bits.
492 return getI8Imm((uint8_t)N->getZExtValue());
493 }]>;
494
495 def FROUND_NO_EXC : ImmLeaf;
496 def FROUND_CURRENT : ImmLeaf;
497
488498 // BYTE_imm - Transform bit immediates into byte immediates.
489499 def BYTE_imm : SDNodeXForm
490500 // Transformation function: imm >> 3
509509 let ParserMatchClass = X86GR32orGR64AsmOperand;
510510 }
511511
512 def AVX512RC : Operand {
513 let PrintMethod = "printRoundingControl";
514 let OperandType = "OPERAND_IMMEDIATE";
515 }
512516 // Sign-extended immediate classes. We don't need to define the full lattice
513517 // here because there is no instruction with an ambiguity between ImmSExti64i32
514518 // and ImmSExti32i8.
7373 }
7474 declare <8 x double> @llvm.x86.avx512.rcp28.pd.512(<8 x double>) nounwind readnone
7575
76 define <8 x double> @test_rndscale_pd_512(<8 x double> %a0) {
77 ; CHECK: vrndscale
78 %res = call <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double> %a0, i32 7) ; <<8 x double>> [#uses=1]
79 ret <8 x double> %res
80 }
81 declare <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double>, i32) nounwind readnone
82
83
84 define <16 x float> @test_rndscale_ps_512(<16 x float> %a0) {
85 ; CHECK: vrndscale
86 %res = call <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float> %a0, i32 7) ; <<16 x float>> [#uses=1]
87 ret <16 x float> %res
88 }
89 declare <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float>, i32) nounwind readnone
90
76 declare <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double>, i32, <8 x double>, i8, i32)
77
78 define <8 x double> @test7(<8 x double> %a) {
79 ; CHECK: vrndscalepd {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0b]
80 %res = call <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512(<8 x double> %a, i32 11, <8 x double> zeroinitializer, i8 -1, i32 4)
81 ret <8 x double>%res
82 }
83
84 declare <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)
85
86 define <16 x float> @test8(<16 x float> %a) {
87 ; CHECK: vrndscaleps {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0b]
88 %res = call <16 x float> @llvm.x86.avx512.mask.rndscale.ps.512(<16 x float> %a, i32 11, <16 x float> zeroinitializer, i16 -1, i32 4)
89 ret <16 x float>%res
90 }
9191
9292 define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) {
9393 ; CHECK: vrsqrt14ps
419419 ret <8 x i64> %res
420420 }
421421 declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i1> %a0, <8 x i64> %a1, <8 x i64> %a2) nounwind readonly
422
423 define <8 x i32> @test_cvtpd2udq(<8 x double> %a) {
424 ;CHECK: vcvtpd2udq {ru-sae}{{.*}}encoding: [0x62,0xf1,0xfc,0x58,0x79,0xc0]
425 %res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %a, <8 x i32>zeroinitializer, i8 -1, i32 2)
426 ret <8 x i32>%res
427 }
428 declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
429
430 define <16 x i32> @test_cvtps2udq(<16 x float> %a) {
431 ;CHECK: vcvtps2udq {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x79,0xc0]
432 %res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %a, <16 x i32>zeroinitializer, i16 -1, i32 1)
433 ret <16 x i32>%res
434 }
435 declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)
436
437 define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
438 ;CHECK: vcmpleps {sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x02]
439 %res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8)
440 ret i16 %res
441 }
442 declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> , <16 x float> , i32, i16, i32)
443
444 define i8 @test_cmppd(<8 x double> %a, <8 x double> %b) {
445 ;CHECK: vcmpneqpd %zmm{{.*}}encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc1,0x04]
446 %res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4)
447 ret i8 %res
448 }
449 declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
2323
2424 using namespace llvm;
2525 using namespace X86Disassembler;
26
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
29 ///
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
35 default:
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
41 INSTRUCTION_CONTEXTS
42 #undef ENUM_ENTRY
43 #undef ENUM_ENTRY_K_B
44 }
45 }
46
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
49 switch (type) {
50 default:
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
53 TYPES
54 #undef ENUM_ENTRY
55 }
56 }
57
58 /// stringForOperandEncoding - like stringForContext, but for
59 /// OperandEncodings.
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
61 switch (encoding) {
62 default:
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
65 ENCODINGS
66 #undef ENUM_ENTRY
67 }
68 }
2669
2770 /// inheritsFrom - Indicates whether all instructions in one class also belong
2871 /// to another class.
197240 case IC_EVEX_L2_K:
198241 case IC_EVEX_L2_B:
199242 case IC_EVEX_L2_XS_K:
243 case IC_EVEX_L2_XS_B:
244 case IC_EVEX_L2_XD_B:
200245 case IC_EVEX_L2_XD_K:
201246 case IC_EVEX_L2_OPSIZE_K:
202247 case IC_EVEX_L2_OPSIZE_B:
211256 case IC_EVEX_L2_W_B:
212257 case IC_EVEX_L2_W_XS_K:
213258 case IC_EVEX_L2_W_XD_K:
259 case IC_EVEX_L2_W_XD_B:
214260 case IC_EVEX_L2_W_OPSIZE_K:
215261 case IC_EVEX_L2_W_OPSIZE_B:
216262 case IC_EVEX_L2_W_OPSIZE_K_B:
221267 case IC_EVEX_L2_W_OPSIZE_KZ_B:
222268 return false;
223269 default:
270 errs() << "Unknown instruction class: " <<
271 stringForContext((InstructionContext)parent) << "\n";
224272 llvm_unreachable("Unknown instruction class");
225273 }
226274 }
248296 #undef ENUM_ENTRY_K_B
249297
250298 return (ranks[upper] > ranks[lower]);
251 }
252
253 /// stringForContext - Returns a string containing the name of a particular
254 /// InstructionContext, usually for diagnostic purposes.
255 ///
256 /// @param insnContext - The instruction class to transform to a string.
257 /// @return - A statically-allocated string constant that contains the
258 /// name of the instruction class.
259 static inline const char* stringForContext(InstructionContext insnContext) {
260 switch (insnContext) {
261 default:
262 llvm_unreachable("Unhandled instruction class");
263 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
264 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
265 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
266 ENUM_ENTRY(n##_KZ_B, r, d)
267 INSTRUCTION_CONTEXTS
268 #undef ENUM_ENTRY
269 #undef ENUM_ENTRY_K_B
270 }
271 }
272
273 /// stringForOperandType - Like stringForContext, but for OperandTypes.
274 static inline const char* stringForOperandType(OperandType type) {
275 switch (type) {
276 default:
277 llvm_unreachable("Unhandled type");
278 #define ENUM_ENTRY(i, d) case i: return #i;
279 TYPES
280 #undef ENUM_ENTRY
281 }
282 }
283
284 /// stringForOperandEncoding - like stringForContext, but for
285 /// OperandEncodings.
286 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
287 switch (encoding) {
288 default:
289 llvm_unreachable("Unhandled encoding");
290 #define ENUM_ENTRY(i, d) case i: return #i;
291 ENCODINGS
292 #undef ENUM_ENTRY
293 }
294299 }
295300
296301 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
12551255 TYPE("i32imm_pcrel", TYPE_REL32)
12561256 TYPE("SSECC", TYPE_IMM3)
12571257 TYPE("AVXCC", TYPE_IMM5)
1258 TYPE("AVX512RC", TYPE_IMM32)
12581259 TYPE("brtarget", TYPE_RELv)
12591260 TYPE("uncondbrtarget", TYPE_RELv)
12601261 TYPE("brtarget8", TYPE_REL8)
13121313 ENCODING("u32u8imm", ENCODING_IB)
13131314 ENCODING("SSECC", ENCODING_IB)
13141315 ENCODING("AVXCC", ENCODING_IB)
1316 ENCODING("AVX512RC", ENCODING_IB)
13151317 ENCODING("i16imm", ENCODING_Iv)
13161318 ENCODING("i16i8imm", ENCODING_IB)
13171319 ENCODING("i32imm", ENCODING_Iv)