llvm.org GIT mirror llvm / 3034c10
Fix ScalarEvolution's Xor handling to not assume that an And that gets recognized with a SCEVZeroExtendExpr must be an And with a low-bits mask. With r73540, this is no longer the case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73594 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
2 changed file(s) with 17 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
24522452 if (BO->getOpcode() == Instruction::And &&
24532453 LCI->getValue() == CI->getValue())
24542454 if (const SCEVZeroExtendExpr *Z =
2455 dyn_cast(getSCEV(U->getOperand(0))))
2456 return getZeroExtendExpr(getNotSCEV(Z->getOperand()),
2457 U->getType());
2455 dyn_cast(getSCEV(U->getOperand(0)))) {
2456 SCEVHandle ZO = Z->getOperand();
2457 if (APIntOps::isMask(getTypeSizeInBits(ZO->getType()),
2458 CI->getValue()))
2459 return getZeroExtendExpr(getNotSCEV(ZO), U->getType());
2460 }
24582461 }
24592462 break;
24602463
0 ; RUN: llvm-as < %s | opt -scalar-evolution -disable-output -analyze | grep {\\--> %z}
1
2 ; ScalarEvolution shouldn't try to analyze %s into something like
3 ; --> (zext i4 (-1 + (-1 * (trunc i64 (8 * %x) to i4))) to i64)
4
5 define i64 @foo(i64 %x) {
6 %a = shl i64 %x, 3
7 %t = and i64 %a, 8
8 %z = xor i64 %t, 8
9 ret i64 %z
10 }