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Merging r228168: ------------------------------------------------------------------------ r228168 | mkuper | 2015-02-04 10:54:01 -0800 (Wed, 04 Feb 2015) | 3 lines Fixes a bug in vector load legalization that confused bits and bytes. Differential Revision: http://reviews.llvm.org/D7400 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@228197 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
2 changed file(s) with 74 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
553553 BitOffset += SrcEltBits;
554554 if (BitOffset >= WideBits) {
555555 WideIdx++;
556 Offset -= WideBits;
557 if (Offset > 0) {
558 ShAmt = DAG.getConstant(SrcEltBits - Offset,
556 BitOffset -= WideBits;
557 if (BitOffset > 0) {
558 ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
559559 TLI.getShiftAmountTy(WideVT));
560560 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
561561 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
33 %ret = load <4 x i3>* %in, align 1
44 ret <4 x i3> %ret
55 }
6
7 ; CHECK: test1
6 ; CHECK-LABEL: test1
87 ; CHECK: movzwl
98 ; CHECK: shrl $3
109 ; CHECK: andl $7
2423 ret <4 x i1> %ret
2524 }
2625
27 ; CHECK: test2
26 ; CHECK-LABEL: test2
2827 ; CHECK: movzbl
2928 ; CHECK: shrl
3029 ; CHECK: andl $1
4544 ret <4 x i64> %sext
4645 }
4746
48 ; CHECK: test3
47 ; CHECK-LABEL: test3
4948 ; CHECK: movzbl
5049 ; CHECK: movq
5150 ; CHECK: shlq
6665 ; CHECK: vpunpcklqdq
6766 ; CHECK: vinsertf128
6867 ; CHECK: ret
68
69 define <16 x i4> @test4(<16 x i4>* %in) nounwind {
70 %ret = load <16 x i4>* %in, align 1
71 ret <16 x i4> %ret
72 }
73
74 ; CHECK-LABEL: test4
75 ; CHECK: movl
76 ; CHECK-NEXT: shrl
77 ; CHECK-NEXT: andl
78 ; CHECK-NEXT: movl
79 ; CHECK-NEXT: andl
80 ; CHECK-NEXT: vmovd
81 ; CHECK-NEXT: vpinsrb
82 ; CHECK-NEXT: movl
83 ; CHECK-NEXT: shrl
84 ; CHECK-NEXT: andl
85 ; CHECK-NEXT: vpinsrb
86 ; CHECK-NEXT: movl
87 ; CHECK-NEXT: shrl
88 ; CHECK-NEXT: andl
89 ; CHECK-NEXT: vpinsrb
90 ; CHECK-NEXT: movl
91 ; CHECK-NEXT: shrl
92 ; CHECK-NEXT: andl
93 ; CHECK-NEXT: vpinsrb
94 ; CHECK-NEXT: movl
95 ; CHECK-NEXT: shrl
96 ; CHECK-NEXT: andl
97 ; CHECK-NEXT: vpinsrb
98 ; CHECK-NEXT: movl
99 ; CHECK-NEXT: shrl
100 ; CHECK-NEXT: andl
101 ; CHECK-NEXT: vpinsrb
102 ; CHECK-NEXT: movl
103 ; CHECK-NEXT: shrl
104 ; CHECK-NEXT: vpinsrb
105 ; CHECK-NEXT: movq
106 ; CHECK-NEXT: shrq
107 ; CHECK-NEXT: andl
108 ; CHECK-NEXT: vpinsrb
109 ; CHECK-NEXT: movq
110 ; CHECK-NEXT: shrq
111 ; CHECK-NEXT: andl
112 ; CHECK-NEXT: vpinsrb
113 ; CHECK-NEXT: movq
114 ; CHECK-NEXT: shrq
115 ; CHECK-NEXT: andl
116 ; CHECK-NEXT: vpinsrb
117 ; CHECK-NEXT: movq
118 ; CHECK-NEXT: shrq
119 ; CHECK-NEXT: andl
120 ; CHECK-NEXT: vpinsrb
121 ; CHECK-NEXT: movq
122 ; CHECK-NEXT: shrq
123 ; CHECK-NEXT: andl
124 ; CHECK-NEXT: vpinsrb
125 ; CHECK-NEXT: movq
126 ; CHECK-NEXT: shrq
127 ; CHECK-NEXT: andl
128 ; CHECK-NEXT: vpinsrb
129 ; CHECK-NEXT: movq
130 ; CHECK-NEXT: shrq
131 ; CHECK-NEXT: andl
132 ; CHECK-NEXT: vpinsrb
133 ; CHECK-NEXT: shrq
134 ; CHECK-NEXT: vpinsrb
135 ; CHECK-NEXT: retq