llvm.org GIT mirror llvm / 2fd827f
Revert "[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction" This reverts commits r347532. Forget add the option -mtriple powerpc64-unknown-linux-gnu. So other platform is error except for PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347534 91177308-0d34-0410-b5e6-96231b3b80d8 Kang Zhang 11 months ago
2 changed file(s) with 4 addition(s) and 173 deletion(s). Raw diff Collapse all Expand all
29832983 if (PostRA) {
29842984 if (isVFReg(MI.getOperand(0).getReg()))
29852985 III.ImmOpcode = PPC::LXSSP;
2986 else {
2986 else
29872987 III.ImmOpcode = PPC::LFS;
2988 III.ImmMustBeMultipleOf = 1;
2989 }
29902988 break;
29912989 }
29922990 LLVM_FALLTHROUGH;
29972995 if (PostRA) {
29982996 if (isVFReg(MI.getOperand(0).getReg()))
29992997 III.ImmOpcode = PPC::LXSD;
3000 else {
2998 else
30012999 III.ImmOpcode = PPC::LFD;
3002 III.ImmMustBeMultipleOf = 1;
3003 }
30043000 break;
30053001 }
30063002 LLVM_FALLTHROUGH;
30153011 if (PostRA) {
30163012 if (isVFReg(MI.getOperand(0).getReg()))
30173013 III.ImmOpcode = PPC::STXSSP;
3018 else {
3014 else
30193015 III.ImmOpcode = PPC::STFS;
3020 III.ImmMustBeMultipleOf = 1;
3021 }
30223016 break;
30233017 }
30243018 LLVM_FALLTHROUGH;
30293023 if (PostRA) {
30303024 if (isVFReg(MI.getOperand(0).getReg()))
30313025 III.ImmOpcode = PPC::STXSD;
3032 else {
3026 else
30333027 III.ImmOpcode = PPC::STFD;
3034 III.ImmMustBeMultipleOf = 1;
3035 }
30363028 break;
30373029 }
30383030 LLVM_FALLTHROUGH;
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-161
test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir less more
None # RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole -mcpu=pwr9 %s -o - | FileCheck %s
1
2 ---
3 name: testLXSSPX
4 alignment: 4
5 exposesReturnsTwice: false
6 legalized: false
7 regBankSelected: false
8 selected: false
9 tracksRegLiveness: true
10 registers:
11 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
12 - { id: 1, class: g8rc, preferred-register: '' }
13 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
14 - { id: 3, class: gprc, preferred-register: '' }
15 - { id: 4, class: g8rc, preferred-register: '' }
16 - { id: 5, class: g8rc, preferred-register: '' }
17 - { id: 6, class: g8rc, preferred-register: '' }
18 - { id: 7, class: vssrc, preferred-register: '' }
19 - { id: 8, class: gprc, preferred-register: '' }
20 - { id: 9, class: g8rc, preferred-register: '' }
21 - { id: 10, class: g8rc, preferred-register: '' }
22 - { id: 11, class: g8rc, preferred-register: '' }
23 - { id: 12, class: vssrc, preferred-register: '' }
24 - { id: 13, class: vssrc, preferred-register: '' }
25 liveins:
26 - { reg: '$x3', virtual-reg: '%0' }
27 - { reg: '$x4', virtual-reg: '%1' }
28 body: |
29 bb.0.entry:
30 liveins: $x3, $x4
31
32 %1 = COPY $x4
33 %0 = COPY $x3
34 %2 = COPY %1.sub_32
35 %3 = ADDI %2, 1
36 %5 = IMPLICIT_DEF
37 %4 = INSERT_SUBREG %5, killed %3, 1
38 %6 = LI8 97
39 %7 = LXSSPX %0, killed %6, implicit $rm
40 ; CHECK: lfs [[REG1:[0-9]+]], 97(3)
41 %8 = ADDI %2, 2
42 %10 = IMPLICIT_DEF
43 %9 = INSERT_SUBREG %10, killed %8, 1
44 %11 = LI8 -92
45 %12 = LXSSPX %0, killed %11, implicit $rm
46 ; CHECK-NEXT: lfs [[REG2:[0-9]+]], -92(3)
47 %13 = XSADDSP killed %7, killed %12
48 ; CHECK-NEXT: xsaddsp {{[0-9]+}}, [[REG1]], [[REG2]]
49 $f1 = COPY %13
50 BLR8 implicit $lr8, implicit $rm, implicit $f1
51 ...
52
53
54 ---
55 name: testLXSDX
56 tracksRegLiveness: true
57 registers:
58 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
59 - { id: 1, class: g8rc, preferred-register: '' }
60 - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
61 - { id: 3, class: gprc, preferred-register: '' }
62 - { id: 4, class: g8rc, preferred-register: '' }
63 - { id: 5, class: g8rc, preferred-register: '' }
64 - { id: 6, class: g8rc, preferred-register: '' }
65 - { id: 7, class: vsfrc, preferred-register: '' }
66 - { id: 8, class: gprc, preferred-register: '' }
67 - { id: 9, class: g8rc, preferred-register: '' }
68 - { id: 10, class: g8rc, preferred-register: '' }
69 - { id: 11, class: g8rc, preferred-register: '' }
70 - { id: 12, class: vsfrc, preferred-register: '' }
71 - { id: 13, class: vsfrc, preferred-register: '' }
72 liveins:
73 - { reg: '$x3', virtual-reg: '%0' }
74 - { reg: '$x4', virtual-reg: '%1' }
75 body: |
76 bb.0.entry:
77 liveins: $x3, $x4
78
79 %1 = COPY $x4
80 %0 = COPY $x3
81 %2 = COPY %1.sub_32
82 %3 = ADDI %2, 1
83 %5 = IMPLICIT_DEF
84 %4 = INSERT_SUBREG %5, killed %3, 1
85 %6 = LI8 99
86 %7 = LXSDX %0, killed %6, implicit $rm
87 ; CHECK: lfd [[REG1:[0-9]+]], 99(3)
88 %8 = ADDI %2, 2
89 %10 = IMPLICIT_DEF
90 %9 = INSERT_SUBREG %10, killed %8, 1
91 %11 = LI8 -120
92 %12 = LXSDX %0, killed %11, implicit $rm
93 ; CHECK-NEXT: lfd [[REG2:[0-9]+]], -120(3)
94 %13 = XSADDDP killed %7, killed %12, implicit $rm
95 ; CHECK-NEXT: xsadddp {{[0-9]+}}, [[REG1]], [[REG2]]
96 $f1 = COPY %13
97 BLR8 implicit $lr8, implicit $rm, implicit $f1
98 ...
99
100
101 ---
102 name: testSTXSSPX
103 alignment: 4
104 exposesReturnsTwice: false
105 legalized: false
106 regBankSelected: false
107 selected: false
108 tracksRegLiveness: true
109 registers:
110 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
111 - { id: 1, class: vssrc, preferred-register: '' }
112 - { id: 2, class: g8rc, preferred-register: '' }
113 - { id: 3, class: g8rc, preferred-register: '' }
114 liveins:
115 - { reg: '$x3', virtual-reg: '%0' }
116 - { reg: '$f1', virtual-reg: '%1' }
117 - { reg: '$x5', virtual-reg: '%2' }
118 body: |
119 bb.0.entry:
120 liveins: $x3, $f1, $x5
121
122 %2 = COPY $x5
123 %1 = COPY $f1
124 %0 = COPY $x3
125 %3 = LI8 443
126 STXSSPX %1, %0, killed %3, implicit $rm
127 ; CHECK: stfs {{[0-9]+}}, 443(3)
128 BLR8 implicit $lr8, implicit $rm
129 ...
130
131
132 ---
133 name: testSTXSDX
134 alignment: 4
135 exposesReturnsTwice: false
136 legalized: false
137 regBankSelected: false
138 selected: false
139 tracksRegLiveness: true
140 registers:
141 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
142 - { id: 1, class: vsfrc, preferred-register: '' }
143 - { id: 2, class: g8rc, preferred-register: '' }
144 - { id: 3, class: g8rc, preferred-register: '' }
145 liveins:
146 - { reg: '$x3', virtual-reg: '%0' }
147 - { reg: '$f1', virtual-reg: '%1' }
148 - { reg: '$x5', virtual-reg: '%2' }
149 body: |
150 bb.0.entry:
151 liveins: $x3, $f1, $x5
152
153 %2 = COPY $x5
154 %1 = COPY $f1
155 %0 = COPY $x3
156 %3 = LI8 7
157 STXSDX %1, %0, killed %3, implicit $rm
158 ; CHECK: stfd {{[0-9]+}}, 7(3)
159 BLR8 implicit $lr8, implicit $rm
160 ...