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[mips] Range check simm16 Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265019 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 4 years ago
9 changed file(s) with 86 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
947947 }
948948
949949 template
950 void addSImmOperands(MCInst &Inst, unsigned N) const {
951 if (isImm() && !isConstantImm()) {
952 addExpr(Inst, getImm());
953 return;
954 }
955 addConstantSImmOperands(Inst, N);
956 }
957
958 template
950959 void addUImmOperands(MCInst &Inst, unsigned N) const {
951960 if (isImm() && !isConstantImm()) {
952961 addExpr(Inst, getImm());
10291038 }
10301039 template bool isConstantUImm() const {
10311040 return isConstantImm() && isUInt(getConstantImm() - Offset);
1041 }
1042 template bool isSImm() const {
1043 return isConstantImm() ? isInt(getConstantImm()) : isImm();
10321044 }
10331045 template bool isUImm() const {
10341046 return isConstantImm() ? isUInt(getConstantImm()) : isImm();
37923804 case Match_UImm16_Relaxed:
37933805 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
37943806 "expected 16-bit unsigned immediate");
3807 case Match_SImm16:
3808 case Match_SImm16_Relaxed:
3809 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3810 "expected 16-bit signed immediate");
37953811 case Match_UImm20_0:
37963812 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
37973813 "expected 20-bit unsigned immediate");
38193835 case Match_MemSImm11:
38203836 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
38213837 "expected memory with 11-bit signed offset");
3838 case Match_MemSImm16:
3839 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3840 "expected memory with 16-bit signed offset");
38223841 }
38233842
38243843 llvm_unreachable("Implement any new match types added!");
371371 unsigned Value,
372372 uint64_t Address,
373373 const void *Decoder);
374
375 static DecodeStatus DecodeSimm16(MCInst &Inst,
376 unsigned Insn,
377 uint64_t Address,
378 const void *Decoder);
379374
380375 template
381376 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
19251920 uint64_t Address,
19261921 const void *Decoder) {
19271922 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1928 return MCDisassembler::Success;
1929 }
1930
1931 static DecodeStatus DecodeSimm16(MCInst &Inst,
1932 unsigned Insn,
1933 uint64_t Address,
1934 const void *Decoder) {
1935 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
19361923 return MCDisassembler::Success;
19371924 }
19381925
4747
4848 class AHI_ATI_DESC_BASE {
4949 dag OutOperandList = (outs GPROpnd:$rs);
50 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
50 dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
5151 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
5252 string Constraints = "$rs = $rt";
5353 InstrItinClass Itinerary = itin;
420420 let DiagnosticType = "UImmRange" # Bottom # "_" # Top;
421421 }
422422
423 class SImmAsmOperandClass Supers = []>
424 : AsmOperandClass {
425 let Name = "SImm" # Bits;
426 let RenderMethod = "addSImmOperands<" # Bits # ">";
427 let PredicateMethod = "isSImm<" # Bits # ">";
428 let SuperClasses = Supers;
429 let DiagnosticType = "SImm" # Bits;
430 }
431
423432 class UImmAsmOperandClass Supers = []>
424433 : AsmOperandClass {
425434 let Name = "UImm" # Bits;
464473 }
465474 def UImm16AsmOperandClass
466475 : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
476 def SImm16RelaxedAsmOperandClass
477 : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {
478 let Name = "SImm16_Relaxed";
479 let PredicateMethod = "isAnyImm<16>";
480 let DiagnosticType = "SImm16_Relaxed";
481 }
482 def SImm16AsmOperandClass
483 : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>;
467484 def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
468485 let Name = "SImm10Lsl3";
469486 let RenderMethod = "addImmOperands";
470487 let PredicateMethod = "isScaledSImm<10, 3>";
471 let SuperClasses = [UImm16AsmOperandClass];
488 let SuperClasses = [SImm16AsmOperandClass];
472489 let DiagnosticType = "SImm10_Lsl3";
473490 }
474491 def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
599616
600617 def imm64: Operand;
601618
602 def simm16 : Operand {
603 let DecoderMethod= "DecodeSimm16";
604 }
605
606619 def simm19_lsl2 : Operand {
607620 let EncoderMethod = "getSimm19Lsl2Encoding";
608621 let DecoderMethod = "DecodeSimm19Lsl2";
616629 }
617630
618631 def simm32 : Operand;
619
620 def simm16_64 : Operand {
621 let DecoderMethod = "DecodeSimm16";
622 }
623632
624633 // Zero
625634 def uimmz : Operand {
793802 let EncoderMethod = "getSImm7Lsl2Encoding";
794803 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>";
795804 let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;
805 }
806
807 def simm16 : Operand {
808 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
809 let ParserMatchClass = !cast("SImm16AsmOperandClass");
810 }
811
812 // Like simm16 but coerces uimm16 to simm16.
813 def simm16_relaxed : Operand {
814 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
815 let ParserMatchClass = !cast("SImm16RelaxedAsmOperandClass");
816 }
817
818 def simm16_64 : Operand {
819 let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
820 let ParserMatchClass = !cast("SImm16AsmOperandClass");
796821 }
797822
798823 // This is almost the same as a uimm7 but 0x7f is interpreted as -1.
862887 let RenderMethod = "addMemOperands";
863888 let ParserMethod = "parseMemOperand";
864889 let PredicateMethod = "isMemWithSimmOffset<16>";
890 let DiagnosticType = "MemSImm16";
865891 }
866892
867893 def MipsInvertedImmoperand : AsmOperandClass {
16021628
16031629 /// Arithmetic Instructions (ALU Immediate)
16041630 let AdditionalPredicates = [NotInMicroMips] in {
1605 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1631 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
16061632 II_ADDIU, immSExt16, add>,
16071633 ADDI_FM<0x9>, IsAsCheapAsAMove;
16081634 }
1609 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1635 def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
16101636 ISA_MIPS1_NOT_32R6_64R6;
16111637 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
16121638 SLTI_FM<0xa>;
21142140 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
21152141 ISA_MIPS1_NOT_32R6_64R6;
21162142 def : MipsInstAlias<"addu $rs, $rt, $imm",
2117 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2143 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21182144 def : MipsInstAlias<"addu $rs, $imm",
2119 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
2145 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
21202146 def : MipsInstAlias<"add $rs, $rt, $imm",
2121 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
2147 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>,
21222148 ISA_MIPS1_NOT_32R6_64R6;
21232149 def : MipsInstAlias<"add $rs, $imm",
2124 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
2150 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>,
21252151 ISA_MIPS1_NOT_32R6_64R6;
21262152 def : MipsInstAlias<"and $rs, $rt, $imm",
2127 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2153 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21282154 def : MipsInstAlias<"and $rs, $imm",
2129 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
2155 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>;
21302156 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
21312157 let Predicates = [NotInMicroMips] in {
21322158 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
21412167 def : MipsInstAlias<"negu $rt, $rs",
21422168 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
21432169 def : MipsInstAlias<"slt $rs, $rt, $imm",
2144 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
2170 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21452171 def : MipsInstAlias<"sltu $rt, $rs, $imm",
2146 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
2172 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32:$imm), 0>;
21472173 def : MipsInstAlias<"xor $rs, $rt, $imm",
21482174 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>;
21492175 def : MipsInstAlias<"xor $rs, $imm",
22372263 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
22382264 "jal\t$rs"> ;
22392265
2240 def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
2241 "nor\t$rs, $rt, $imm"> ;
2266 def NORImm : MipsAsmPseudoInst<
2267 (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm),
2268 "nor\t$rs, $rt, $imm"> ;
22422269
22432270 let hasDelaySlot = 1, isCTI = 1 in {
22442271 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
66
77 .set noat
88 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
10 ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
9 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
10 ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1111 ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1212 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1313 sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1414 sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
16 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
15 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
16 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1717 sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
77 .set noat
88 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
99 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
11 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
10 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
11 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1212 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1313 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1414 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1818 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1919 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2020 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
21 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
22 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
21 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
22 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2323 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2424 sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
99 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1010 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1111 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
13 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
12 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
13 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1414 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1515 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1616 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2020 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2121 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2222 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
23 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
24 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
23 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
24 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2525 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2626 sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
55
66 .text
77 .set noreorder
8 addiu $2, $3, -32769 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
9 addiu $2, $3, 65536 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
810 andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
911 andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
1012 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
1921 ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
2022 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
2123 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
24 lwc2 $2, -32769($3) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
25 lwc2 $2, 32768($3) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
2226 ori $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
2327 ori $2, $3, 65536 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
2428 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
104104 daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
105105 dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78]
106106 dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
107 dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd]
108 daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
107 dati $3,0xabcd # CHECK: dati $3, -21555 # encoding: [0x04,0x7e,0xab,0xcd]
108 daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34]
109109 dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24]
110110 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53]
111111 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]