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RAS extensions are part of ARMv8.2-A. This change enables them by introducing a new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271670 91177308-0d34-0410-b5e6-96231b3b80d8 Sjoerd Meijer 4 years ago
20 changed file(s) with 254 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
8686 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
8787 ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8_A,
8888 FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
89 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
89 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
9090 ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a", ARMBuildAttrs::CPUArch::v8_A,
9191 FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
9292 ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
123123 ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr)
124124 ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr)
125125 ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16")
126 ARM_ARCH_EXT_NAME("ras", ARM::AEK_RAS, "+ras", "-ras")
126127 ARM_ARCH_EXT_NAME("os", ARM::AEK_OS, nullptr, nullptr)
127128 ARM_ARCH_EXT_NAME("iwmmxt", ARM::AEK_IWMMXT, nullptr, nullptr)
128129 ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr)
8282 AEK_VIRT = 0x200,
8383 AEK_DSP = 0x400,
8484 AEK_FP16 = 0x800,
85 AEK_RAS = 0x1000,
8586 // Unsupported extensions.
8687 AEK_OS = 0x8000000,
8788 AEK_IWMMXT = 0x10000000,
3030
3131 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
3232 "Enable ARMv8 CRC-32 checksum instructions">;
33
34 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
35 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
3336
3437 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
3538 "Enable ARMv8 PMUv3 Performance Monitors extension">;
109112 "Support ARM v8.1a instructions", [FeatureCRC]>;
110113
111114 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
112 "Support ARM v8.2a instructions", [HasV8_1aOps]>;
115 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
113116
114117 //===----------------------------------------------------------------------===//
115118 // Register File Description
2525 AssemblerPredicate<"FeatureCrypto", "crypto">;
2626 def HasCRC : Predicate<"Subtarget->hasCRC()">,
2727 AssemblerPredicate<"FeatureCRC", "crc">;
28 def HasRAS : Predicate<"Subtarget->hasRAS()">,
29 AssemblerPredicate<"FeatureRAS", "ras">;
2830 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
2931 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
3032 AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
389391 def : InstAlias<"wfi", (HINT 0b011)>;
390392 def : InstAlias<"sev", (HINT 0b100)>;
391393 def : InstAlias<"sevl", (HINT 0b101)>;
394 def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
392395
393396 // v8.2a Statistical Profiling extension
394397 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
5454 bool HasNEON = false;
5555 bool HasCrypto = false;
5656 bool HasCRC = false;
57 bool HasRAS = false;
5758 bool HasPerfMon = false;
5859 bool HasFullFP16 = false;
5960 bool HasSPE = false;
169170 bool hasNEON() const { return HasNEON; }
170171 bool hasCrypto() const { return HasCrypto; }
171172 bool hasCRC() const { return HasCRC; }
173 bool hasRAS() const { return HasRAS; }
172174 bool mergeNarrowLoads() const { return MergeNarrowLoads; }
173175 bool balanceFPOps() const { return BalanceFPOps; }
174176 bool predictableSelectIsExpensive() const {
262262
263263 // v8.1a "Limited Ordering Regions" extension-specific system registers
264264 {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
265
266 // v8.2a "Reliability, Availability and Serviceability" extensions registers
267 {"erridr_el1", ERRIDR_EL1, {AArch64::FeatureRAS}},
268 {"erxfr_el1", ERXFR_EL1, {AArch64::FeatureRAS}}
265269 };
266270
267271 AArch64SysReg::MRSMapper::MRSMapper() {
815819 // v8.2a registers
816820 {"uao", UAO, {AArch64::HasV8_2aOps}},
817821
822 // v8.2a "Reliability, Availability and Serviceability" extensions registers
823 {"errselr_el1", ERRSELR_EL1, {AArch64::FeatureRAS}},
824 {"erxctlr_el1", ERXCTLR_EL1, {AArch64::FeatureRAS}},
825 {"erxstatus_el1", ERXSTATUS_EL1, {AArch64::FeatureRAS}},
826 {"erxaddr_el1", ERXADDR_EL1, {AArch64::FeatureRAS}},
827 {"erxmisc0_el1", ERXMISC0_EL1, {AArch64::FeatureRAS}},
828 {"erxmisc1_el1", ERXMISC1_EL1, {AArch64::FeatureRAS}},
829 {"disr_el1", DISR_EL1, {AArch64::FeatureRAS}},
830 {"vdisr_el2", VDISR_EL2, {AArch64::FeatureRAS}},
831 {"vsesr_el2", VSESR_EL2, {AArch64::FeatureRAS}},
832
818833 // v8.2a "Statistical Profiling extension" registers
819834 {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},
820835 {"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}},
671671 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
672672 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
673673 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
674 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
674 ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
675
676 // RAS extension registers
677 ERRIDR_EL1 = 0xc298, // 11 000 0101 0011 000
678 ERXFR_EL1 = 0xc2a0 // 11 000 0101 0100 000
675679 };
676680
677681 enum SysRegWOValues {
12101214 SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
12111215 ELR_EL12 = 0xea01, // 11 101 0100 0000 001
12121216
1217 // RAS extension registers
1218 ERRSELR_EL1 = 0xc299, // 11 000 0101 0011 001
1219 ERXCTLR_EL1 = 0xc2a1, // 11 000 0101 0100 001
1220 ERXSTATUS_EL1 = 0xc2a2, // 11 000 0101 0100 010
1221 ERXADDR_EL1 = 0xc2a3, // 11 000 0101 0100 011
1222 ERXMISC0_EL1 = 0xc2a8, // 11 000 0101 0101 000
1223 ERXMISC1_EL1 = 0xc2a9, // 11 000 0101 0101 001
1224 DISR_EL1 = 0xc609, // 11 000 1100 0001 001
1225 VDISR_EL2 = 0xe609, // 11 100 1100 0001 001
1226 VSESR_EL2 = 0xe293, // 11 100 0101 0010 011
1227
12131228 // v8.2a registers
12141229 UAO = 0xc214, // 11 000 0100 0010 100
12151230
9595 [FeatureNEON]>;
9696 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
9797 "Enable support for CRC instructions">;
98 // Not to be confused with FeatureHasRetAddrStack (return address stack)
99 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
100 "Enable Reliability, Availability and Serviceability extensions">;
101
98102
99103 // Cyclone has preferred instructions for zeroing VFP registers, which can
100104 // execute in 0 cycles.
136140
137141 // Some processors perform return stack prediction. CodeGen should avoid issue
138142 // "normal" call instructions to callees which do not return.
139 def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
143 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
140144 "Has return address stack">;
141145
142146 /// DSP extension.
393397 FeatureMP,
394398 FeatureVirtualization,
395399 FeatureCrypto,
396 FeatureCRC]>;
400 FeatureCRC,
401 FeatureRAS]>;
397402
398403 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
399404 [HasV8MBaselineOps,
490495
491496 // FIXME: A5 has currently the same Schedule model as A8
492497 def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
493 FeatureHasRAS,
498 FeatureHasRetAddrStack,
494499 FeatureTrustZone,
495500 FeatureSlowFPBrcc,
496501 FeatureHasSlowFPVMLx,
500505 FeatureVFP4]>;
501506
502507 def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
503 FeatureHasRAS,
508 FeatureHasRetAddrStack,
504509 FeatureTrustZone,
505510 FeatureSlowFPBrcc,
506511 FeatureHasSlowFPVMLx,
513518 FeatureVirtualization]>;
514519
515520 def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
516 FeatureHasRAS,
521 FeatureHasRetAddrStack,
517522 FeatureTrustZone,
518523 FeatureSlowFPBrcc,
519524 FeatureHasSlowFPVMLx,
521526 FeatureT2XtPk]>;
522527
523528 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
524 FeatureHasRAS,
529 FeatureHasRetAddrStack,
525530 FeatureTrustZone,
526531 FeatureVMLxForwarding,
527532 FeatureT2XtPk,
531536
532537 // FIXME: A12 has currently the same Schedule model as A9
533538 def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
534 FeatureHasRAS,
539 FeatureHasRetAddrStack,
535540 FeatureTrustZone,
536541 FeatureVMLxForwarding,
537542 FeatureT2XtPk,
544549
545550 // FIXME: A15 has currently the same Schedule model as A9.
546551 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
547 FeatureHasRAS,
552 FeatureHasRetAddrStack,
548553 FeatureTrustZone,
549554 FeatureT2XtPk,
550555 FeatureVFP4,
556561
557562 // FIXME: A17 has currently the same Schedule model as A9
558563 def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
559 FeatureHasRAS,
564 FeatureHasRetAddrStack,
560565 FeatureTrustZone,
561566 FeatureMP,
562567 FeatureVMLxForwarding,
571576 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
572577 // division features.
573578 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
574 FeatureHasRAS,
579 FeatureHasRetAddrStack,
575580 FeatureVMLxForwarding,
576581 FeatureT2XtPk,
577582 FeatureFP16,
581586 FeatureHWDivARM]>;
582587
583588 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
584 FeatureHasRAS,
589 FeatureHasRetAddrStack,
585590 FeatureNEONForFP,
586591 FeatureT2XtPk,
587592 FeatureVFP4,
594599
595600 // FIXME: R4 has currently the same ProcessorModel as A8.
596601 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
597 FeatureHasRAS,
602 FeatureHasRetAddrStack,
598603 FeatureAvoidPartialCPSR,
599604 FeatureT2XtPk]>;
600605
601606 // FIXME: R4F has currently the same ProcessorModel as A8.
602607 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
603 FeatureHasRAS,
608 FeatureHasRetAddrStack,
604609 FeatureSlowFPBrcc,
605610 FeatureHasSlowFPVMLx,
606611 FeatureVFP3,
610615
611616 // FIXME: R5 has currently the same ProcessorModel as A8.
612617 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
613 FeatureHasRAS,
618 FeatureHasRetAddrStack,
614619 FeatureVFP3,
615620 FeatureD16,
616621 FeatureSlowFPBrcc,
621626
622627 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
623628 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
624 FeatureHasRAS,
629 FeatureHasRetAddrStack,
625630 FeatureVFP3,
626631 FeatureD16,
627632 FeatureFP16,
633638 FeatureT2XtPk]>;
634639
635640 def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
636 FeatureHasRAS,
641 FeatureHasRetAddrStack,
637642 FeatureVFP3,
638643 FeatureD16,
639644 FeatureFP16,
700705
701706 // Cyclone is very similar to swift
702707 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
703 FeatureHasRAS,
708 FeatureHasRetAddrStack,
704709 FeatureNEONForFP,
705710 FeatureT2XtPk,
706711 FeatureVFP4,
19241924 } else {
19251925 if (!isDirect && !Subtarget->hasV5TOps())
19261926 CallOpc = ARMISD::CALL_NOLINK;
1927 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1927 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
19281928 // Emit regular call when code size is the priority
19291929 !MF.getFunction()->optForMinSize())
19301930 // "mov lr, pc; b _foo" to avoid confusing the RSP
240240 AssemblerPredicate<"FeatureCrypto", "crypto">;
241241 def HasCRC : Predicate<"Subtarget->hasCRC()">,
242242 AssemblerPredicate<"FeatureCRC", "crc">;
243 def HasRAS : Predicate<"Subtarget->hasRAS()">,
244 AssemblerPredicate<"FeatureRAS", "ras">;
243245 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
244246 AssemblerPredicate<"FeatureFP16","half-float conversions">;
245247 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
19091911 bits<8> imm;
19101912 let Inst{27-8} = 0b00110010000011110000;
19111913 let Inst{7-0} = imm;
1914 let DecoderMethod = "DecodeHINTInstruction";
19121915 }
19131916
19141917 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
19171920 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
19181921 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
19191922 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1923 def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
19201924
19211925 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
19221926 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
37273727 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
37283728 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
37293729 let Predicates = [IsThumb2, HasV8];
3730 }
3731 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3732 let Predicates = [IsThumb2, HasRAS];
3733 }
3734 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3735 let Predicates = [IsThumb2, HasRAS];
37303736 }
37313737
37323738 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
142142 Pref32BitThumb = false;
143143 AvoidCPSRPartialUpdate = false;
144144 AvoidMOVsShifterOperand = false;
145 HasRAS = false;
145 HasRetAddrStack = false;
146146 HasMPExtension = false;
147147 HasVirtualization = false;
148148 FPOnlySP = false;
151151 Has8MSecExt = false;
152152 HasCrypto = false;
153153 HasCRC = false;
154 HasRAS = false;
154155 HasZeroCycleZeroing = false;
155156 StrictAlign = false;
156157 HasDSP = false;
177177 /// movs with shifter operand (i.e. asr, lsl, lsr).
178178 bool AvoidMOVsShifterOperand;
179179
180 /// HasRAS - Some processors perform return stack prediction. CodeGen should
180 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
181181 /// avoid issue "normal" call instructions to callees which do not return.
182 bool HasRAS;
182 bool HasRetAddrStack;
183183
184184 /// HasMPExtension - True if the subtarget supports Multiprocessing
185185 /// extension (ARMv7 only).
209209
210210 /// HasCRC - if true, processor supports CRC instructions
211211 bool HasCRC;
212
213 /// HasRAS - if true, the processor supports RAS extensions
214 bool HasRAS;
212215
213216 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
214217 /// particularly effective at zeroing a VFP register.
348351 bool hasNEON() const { return HasNEON; }
349352 bool hasCrypto() const { return HasCrypto; }
350353 bool hasCRC() const { return HasCRC; }
354 bool hasRAS() const { return HasRAS; }
351355 bool hasVirtualization() const { return HasVirtualization; }
352356 bool useNEONForSinglePrecisionFP() const {
353357 return hasNEON() && UseNEONForSinglePrecisionFP;
374378 bool prefers32BitThumb() const { return Pref32BitThumb; }
375379 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
376380 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
377 bool hasRAS() const { return HasRAS; }
381 bool hasRetAddrStack() const { return HasRetAddrStack; }
378382 bool hasMPExtension() const { return HasMPExtension; }
379383 bool hasDSP() const { return HasDSP; }
380384 bool useNaClTrap() const { return UseNaClTrap; }
294294 }
295295 bool hasV8_1aOps() const {
296296 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
297 }
298 bool hasRAS() const {
299 return getSTI().getFeatureBits()[ARM::FeatureRAS];
297300 }
298301
299302 void SwitchMode() {
65096512 return Error(
65106513 Op.getStartLoc(),
65116514 "immediate expression for mov requires :lower16: or :upper16");
6515 break;
6516 }
6517 case ARM::HINT:
6518 case ARM::t2HINT: {
6519 if (hasRAS()) {
6520 // ESB is not predicable (pred must be AL)
6521 unsigned Imm8 = Inst.getOperand(0).getImm();
6522 unsigned Pred = Inst.getOperand(1).getImm();
6523 if (Imm8 == 0x10 && Pred != ARMCC::AL)
6524 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6525 "predicable, but condition "
6526 "code specified");
6527 }
6528 // Without the RAS extension, this behaves as any other unallocated hint.
65126529 break;
65136530 }
65146531 }
1015410171 // FIXME: Only available in A-class, isel not predicated
1015510172 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
1015610173 { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10174 { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
1015710175 // FIXME: Unsupported extensions.
1015810176 { ARM::AEK_OS, Feature_None, {} },
1015910177 { ARM::AEK_IWMMXT, Feature_None, {} },
209209 uint64_t Address, const void *Decoder);
210210 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
211211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
213 uint64_t Address, const void *Decoder);
212214 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
213215 uint64_t Address, const void *Decoder);
214216 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
591593 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
592594 MCDisassembler::DecodeStatus S = Success;
593595
596 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
597
594598 // A few instructions actually have predicates encoded in them. Don't
595599 // try to overwrite it if we're seeing one of those.
596600 switch (MI.getOpcode()) {
610614 S = SoftFail;
611615 else
612616 return Success;
617 break;
618 case ARM::t2HINT:
619 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
620 S = SoftFail;
613621 break;
614622 case ARM::tB:
615623 case ARM::t2B:
19381946 return MCDisassembler::Fail;
19391947 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
19401948 return MCDisassembler::Fail;
1949
1950 return S;
1951 }
1952
1953 // Check for UNPREDICTABLE predicated ESB instruction
1954 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
1956 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1957 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1958 const MCDisassembler *Dis = static_cast(Decoder);
1959 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
1960
1961 DecodeStatus S = MCDisassembler::Success;
1962
1963 Inst.addOperand(MCOperand::createImm(imm8));
1964
1965 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1966 return MCDisassembler::Fail;
1967
1968 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
1969 // so all predicates should be allowed.
1970 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1971 S = MCDisassembler::SoftFail;
19411972
19421973 return S;
19431974 }
0 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ras < %s | FileCheck %s
1
2 esb
3 // CHECK: esb // encoding: [0x1f,0x22,0x03,0xd5]
4
5 msr errselr_el1, x0
6 msr errselr_el1, x15
7 msr errselr_el1, x25
8 msr erxctlr_el1, x1
9 msr erxstatus_el1, x2
10 msr erxaddr_el1, x3
11 msr erxmisc0_el1, x4
12 msr erxmisc1_el1, x5
13 msr disr_el1, x6
14 msr vdisr_el2, x7
15 msr vsesr_el2, x8
16 // CHECK: msr ERRSELR_EL1, x0 // encoding: [0x20,0x53,0x18,0xd5]
17 // CHECK: msr ERRSELR_EL1, x15 // encoding: [0x2f,0x53,0x18,0xd5]
18 // CHECK: msr ERRSELR_EL1, x25 // encoding: [0x39,0x53,0x18,0xd5]
19 // CHECK: msr ERXCTLR_EL1, x1 // encoding: [0x21,0x54,0x18,0xd5]
20 // CHECK: msr ERXSTATUS_EL1, x2 // encoding: [0x42,0x54,0x18,0xd5]
21 // CHECK: msr ERXADDR_EL1, x3 // encoding: [0x63,0x54,0x18,0xd5]
22 // CHECK: msr ERXMISC0_EL1, x4 // encoding: [0x04,0x55,0x18,0xd5]
23 // CHECK: msr ERXMISC1_EL1, x5 // encoding: [0x25,0x55,0x18,0xd5]
24 // CHECK: msr DISR_EL1, x6 // encoding: [0x26,0xc1,0x18,0xd5]
25 // CHECK: msr VDISR_EL2, x7 // encoding: [0x27,0xc1,0x1c,0xd5]
26 // CHECK: msr VSESR_EL2, x8 // encoding: [0x68,0x52,0x1c,0xd5]
27
28 mrs x0, errselr_el1
29 mrs x15, errselr_el1
30 mrs x25, errselr_el1
31 mrs x1, erxctlr_el1
32 mrs x2, erxstatus_el1
33 mrs x3, erxaddr_el1
34 mrs x4, erxmisc0_el1
35 mrs x5, erxmisc1_el1
36 mrs x6, disr_el1
37 mrs x7, vdisr_el2
38 mrs x8, vsesr_el2
39 // CHECK: mrs x0, ERRSELR_EL1 // encoding: [0x20,0x53,0x38,0xd5]
40 // CHECK: mrs x15, ERRSELR_EL1 // encoding: [0x2f,0x53,0x38,0xd5]
41 // CHECK: mrs x25, ERRSELR_EL1 // encoding: [0x39,0x53,0x38,0xd5]
42 // CHECK: mrs x1, ERXCTLR_EL1 // encoding: [0x21,0x54,0x38,0xd5]
43 // CHECK: mrs x2, ERXSTATUS_EL1 // encoding: [0x42,0x54,0x38,0xd5]
44 // CHECK: mrs x3, ERXADDR_EL1 // encoding: [0x63,0x54,0x38,0xd5]
45 // CHECK: mrs x4, ERXMISC0_EL1 // encoding: [0x04,0x55,0x38,0xd5]
46 // CHECK: mrs x5, ERXMISC1_EL1 // encoding: [0x25,0x55,0x38,0xd5]
47 // CHECK: mrs x6, DISR_EL1 // encoding: [0x26,0xc1,0x38,0xd5]
48 // CHECK: mrs x7, VDISR_EL2 // encoding: [0x27,0xc1,0x3c,0xd5]
49 // CHECK: mrs x8, VSESR_EL2 // encoding: [0x68,0x52,0x3c,0xd5]
50
51 mrs x0, erridr_el1
52 mrs x1, erxfr_el1
53 // CHECK: mrs x0, ERRIDR_EL1 // encoding: [0x00,0x53,0x38,0xd5]
54 // CHECK: mrs x1, ERXFR_EL1 // encoding: [0x01,0x54,0x38,0xd5]
0 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=ARM
1 @ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=THUMB
2
3 esb
4 @ ARM: esb @ encoding: [0x10,0xf0,0x20,0xe3]
5 @ THUMB: esb.w @ encoding: [0xaf,0xf3,0x10,0x80]
0 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+ras --disassemble < %s | FileCheck %s
1
2 [0x1f,0x22,0x03,0xd5]
3 # CHECK: esb
4
5 # CHECK: msr ERRSELR_EL1, x0
6 # CHECK: msr ERXCTLR_EL1, x0
7 # CHECK: msr ERXSTATUS_EL1, x0
8 # CHECK: msr ERXADDR_EL1, x0
9 # CHECK: msr ERXMISC0_EL1, x0
10 # CHECK: msr ERXMISC1_EL1, x0
11 # CHECK: msr DISR_EL1, x0
12 # CHECK: msr VDISR_EL2, x0
13 # CHECK: msr VSESR_EL2, x0
14 [0x20,0x53,0x18,0xd5]
15 [0x20,0x54,0x18,0xd5]
16 [0x40,0x54,0x18,0xd5]
17 [0x60,0x54,0x18,0xd5]
18 [0x00,0x55,0x18,0xd5]
19 [0x20,0x55,0x18,0xd5]
20 [0x20,0xc1,0x18,0xd5]
21 [0x20,0xc1,0x1c,0xd5]
22 [0x60,0x52,0x1c,0xd5]
23
24 # CHECK: mrs x0, ERRSELR_EL1
25 # CHECK: mrs x0, ERXCTLR_EL1
26 # CHECK: mrs x0, ERXSTATUS_EL1
27 # CHECK: mrs x0, ERXADDR_EL1
28 # CHECK: mrs x0, ERXMISC0_EL1
29 # CHECK: mrs x0, ERXMISC1_EL1
30 # CHECK: mrs x0, DISR_EL1
31 # CHECK: mrs x0, VDISR_EL2
32 # CHECK: mrs x0, VSESR_EL2
33 [0x20,0x53,0x38,0xd5]
34 [0x20,0x54,0x38,0xd5]
35 [0x40,0x54,0x38,0xd5]
36 [0x60,0x54,0x38,0xd5]
37 [0x00,0x55,0x38,0xd5]
38 [0x20,0x55,0x38,0xd5]
39 [0x20,0xc1,0x38,0xd5]
40 [0x20,0xc1,0x3c,0xd5]
41 [0x60,0x52,0x3c,0xd5]
42
43 # CHECK: mrs x0, ERRIDR_EL1
44 # CHECK: mrs x0, ERXFR_EL1
45 [0x00,0x53,0x38,0xd5]
46 [0x00,0x54,0x38,0xd5]
0 # RUN: llvm-mc < %s -triple armv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
1 # RUN: llvm-mc < %s -triple armv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
2
3 [0x10,0xf0,0x20,0xe3]
4 # RAS: esb
5 # NO-RAS: hint #16
0 # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
1 # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
2
3 [0xaf,0xf3,0x10,0x80]
4 # RAS: esb
5 # NO-RAS: hint.w #16