llvm.org GIT mirror llvm / 2e9d5f9
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70270 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 10 years ago
93 changed file(s) with 416 addition(s) and 368 deletion(s). Raw diff Collapse all Expand all
6464 // Necessary for external weak linkage support
6565 std::set ExtWeakSymbols;
6666
67 /// Fast - Generating code via fast instruction selection.
68 bool Fast;
67 /// OptLevel - Generating code at a specific optimization level.
68 unsigned OptLevel;
6969 public:
7070 /// Output stream on which we're printing assembly code.
7171 ///
109109 bool VerboseAsm;
110110
111111 protected:
112 AsmPrinter(raw_ostream &o, TargetMachine &TM,
113 const TargetAsmInfo *T, bool F, bool V);
112 explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
113 const TargetAsmInfo *T, unsigned OL, bool V);
114114
115115 public:
116116 virtual ~AsmPrinter();
8080 void EndFunction(MachineFunction *MF);
8181
8282 /// ValidDebugInfo - Return true if V represents valid debug info value.
83 bool ValidDebugInfo(Value *V, bool FastISel);
83 bool ValidDebugInfo(Value *V, unsigned OptLevel);
8484
8585 /// RecordSourceLine - Register a source line with debug info. Returns a
8686 /// unique label ID used to generate a label and provide correspondence to
4141 llvm::linkOcamlGC();
4242 llvm::linkShadowStackGC();
4343
44 (void) llvm::createBURRListDAGScheduler(NULL, false);
45 (void) llvm::createTDRRListDAGScheduler(NULL, false);
46 (void) llvm::createTDListDAGScheduler(NULL, false);
47 (void) llvm::createFastDAGScheduler(NULL, false);
48 (void) llvm::createDefaultScheduler(NULL, false);
44 (void) llvm::createBURRListDAGScheduler(NULL, 3);
45 (void) llvm::createTDRRListDAGScheduler(NULL, 3);
46 (void) llvm::createTDListDAGScheduler(NULL, 3);
47 (void) llvm::createFastDAGScheduler(NULL, 3);
48 (void) llvm::createDefaultScheduler(NULL, 3);
4949
5050 }
5151 } ForceCodegenLinking; // Force link by creating a global definition.
3131
3232 class RegisterScheduler : public MachinePassRegistryNode {
3333 public:
34 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
34 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
3535
3636 static MachinePassRegistry Registry;
3737
6363 /// createBURRListDAGScheduler - This creates a bottom up register usage
6464 /// reduction list scheduler.
6565 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
66 bool Fast);
66 unsigned OptLevel);
6767
6868 /// createTDRRListDAGScheduler - This creates a top down register usage
6969 /// reduction list scheduler.
7070 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
71 bool Fast);
71 unsigned OptLevel);
7272
7373 /// createTDListDAGScheduler - This creates a top-down list scheduler with
7474 /// a hazard recognizer.
7575 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
76 bool Fast);
76 unsigned OptLevel);
7777
7878 /// createFastDAGScheduler - This creates a "fast" scheduler.
7979 ///
8080 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
81 bool Fast);
81 unsigned OptLevel);
8282
8383 /// createDefaultScheduler - This creates an instruction scheduler appropriate
8484 /// for the target.
8585 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
86 bool Fast);
86 unsigned OptLevel);
8787
8888 } // end namespace llvm
8989
201201 /// certain types of nodes together, or eliminating superfluous nodes. The
202202 /// Level argument controls whether Combine is allowed to produce nodes and
203203 /// types that are illegal on the target.
204 void Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast);
204 void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
205205
206206 /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
207207 /// only uses types natively supported by the target. Returns "true" if it
217217 ///
218218 /// Note that this is an involved process that may invalidate pointers into
219219 /// the graph.
220 void Legalize(bool TypesNeedLegalizing, bool Fast);
220 void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
221221
222222 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
223223 /// SelectionDAG.
5050 MachineBasicBlock *BB;
5151 AliasAnalysis *AA;
5252 GCFunctionInfo *GFI;
53 bool Fast;
53 unsigned OptLevel;
5454 static char ID;
5555
56 explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
56 explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
5757 virtual ~SelectionDAGISel();
5858
5959 TargetLowering &getTargetLowering() { return TLI; }
212212 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
213213 raw_ostream &,
214214 CodeGenFileType,
215 bool /*Fast*/) {
215 unsigned /* OptLevel */) {
216216 return FileModel::None;
217217 }
218218
221221 /// used to finish up adding passes to emit the file, if necessary.
222222 ///
223223 virtual bool addPassesToEmitFileFinish(PassManagerBase &,
224 MachineCodeEmitter *, bool /*Fast*/) {
224 MachineCodeEmitter *,
225 unsigned /* OptLevel */) {
225226 return true;
226227 }
227228
233234 ///
234235 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
235236 MachineCodeEmitter &,
236 bool /*Fast*/) {
237 unsigned /* OptLevel */) {
237238 return true;
238239 }
239240
242243 /// use this.
243244 virtual bool WantsWholeFile() const { return false; }
244245 virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
245 CodeGenFileType, bool /*Fast*/) {
246 CodeGenFileType,
247 unsigned /* OptLevel */) {
246248 return true;
247249 }
248250 };
257259 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
258260 /// both emitting to assembly files or machine code output.
259261 ///
260 bool addCommonCodeGenPasses(PassManagerBase &, bool /*Fast*/);
262 bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
261263
262264 public:
263265
264266 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
265267 /// specified file emitted. Typically this will involve several steps of code
266 /// generation. If Fast is set to true, the code generator should emit code
267 /// as fast as possible, though the generated code may be less efficient.
268 /// This method should return FileModel::Error if emission of this file type
269 /// is not supported.
268 /// generation. If OptLevel is 0, the code generator should emit code as fast
269 /// as possible, though the generated code may be less efficient. This method
270 /// should return FileModel::Error if emission of this file type is not
271 /// supported.
270272 ///
271273 /// The default implementation of this method adds components from the
272274 /// LLVM retargetable code generator, invoking the methods below to get
275277 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
276278 raw_ostream &Out,
277279 CodeGenFileType FileType,
278 bool Fast);
280 unsigned OptLevel);
279281
280282 /// addPassesToEmitFileFinish - If the passes to emit the specified file had
281283 /// to be split up (e.g., to add an object writer pass), this method can be
282284 /// used to finish up adding passes to emit the file, if necessary.
283285 ///
284286 virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
285 MachineCodeEmitter *MCE, bool Fast);
287 MachineCodeEmitter *MCE,
288 unsigned OptLevel);
286289
287290 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
288291 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
291294 /// not supported.
292295 ///
293296 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
294 MachineCodeEmitter &MCE, bool Fast);
297 MachineCodeEmitter &MCE,
298 unsigned OptLevel);
295299
296300 /// Target-Independent Code Generator Pass Configuration Options.
297301
298302 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
299303 /// passes, then install an instruction selector pass, which converts from
300304 /// LLVM code to machine instructions.
301 virtual bool addInstSelector(PassManagerBase &, bool /*Fast*/) {
305 virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
302306 return true;
303307 }
304308
305309 /// addPreRegAllocPasses - This method may be implemented by targets that want
306310 /// to run passes immediately before register allocation. This should return
307311 /// true if -print-machineinstrs should print after these passes.
308 virtual bool addPreRegAlloc(PassManagerBase &, bool /*Fast*/) {
312 virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
309313 return false;
310314 }
311315
313317 /// want to run passes after register allocation but before prolog-epilog
314318 /// insertion. This should return true if -print-machineinstrs should print
315319 /// after these passes.
316 virtual bool addPostRegAlloc(PassManagerBase &, bool /*Fast*/) {
320 virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
317321 return false;
318322 }
319323
320324 /// addPreEmitPass - This pass may be implemented by targets that want to run
321325 /// passes immediately before machine code is emitted. This should return
322326 /// true if -print-machineinstrs should print out the code after the passes.
323 virtual bool addPreEmitPass(PassManagerBase &, bool /*Fast*/) {
327 virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
324328 return false;
325329 }
326330
328332 /// addAssemblyEmitter - This pass should be overridden by the target to add
329333 /// the asmprinter, if asm emission is supported. If this is not supported,
330334 /// 'true' should be returned.
331 virtual bool addAssemblyEmitter(PassManagerBase &, bool /*Fast*/,
335 virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
332336 bool /* VerboseAsmDefault */, raw_ostream &) {
333337 return true;
334338 }
336340 /// addCodeEmitter - This pass should be overridden by the target to add a
337341 /// code emitter, if supported. If this is not supported, 'true' should be
338342 /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
339 virtual bool addCodeEmitter(PassManagerBase &, bool /*Fast*/,
343 virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
340344 bool /*DumpAsm*/, MachineCodeEmitter &) {
341345 return true;
342346 }
345349 /// a code emitter (without setting flags), if supported. If this is not
346350 /// supported, 'true' should be returned. If DumpAsm is true, the generated
347351 /// assembly is printed to cerr.
348 virtual bool addSimpleCodeEmitter(PassManagerBase &, bool /*Fast*/,
352 virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
349353 bool /*DumpAsm*/, MachineCodeEmitter &) {
350354 return true;
351355 }
107107 /// generated.
108108 extern bool DisableJumpTables;
109109
110 /// FastISel - This flag enables fast-path instruction selection
110 /// EnableFastISel - This flag enables fast-path instruction selection
111111 /// which trades away generated code quality in favor of reducing
112112 /// compile time.
113113 extern bool EnableFastISel;
4141
4242 char AsmPrinter::ID = 0;
4343 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
44 const TargetAsmInfo *T, bool F, bool VDef)
45 : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o),
44 const TargetAsmInfo *T, unsigned OL, bool VDef)
45 : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
4646 TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
4747 IsInTextSection(false)
4848 {
33503350 }
33513351
33523352 /// ValidDebugInfo - Return true if V represents valid debug info value.
3353 bool ValidDebugInfo(Value *V, bool FastISel) {
3353 bool ValidDebugInfo(Value *V, unsigned OptLevel) {
33543354 if (!V)
33553355 return false;
33563356
33923392 case DW_TAG_lexical_block:
33933393 /// FIXME. This interfers with the qualitfy of generated code when
33943394 /// during optimization.
3395 if (FastISel == false)
3395 if (OptLevel != 0)
33963396 return false;
33973397 default:
33983398 break;
47294729 }
47304730
47314731 /// ValidDebugInfo - Return true if V represents valid debug info value.
4732 bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) {
4733 return DD && DD->ValidDebugInfo(V, FastISel);
4732 bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
4733 return DD && DD->ValidDebugInfo(V, OptLevel);
47344734 }
47354735
47364736 /// RecordSourceLine - Records location information and associates it with a
5454 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
5555 raw_ostream &Out,
5656 CodeGenFileType FileType,
57 bool Fast) {
57 unsigned OptLevel) {
5858 // Add common CodeGen passes.
59 if (addCommonCodeGenPasses(PM, Fast))
59 if (addCommonCodeGenPasses(PM, OptLevel))
6060 return FileModel::Error;
6161
6262 // Fold redundant debug labels.
6565 if (PrintMachineCode)
6666 PM.add(createMachineFunctionPrinterPass(cerr));
6767
68 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
69 PM.add(createMachineFunctionPrinterPass(cerr));
70
71 if (!Fast)
68 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
69 PM.add(createMachineFunctionPrinterPass(cerr));
70
71 if (OptLevel != 0)
7272 PM.add(createLoopAlignerPass());
7373
7474 switch (FileType) {
7575 default:
7676 break;
7777 case TargetMachine::AssemblyFile:
78 if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out))
78 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
7979 return FileModel::Error;
8080 return FileModel::AsmFile;
8181 case TargetMachine::ObjectFile:
9393 /// finish up adding passes to emit the file, if necessary.
9494 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
9595 MachineCodeEmitter *MCE,
96 bool Fast) {
96 unsigned OptLevel) {
9797 if (MCE)
98 addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
98 addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
9999
100100 PM.add(createGCInfoDeleter());
101101
113113 ///
114114 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
115115 MachineCodeEmitter &MCE,
116 bool Fast) {
116 unsigned OptLevel) {
117117 // Add common CodeGen passes.
118 if (addCommonCodeGenPasses(PM, Fast))
118 if (addCommonCodeGenPasses(PM, OptLevel))
119119 return true;
120120
121 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
122 PM.add(createMachineFunctionPrinterPass(cerr));
123
124 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
121 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
122 PM.add(createMachineFunctionPrinterPass(cerr));
123
124 addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
125125
126126 PM.add(createGCInfoDeleter());
127127
134134 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
135135 /// both emitting to assembly files or machine code output.
136136 ///
137 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
137 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
138 unsigned OptLevel) {
138139 // Standard LLVM-Level Passes.
139140
140141 // Run loop strength reduction before anything else.
141 if (!Fast) {
142 if (OptLevel != 0) {
142143 PM.add(createLoopStrengthReducePass(getTargetLowering()));
143144 if (PrintLSR)
144145 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
152153 // Make sure that no unreachable blocks are instruction selected.
153154 PM.add(createUnreachableBlockEliminationPass());
154155
155 if (!Fast)
156 if (OptLevel != 0)
156157 PM.add(createCodeGenPreparePass(getTargetLowering()));
157158
158159 PM.add(createStackProtectorPass(getTargetLowering()));
166167
167168 // Enable FastISel with -fast, but allow that to be overridden.
168169 if (EnableFastISelOption == cl::BOU_TRUE ||
169 (Fast && EnableFastISelOption != cl::BOU_FALSE))
170 (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
170171 EnableFastISel = true;
171172
172173 // Ask the target for an isel.
173 if (addInstSelector(PM, Fast))
174 if (addInstSelector(PM, OptLevel))
174175 return true;
175176
176177 // Print the instruction selected machine code...
177178 if (PrintMachineCode)
178179 PM.add(createMachineFunctionPrinterPass(cerr));
179180
180 if (!Fast) {
181 if (OptLevel != 0) {
181182 PM.add(createMachineLICMPass());
182183 PM.add(createMachineSinkingPass());
183184 }
184185
185186 // Run pre-ra passes.
186 if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
187 if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
187188 PM.add(createMachineFunctionPrinterPass(cerr));
188189
189190 // Perform register allocation.
190191 PM.add(createRegisterAllocator());
191192
192193 // Perform stack slot coloring.
193 if (!Fast)
194 if (OptLevel != 0)
194195 PM.add(createStackSlotColoringPass());
195196
196197 if (PrintMachineCode) // Print the register-allocated code
197198 PM.add(createMachineFunctionPrinterPass(cerr));
198199
199200 // Run post-ra passes.
200 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
201 if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
201202 PM.add(createMachineFunctionPrinterPass(cerr));
202203
203204 if (PrintMachineCode)
215216 PM.add(createMachineFunctionPrinterPass(cerr));
216217
217218 // Second pass scheduler.
218 if (!Fast && !DisablePostRAScheduler) {
219 if (OptLevel != 0 && !DisablePostRAScheduler) {
219220 PM.add(createPostRAScheduler());
220221
221222 if (PrintMachineCode)
223224 }
224225
225226 // Branch folding must be run after regalloc and prolog/epilog insertion.
226 if (!Fast)
227 if (OptLevel != 0)
227228 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
228229
229230 if (PrintMachineCode)
5656 SelectionDAG &DAG;
5757 const TargetLowering &TLI;
5858 CombineLevel Level;
59 unsigned OptLevel;
5960 bool LegalOperations;
6061 bool LegalTypes;
61 bool Fast;
6262
6363 // Worklist of all of the nodes that need to be simplified.
6464 std::vector WorkList;
253253 }
254254
255255 public:
256 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
256 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
257257 : DAG(D),
258258 TLI(D.getTargetLoweringInfo()),
259259 Level(Unrestricted),
260 OptLevel(OL),
260261 LegalOperations(false),
261262 LegalTypes(false),
262 Fast(fast),
263263 AA(A) {}
264264
265265 /// Run - runs the dag combiner on all nodes in the work list
47834783 SDValue Ptr = LD->getBasePtr();
47844784
47854785 // Try to infer better alignment information than the load already has.
4786 if (!Fast && LD->isUnindexed()) {
4786 if (OptLevel != 0 && LD->isUnindexed()) {
47874787 if (unsigned Align = InferAlignment(Ptr, DAG)) {
47884788 if (Align > LD->getAlignment())
47894789 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
49034903 SDValue Ptr = ST->getBasePtr();
49044904
49054905 // Try to infer better alignment information than the store already has.
4906 if (!Fast && ST->isUnindexed()) {
4906 if (OptLevel != 0 && ST->isUnindexed()) {
49074907 if (unsigned Align = InferAlignment(Ptr, DAG)) {
49084908 if (Align > ST->getAlignment())
49094909 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
60836083
60846084 // SelectionDAG::Combine - This is the entry point for the file.
60856085 //
6086 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
6086 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6087 unsigned OptLevel) {
60876088 /// run - This is the main entry point to this class.
60886089 ///
6089 DAGCombiner(*this, AA, Fast).Run(Level);
6090 }
6090 DAGCombiner(*this, AA, OptLevel).Run(Level);
6091 }
326326 default: break;
327327 case Intrinsic::dbg_stoppoint: {
328328 DbgStopPointInst *SPI = cast(I);
329 if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) {
329 if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
330330 DICompileUnit CU(cast(SPI->getContext()));
331331 std::string Dir, FN;
332332 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343343 }
344344 case Intrinsic::dbg_region_start: {
345345 DbgRegionStartInst *RSI = cast(I);
346 if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) {
346 if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
347347 unsigned ID =
348348 DW->RecordRegionStart(cast(RSI->getContext()));
349349 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
353353 }
354354 case Intrinsic::dbg_region_end: {
355355 DbgRegionEndInst *REI = cast(I);
356 if (DW && DW->ValidDebugInfo(REI->getContext(), true)) {
356 if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
357357 unsigned ID = 0;
358358 DISubprogram Subprogram(cast(REI->getContext()));
359359 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
379379 DbgFuncStartInst *FSI = cast(I);
380380 Value *SP = FSI->getSubprogram();
381381
382 if (DW->ValidDebugInfo(SP, true)) {
382 if (DW->ValidDebugInfo(SP, 0)) {
383383 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
384384 // (most?) gdb expects.
385385 DebugLoc PrevLoc = DL;
424424 case Intrinsic::dbg_declare: {
425425 DbgDeclareInst *DI = cast(I);
426426 Value *Variable = DI->getVariable();
427 if (DW && DW->ValidDebugInfo(Variable, true)) {
427 if (DW && DW->ValidDebugInfo(Variable, 0)) {
428428 // Determine the address of the declared object.
429429 Value *Address = DI->getAddress();
430430 if (BitCastInst *BCI = dyn_cast(Address))
5454 class VISIBILITY_HIDDEN SelectionDAGLegalize {
5555 TargetLowering &TLI;
5656 SelectionDAG &DAG;
57 unsigned OptLevel;
5758 bool TypesNeedLegalizing;
58 bool Fast;
5959
6060 // Libcall insertion helpers.
6161
138138
139139 public:
140140 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
141 bool fast);
141 unsigned ol);
142142
143143 /// getTypeAction - Return how we should legalize values of this type, either
144144 /// it is already legal or we need to expand it into multiple registers of
344344 }
345345
346346 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
347 bool types, bool fast)
348 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
349 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
347 bool types, unsigned ol)
348 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
349 TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
350350 assert(MVT::LAST_VALUETYPE <= 32 &&
351351 "Too many value types for ValueTypeActions to hold!");
352352 }
12701270 unsigned Line = DSP->getLine();
12711271 unsigned Col = DSP->getColumn();
12721272
1273 if (Fast) {
1273 if (OptLevel == 0) {
12741274 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
12751275 // won't hurt anything.
12761276 if (useDEBUG_LOC) {
85658565
85668566 // SelectionDAG::Legalize - This is the entry point for the file.
85678567 //
8568 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8568 void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
85698569 /// run - This is the main entry point to this class.
85708570 ///
8571 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
8571 SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
85728572 }
85738573
629629 //===----------------------------------------------------------------------===//
630630
631631 llvm::ScheduleDAGSDNodes *
632 llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
632 llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
633633 return new ScheduleDAGFast(*IS->MF);
634634 }
260260 /// new hazard recognizer. This scheduler takes ownership of the hazard
261261 /// recognizer and deletes it when done.
262262 ScheduleDAGSDNodes *
263 llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
263 llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
264264 return new ScheduleDAGList(*IS->MF,
265265 new LatencyPriorityQueue(),
266266 IS->CreateTargetHazardRecognizer());
15041504 //===----------------------------------------------------------------------===//
15051505
15061506 llvm::ScheduleDAGSDNodes *
1507 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
1507 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
15081508 const TargetMachine &TM = IS->TM;
15091509 const TargetInstrInfo *TII = TM.getInstrInfo();
15101510 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
15181518 }
15191519
15201520 llvm::ScheduleDAGSDNodes *
1521 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
1521 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
15221522 const TargetMachine &TM = IS->TM;
15231523 const TargetInstrInfo *TII = TM.getInstrInfo();
15241524 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
39093909 case Intrinsic::dbg_stoppoint: {
39103910 DwarfWriter *DW = DAG.getDwarfWriter();
39113911 DbgStopPointInst &SPI = cast(I);
3912 if (DW && DW->ValidDebugInfo(SPI.getContext(), Fast)) {
3912 if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
39133913 MachineFunction &MF = DAG.getMachineFunction();
3914 if (Fast)
3914 if (OptLevel == 0)
39153915 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
39163916 SPI.getLine(),
39173917 SPI.getColumn(),
39293929 case Intrinsic::dbg_region_start: {
39303930 DwarfWriter *DW = DAG.getDwarfWriter();
39313931 DbgRegionStartInst &RSI = cast(I);
3932 if (DW && DW->ValidDebugInfo(RSI.getContext(), Fast)) {
3932
3933 if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
39333934 unsigned LabelID =
39343935 DW->RecordRegionStart(cast(RSI.getContext()));
39353936 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
39413942 case Intrinsic::dbg_region_end: {
39423943 DwarfWriter *DW = DAG.getDwarfWriter();
39433944 DbgRegionEndInst &REI = cast(I);
3944 if (DW && DW->ValidDebugInfo(REI.getContext(), Fast)) {
3945
3945
3946 if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
39463947 MachineFunction &MF = DAG.getMachineFunction();
39473948 DISubprogram Subprogram(cast(REI.getContext()));
39483949 std::string SPName;
39513952 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
39523953 // This is end of inlined function. Debugging information for
39533954 // inlined function is not handled yet (only supported by FastISel).
3954 if (Fast) {
3955 if (OptLevel == 0) {
39553956 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
39563957 if (ID != 0)
39573958 // Returned ID is 0 if this is unbalanced "end of inlined
39773978 if (!DW) return 0;
39783979 DbgFuncStartInst &FSI = cast(I);
39793980 Value *SP = FSI.getSubprogram();
3980 if (SP && DW->ValidDebugInfo(SP, Fast)) {
3981 MachineFunction &MF = DAG.getMachineFunction();
3982 if (Fast) {
3981 if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
3982 MachineFunction &MF = DAG.getMachineFunction();
3983 if (OptLevel == 0) {
39833984 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
39843985 // (most?) gdb expects.
39853986 DebugLoc PrevLoc = CurDebugLoc;
40504051 return 0;
40514052 }
40524053 case Intrinsic::dbg_declare: {
4053 if (Fast) {
4054 if (OptLevel == 0) {
40544055 DwarfWriter *DW = DAG.getDwarfWriter();
40554056 DbgDeclareInst &DI = cast(I);
40564057 Value *Variable = DI.getVariable();
4057 if (DW && DW->ValidDebugInfo(Variable, Fast))
4058 if (DW && DW->ValidDebugInfo(Variable, OptLevel))
40584059 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
40594060 getValue(DI.getAddress()), getValue(Variable)));
40604061 } else {
354354 ///
355355 FunctionLoweringInfo &FuncInfo;
356356
357 /// Fast - We are in -fast mode.
357 /// OptLevel - What optimization level we're generating code for.
358358 ///
359 bool Fast;
359 unsigned OptLevel;
360360
361361 /// GFI - Garbage collection metadata for the function.
362362 GCFunctionInfo *GFI;
363363
364364 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
365 FunctionLoweringInfo &funcinfo, bool fast)
365 FunctionLoweringInfo &funcinfo, unsigned ol)
366366 : CurDebugLoc(DebugLoc::getUnknownLoc()),
367 TLI(tli), DAG(dag), FuncInfo(funcinfo), Fast(fast) {
367 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
368368 }
369369
370370 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
135135 /// createDefaultScheduler - This creates an instruction scheduler appropriate
136136 /// for the target.
137137 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
138 bool Fast) {
138 unsigned OptLevel) {
139139 const TargetLowering &TLI = IS->getTargetLowering();
140140
141 if (Fast)
142 return createFastDAGScheduler(IS, Fast);
141 if (OptLevel == 0)
142 return createFastDAGScheduler(IS, OptLevel);
143143 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
144 return createTDListDAGScheduler(IS, Fast);
144 return createTDListDAGScheduler(IS, OptLevel);
145145 assert(TLI.getSchedulingPreference() ==
146146 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
147 return createBURRListDAGScheduler(IS, Fast);
147 return createBURRListDAGScheduler(IS, OptLevel);
148148 }
149149 }
150150
261261 // SelectionDAGISel code
262262 //===----------------------------------------------------------------------===//
263263
264 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
264 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
265265 FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
266266 FuncInfo(new FunctionLoweringInfo(TLI)),
267267 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
268 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, fast)),
268 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
269269 GFI(),
270 Fast(fast),
270 OptLevel(OL),
271271 DAGSize(0)
272272 {}
273273
575575 // Run the DAG combiner in pre-legalize mode.
576576 if (TimePassesIsEnabled) {
577577 NamedRegionTimer T("DAG Combining 1", GroupName);
578 CurDAG->Combine(Unrestricted, *AA, Fast);
578 CurDAG->Combine(Unrestricted, *AA, OptLevel);
579579 } else {
580 CurDAG->Combine(Unrestricted, *AA, Fast);
580 CurDAG->Combine(Unrestricted, *AA, OptLevel);
581581 }
582582
583583 DOUT << "Optimized lowered selection DAG:\n";
607607 // Run the DAG combiner in post-type-legalize mode.
608608 if (TimePassesIsEnabled) {
609609 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
610 CurDAG->Combine(NoIllegalTypes, *AA, Fast);
610 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
611611 } else {
612 CurDAG->Combine(NoIllegalTypes, *AA, Fast);
612 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
613613 }
614614
615615 DOUT << "Optimized type-legalized selection DAG:\n";
621621
622622 if (TimePassesIsEnabled) {
623623 NamedRegionTimer T("DAG Legalization", GroupName);
624 CurDAG->Legalize(DisableLegalizeTypes, Fast);
624 CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
625625 } else {
626 CurDAG->Legalize(DisableLegalizeTypes, Fast);
626 CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
627627 }
628628
629629 DOUT << "Legalized selection DAG:\n";
634634 // Run the DAG combiner in post-legalize mode.
635635 if (TimePassesIsEnabled) {
636636 NamedRegionTimer T("DAG Combining 2", GroupName);
637 CurDAG->Combine(NoIllegalOperations, *AA, Fast);
637 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
638638 } else {
639 CurDAG->Combine(NoIllegalOperations, *AA, Fast);
639 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
640640 }
641641
642642 DOUT << "Optimized legalized selection DAG:\n";
644644
645645 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
646646
647 if (!Fast)
647 if (OptLevel != 0)
648648 ComputeLiveOutVRegInfo();
649649
650650 // Third, instruction select all of the operations to machine code, adding the
10811081 RegisterScheduler::setDefault(Ctor);
10821082 }
10831083
1084 return Ctor(this, Fast);
1084 return Ctor(this, OptLevel);
10851085 }
10861086
10871087 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
9090 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
9191 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
9292 ARMTargetMachine &TM,
93 bool Fast, bool Verbose);
93 unsigned OptLevel, bool Verbose);
9494 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
9595 MachineCodeEmitter &MCE);
9696 FunctionPass *createARMLoadStoreOptimizationPass();
137137
138138
139139 // Pass Pipeline Configuration
140 bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
140 bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
141141 PM.add(createARMISelDag(*this));
142142 return false;
143143 }
144144
145 bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
145 bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
146146 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
147 if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())
147 if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
148148 PM.add(createARMLoadStoreOptimizationPass());
149149
150 if (!Fast && !DisableIfConversion && !Subtarget.isThumb())
150 if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
151151 PM.add(createIfConverterPass());
152152
153153 PM.add(createARMConstantIslandPass());
154154 return true;
155155 }
156156
157 bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
158 bool Verbose, raw_ostream &Out) {
157 bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
158 unsigned OptLevel,
159 bool Verbose,
160 raw_ostream &Out) {
159161 // Output assembly language.
160162 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
161163 if (AsmPrinterCtor)
162 PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
163
164 return false;
165 }
166
167
168 bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
164 PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
165
166 return false;
167 }
168
169
170 bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
169171 bool DumpAsm, MachineCodeEmitter &MCE) {
170172 // FIXME: Move this to TargetJITInfo!
171173 if (DefRelocModel == Reloc::Default)
176178 if (DumpAsm) {
177179 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
178180 if (AsmPrinterCtor)
179 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
181 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
180182 }
181183
182184 return false;
183185 }
184186
185 bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
186 bool DumpAsm, MachineCodeEmitter &MCE) {
187 bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
188 unsigned OptLevel,
189 bool DumpAsm,
190 MachineCodeEmitter &MCE) {
187191 // Machine code emitter pass for ARM.
188192 PM.add(createARMCodeEmitterPass(*this, MCE));
189193 if (DumpAsm) {
190194 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
191195 if (AsmPrinterCtor)
192 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
196 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
193197 }
194198
195199 return false;
4040 // set this functions to ctor pointer at startup time if they are linked in.
4141 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4242 ARMTargetMachine &tm,
43 bool fast, bool verbose);
43 unsigned OptLevel, bool verbose);
4444 static AsmPrinterCtorFn AsmPrinterCtor;
4545
4646 public:
6868 virtual const TargetAsmInfo *createTargetAsmInfo() const;
6969
7070 // Pass Pipeline Configuration
71 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
72 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
73 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
71 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
72 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
73 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
7474 bool Verbose, raw_ostream &Out);
75 virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
75 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
7676 bool DumpAsm, MachineCodeEmitter &MCE);
77 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
77 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
7878 bool DumpAsm, MachineCodeEmitter &MCE);
7979 };
8080
7979 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
8080 bool InCPMode;
8181 public:
82 ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
83 const TargetAsmInfo *T, bool F, bool V)
84 : AsmPrinter(O, TM, T, F, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
82 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
83 const TargetAsmInfo *T, unsigned OL, bool V)
84 : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
8585 InCPMode(false) {
8686 Subtarget = &TM.getSubtarget();
8787 }
10601060 ///
10611061 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
10621062 ARMTargetMachine &tm,
1063 bool fast, bool verbose) {
1064 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
1063 unsigned OptLevel, bool verbose) {
1064 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
10651065 }
10661066
10671067 namespace {
2525 FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
2626 FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
2727 TargetMachine &TM,
28 bool Fast, bool Verbose);
28 unsigned OptLevel, bool Verbose);
2929 FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
3030 FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
3131 MachineCodeEmitter &MCE);
7575 // Pass Pipeline Configuration
7676 //===----------------------------------------------------------------------===//
7777
78 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
78 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
79 unsigned OptLevel) {
7980 PM.add(createAlphaISelDag(*this));
8081 return false;
8182 }
82 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
83 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
84 unsigned OptLevel) {
8385 // Must run branch selection immediately preceding the asm printer
8486 PM.add(createAlphaBranchSelectionPass());
8587 return false;
8688 }
87 bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
89 bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
90 unsigned OptLevel,
8891 bool Verbose,
8992 raw_ostream &Out) {
9093 PM.add(createAlphaLLRPPass(*this));
91 PM.add(createAlphaCodePrinterPass(Out, *this, Fast, Verbose));
94 PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
9295 return false;
9396 }
94 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
97 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
9598 bool DumpAsm, MachineCodeEmitter &MCE) {
9699 PM.add(createAlphaCodeEmitterPass(*this, MCE));
97100 if (DumpAsm)
98 PM.add(createAlphaCodePrinterPass(errs(), *this, Fast, true));
101 PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
99102 return false;
100103 }
101104 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
102 bool Fast, bool DumpAsm,
105 unsigned OptLevel, bool DumpAsm,
103106 MachineCodeEmitter &MCE) {
104 return addCodeEmitter(PM, Fast, DumpAsm, MCE);
107 return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
105108 }
5757 static unsigned getModuleMatchQuality(const Module &M);
5858
5959 // Pass Pipeline Configuration
60 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
61 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
62 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
60 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
61 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
62 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
6363 bool Verbose, raw_ostream &Out);
64 virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
64 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
6565 bool DumpAsm, MachineCodeEmitter &MCE);
66 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
66 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
6767 bool DumpAsm, MachineCodeEmitter &MCE);
6868 };
6969
3535 /// Unique incrementer for label values for referencing Global values.
3636 ///
3737
38 AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
39 const TargetAsmInfo *T, bool F, bool V)
40 : AsmPrinter(o, tm, T, F, V) {}
38 explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
39 const TargetAsmInfo *T, unsigned OL, bool V)
40 : AsmPrinter(o, tm, T, OL, V) {}
4141
4242 virtual const char *getPassName() const {
4343 return "Alpha Assembly Printer";
6767 ///
6868 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
6969 TargetMachine &tm,
70 bool fast, bool verbose) {
71 return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
70 unsigned OptLevel,
71 bool verbose) {
72 return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
7273 }
7374
7475 #include "AlphaGenAsmWriter.inc"
35863586 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
35873587 raw_ostream &o,
35883588 CodeGenFileType FileType,
3589 bool Fast) {
3589 unsigned OptLevel) {
35903590 if (FileType != TargetMachine::AssemblyFile) return true;
35913591
35923592 PM.add(createGCLoweringPass());
2626
2727 virtual bool WantsWholeFile() const { return true; }
2828 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
29 CodeGenFileType FileType, bool Fast);
29 CodeGenFileType FileType,
30 unsigned OptLevel);
3031
3132 // This class always works, but must be requested explicitly on
3233 // llc command line.
4747 class VISIBILITY_HIDDEN SPUAsmPrinter : public AsmPrinter {
4848 std::set FnStubs, GVStubs;
4949 public:
50 SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, bool F, bool V) :
52 AsmPrinter(O, TM, T, F, V) {}
50 explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, unsigned OL, bool V) :
52 AsmPrinter(O, TM, T, OL, V) {}
5353
5454 virtual const char *getPassName() const {
5555 return "STI CBEA SPU Assembly Printer";
614614 ///
615615 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
616616 SPUTargetMachine &tm,
617 bool fast, bool verbose) {
618 return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
619 }
617 unsigned OptLevel, bool verbose) {
618 return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
619 }
2424 FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
2525 FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
2626 SPUTargetMachine &tm,
27 bool fast, bool verbose);
27 unsigned OptLevel, bool verbose);
2828
2929 /*--== Utility functions/predicates/etc used all over the place: --==*/
3030 //! Predicate test for a signed 10-bit value
8080 //===----------------------------------------------------------------------===//
8181
8282 bool
83 SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast)
83 SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
8484 {
8585 // Install an instruction selector.
8686 PM.add(createSPUISelDag(*this));
8787 return false;
8888 }
8989
90 bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
91 bool Verbose, raw_ostream &Out) {
92 PM.add(createSPUAsmPrinterPass(Out, *this, Fast, Verbose));
90 bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
91 unsigned OptLevel,
92 bool Verbose,
93 raw_ostream &Out) {
94 PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
9395 return false;
9496 }
8282 }
8383
8484 // Pass Pipeline Configuration
85 virtual bool addInstSelector(PassManagerBase &PM, bool /*Fast*/);
86 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool /*Fast*/,
87 bool /*Verbose*/, raw_ostream &Out);
85 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
86 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
87 bool Verbose, raw_ostream &Out);
8888 };
8989
9090 } // end namespace llvm
19941994 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
19951995 raw_ostream &o,
19961996 CodeGenFileType FileType,
1997 bool Fast) {
1997 unsigned OptLevel) {
19981998 if (FileType != TargetMachine::AssemblyFile) return true;
19991999 PM.add(new CppWriter(o));
20002000 return false;
2828
2929 virtual bool WantsWholeFile() const { return true; }
3030 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
31 CodeGenFileType FileType, bool Fast);
31 CodeGenFileType FileType,
32 unsigned OptLevel);
3233
3334 // This class always works, but shouldn't be the default in most cases.
3435 static unsigned getModuleMatchQuality(const Module &M) { return 1; }
3636 class IA64AsmPrinter : public AsmPrinter {
3737 std::set ExternalFunctionNames, ExternalObjectNames;
3838 public:
39 IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
40 const TargetAsmInfo *T, bool F, bool V)
41 : AsmPrinter(O, TM, T, F, V) {}
39 explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
40 const TargetAsmInfo *T, unsigned OL, bool V)
41 : AsmPrinter(O, TM, T, OL, V) {}
4242
4343 virtual const char *getPassName() const {
4444 return "IA64 Assembly Printer";
369369 ///
370370 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
371371 IA64TargetMachine &tm,
372 bool fast, bool verbose) {
373 return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
374 }
372 unsigned OptLevel,
373 bool verbose) {
374 return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
375 }
3636 ///
3737 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
3838 IA64TargetMachine &tm,
39 bool fast, bool verbose);
39 unsigned OptLevel, bool verbose);
4040
4141 } // End llvm namespace
4242
7171 // Pass Pipeline Configuration
7272 //===----------------------------------------------------------------------===//
7373
74 bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
74 bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
7575 PM.add(createIA64DAGToDAGInstructionSelector(*this));
7676 return false;
7777 }
7878
79 bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
79 bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
8080 // Make sure everything is bundled happily
8181 PM.add(createIA64BundlingPass(*this));
8282 return true;
8383 }
84 bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
85 bool Verbose, raw_ostream &Out) {
86 PM.add(createIA64CodePrinterPass(Out, *this, Fast, Verbose));
84 bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
85 unsigned OptLevel,
86 bool Verbose,
87 raw_ostream &Out) {
88 PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
8789 return false;
8890 }
8991
5050 static unsigned getModuleMatchQuality(const Module &M);
5151
5252 // Pass Pipeline Configuration
53 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
54 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
53 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
5656 bool Verbose, raw_ostream &Out);
5757 };
5858 } // End llvm namespace
3434
3535 virtual bool WantsWholeFile() const { return true; }
3636 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
37 CodeGenFileType FileType, bool Fast);
37 CodeGenFileType FileType,
38 unsigned OptLevel);
3839
3940 // This class always works, but shouldn't be the default in most cases.
4041 static unsigned getModuleMatchQuality(const Module &M) { return 1; }
16611662 //===----------------------------------------------------------------------===//
16621663
16631664 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
1664 CodeGenFileType FileType, bool Fast)
1665 CodeGenFileType FileType,
1666 unsigned OptLevel)
16651667 {
16661668 if (FileType != TargetMachine::AssemblyFile) return true;
16671669 MSILWriter* Writer = new MSILWriter(o);
4848 class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
4949 const MipsSubtarget *Subtarget;
5050 public:
51 MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
52 const TargetAsmInfo *T, bool F, bool V)
53 : AsmPrinter(O, TM, T, F, V) {
51 explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
52 const TargetAsmInfo *T, unsigned OL, bool V)
53 : AsmPrinter(O, TM, T, OL, V) {
5454 Subtarget = &TM.getSubtarget();
5555 }
5656
9090 /// regardless of whether the function is in SSA form.
9191 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
9292 MipsTargetMachine &tm,
93 bool fast, bool verbose) {
94 return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
93 unsigned OptLevel, bool verbose) {
94 return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
9595 }
9696
9797 //===----------------------------------------------------------------------===//
2424 FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
2525 FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
2626 MipsTargetMachine &TM,
27 bool Fast, bool Verbose);
27 unsigned OptLevel, bool Verbose);
2828 } // end namespace llvm;
2929
3030 // Defines symbolic names for Mips registers. This defines a mapping from
104104 // Install an instruction selector pass using
105105 // the ISelDag to gen Mips code.
106106 bool MipsTargetMachine::
107 addInstSelector(PassManagerBase &PM, bool Fast)
107 addInstSelector(PassManagerBase &PM, unsigned OptLevel)
108108 {
109109 PM.add(createMipsISelDag(*this));
110110 return false;
114114 // machine code is emitted. return true if -print-machineinstrs should
115115 // print out the code after the passes.
116116 bool MipsTargetMachine::
117 addPreEmitPass(PassManagerBase &PM, bool Fast)
117 addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
118118 {
119119 PM.add(createMipsDelaySlotFillerPass(*this));
120120 return true;
123123 // Implements the AssemblyEmitter for the target. Must return
124124 // true if AssemblyEmitter is supported
125125 bool MipsTargetMachine::
126 addAssemblyEmitter(PassManagerBase &PM, bool Fast,
126 addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
127127 bool Verbose, raw_ostream &Out)
128128 {
129129 // Output assembly language.
130 PM.add(createMipsCodePrinterPass(Out, *this, Fast, Verbose));
130 PM.add(createMipsCodePrinterPass(Out, *this, OptLevel, Verbose));
131131 return false;
132132 }
5656 static unsigned getModuleMatchQuality(const Module &M);
5757
5858 // Pass Pipeline Configuration
59 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
60 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
61 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
59 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
60 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
61 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
6262 bool Verbose, raw_ostream &Out);
6363 };
6464
7474 FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
7575 FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
7676 PIC16TargetMachine &TM,
77 bool Fast, bool Verbose);
77 unsigned OptLevel, bool Verbose);
7878 } // end namespace llvm;
7979
8080 // Defines symbolic names for PIC16 registers. This defines a mapping from
160160 ///
161161 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
162162 PIC16TargetMachine &tm,
163 bool fast, bool verbose) {
164 return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
163 unsigned OptLevel,
164 bool verbose) {
165 return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
165166 }
166167
167168 void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
2323
2424 namespace llvm {
2525 struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
26 PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
27 const TargetAsmInfo *T, bool F, bool V)
28 : AsmPrinter(O, TM, T, F, V) {
26 explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
27 const TargetAsmInfo *T, unsigned OL, bool V)
28 : AsmPrinter(O, TM, T, OL, V) {
2929 CurBank = "";
3030 FunctionLabelBegin = '@';
3131 IsRomData = false;
5454 return new PIC16TargetAsmInfo(*this);
5555 }
5656
57 bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
57 bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
58 unsigned OptLevel) {
5859 // Install an instruction selector.
5960 PM.add(createPIC16ISelDag(*this));
6061 return false;
6162 }
6263
6364 bool PIC16TargetMachine::
64 addAssemblyEmitter(PassManagerBase &PM, bool Fast, bool Verbose,
65 addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
6566 raw_ostream &Out) {
6667 // Output assembly language.
67 PM.add(createPIC16CodePrinterPass(Out, *this, Fast, Verbose));
68 PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
6869 return false;
6970 }
7071
5656 return const_cast(&TLInfo);
5757 }
5858
59 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
60 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
59 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
60 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
6161 bool Verbose, raw_ostream &Out);
6262 }; // PIC16TargetMachine.
6363
5353 StringSet<> FnStubs, GVStubs, HiddenGVStubs;
5454 const PPCSubtarget &Subtarget;
5555 public:
56 PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
57 const TargetAsmInfo *T, bool F, bool V)
58 : AsmPrinter(O, TM, T, F, V),
56 explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
57 const TargetAsmInfo *T, unsigned OL, bool V)
58 : AsmPrinter(O, TM, T, OL, V),
5959 Subtarget(TM.getSubtarget()) {}
6060
6161 virtual const char *getPassName() const {
296296 DwarfWriter *DW;
297297 MachineModuleInfo *MMI;
298298 public:
299 PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
300 const TargetAsmInfo *T, bool F, bool V)
301 : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
299 explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
300 const TargetAsmInfo *T, unsigned OL, bool V)
301 : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
302302
303303 virtual const char *getPassName() const {
304304 return "Linux PPC Assembly Printer";
325325 MachineModuleInfo *MMI;
326326 raw_ostream &OS;
327327 public:
328 PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
329 const TargetAsmInfo *T, bool F, bool V)
330 : PPCAsmPrinter(O, TM, T, F, V), DW(0), MMI(0), OS(O) {}
328 explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
329 const TargetAsmInfo *T, unsigned OL, bool V)
330 : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
331331
332332 virtual const char *getPassName() const {
333333 return "Darwin PPC Assembly Printer";
11751175 ///
11761176 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
11771177 PPCTargetMachine &tm,
1178 bool fast, bool verbose) {
1178 unsigned OptLevel, bool verbose) {
11791179 const PPCSubtarget *Subtarget = &tm.getSubtarget();
11801180
11811181 if (Subtarget->isDarwin()) {
1182 return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
1182 return new PPCDarwinAsmPrinter(o, tm, tm.getTargetAsmInfo(),
1183 OptLevel, verbose);
11831184 } else {
1184 return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
1185 return new PPCLinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(),
1186 OptLevel, verbose);
11851187 }
11861188 }
11871189
2727 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
2828 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
2929 PPCTargetMachine &TM,
30 bool Fast, bool Verbose);
30 unsigned OptLevel, bool Verbose);
3131 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
3232 MachineCodeEmitter &MCE);
3333 } // end namespace llvm;
128128 // Pass Pipeline Configuration
129129 //===----------------------------------------------------------------------===//
130130
131 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
131 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
132132 // Install an instruction selector.
133133 PM.add(createPPCISelDag(*this));
134134 return false;
135135 }
136136
137 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
137 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
138138
139139 // Must run branch selection immediately preceding the asm printer.
140140 PM.add(createPPCBranchSelectionPass());
141141 return false;
142142 }
143143
144 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
145 bool Verbose, raw_ostream &Out) {
144 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
145 unsigned OptLevel,
146 bool Verbose,
147 raw_ostream &Out) {
146148 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
147149 if (AsmPrinterCtor)
148 PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
150 PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
149151
150152 return false;
151153 }
152154
153 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
155 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
154156 bool DumpAsm, MachineCodeEmitter &MCE) {
155157 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
156158 // FIXME: This should be moved to TargetJITInfo!!
175177 if (DumpAsm) {
176178 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
177179 if (AsmPrinterCtor)
178 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
180 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
179181 }
180182
181183 return false;
182184 }
183185
184 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
186 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
185187 bool DumpAsm, MachineCodeEmitter &MCE) {
186188 // Machine code emitter pass for PowerPC.
187189 PM.add(createPPCCodeEmitterPass(*this, MCE));
188190 if (DumpAsm) {
189191 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
190192 if (AsmPrinterCtor)
191 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
193 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
192194 }
193195
194196 return false;
4545 // set this functions to ctor pointer at startup time if they are linked in.
4646 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4747 PPCTargetMachine &tm,
48 bool fast, bool verbose);
48 unsigned OptLevel, bool verbose);
4949 static AsmPrinterCtorFn AsmPrinterCtor;
5050
5151 public:
7575 }
7676
7777 // Pass Pipeline Configuration
78 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
79 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
80 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
78 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
79 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
80 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
8181 bool Verbose, raw_ostream &Out);
82 virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
82 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
8383 bool DumpAsm, MachineCodeEmitter &MCE);
84 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
84 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
8585 bool DumpAsm, MachineCodeEmitter &MCE);
8686 virtual bool getEnableTailMergeDefault() const;
8787 };
4747 typedef std::map ValueMapTy;
4848 ValueMapTy NumberForBB;
4949 public:
50 SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, bool F, bool V)
52 : AsmPrinter(O, TM, T, F, V) {}
50 explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, unsigned OL, bool V)
52 : AsmPrinter(O, TM, T, OL, V) {}
5353
5454 virtual const char *getPassName() const {
5555 return "Sparc Assembly Printer";
8181 ///
8282 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
8383 TargetMachine &tm,
84 bool fast, bool verbose) {
85 return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
84 unsigned OptLevel,
85 bool verbose) {
86 return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
8687 }
8788
8889 /// runOnMachineFunction - This uses the printInstruction()
2424
2525 FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
2626 FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
27 bool Fast, bool Verbose);
27 unsigned OptLevel, bool Verbose);
2828 FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
2929 FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
3030 } // end namespace llvm;
6767 #endif
6868 }
6969
70 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
70 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
71 unsigned OptLevel) {
7172 PM.add(createSparcISelDag(*this));
7273 return false;
7374 }
7576 /// addPreEmitPass - This pass may be implemented by targets that want to run
7677 /// passes immediately before machine code is emitted. This should return
7778 /// true if -print-machineinstrs should print out the code after the passes.
78 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
79 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
7980 PM.add(createSparcFPMoverPass(*this));
8081 PM.add(createSparcDelaySlotFillerPass(*this));
8182 return true;
8283 }
8384
84 bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
85 bool Verbose, raw_ostream &Out) {
85 bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
86 unsigned OptLevel,
87 bool Verbose,
88 raw_ostream &Out) {
8689 // Output assembly language.
87 PM.add(createSparcCodePrinterPass(Out, *this, Fast, Verbose));
90 PM.add(createSparcCodePrinterPass(Out, *this, OptLevel, Verbose));
8891 return false;
8992 }
5050 static unsigned getModuleMatchQuality(const Module &M);
5151
5252 // Pass Pipeline Configuration
53 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
54 virtual bool addPreEmitPass(PassManagerBase &PM, bool Fast);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
53 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
5656 bool Verbose, raw_ostream &Out);
5757 };
5858
3232 MachineModuleInfo *MMI;
3333 const X86Subtarget *Subtarget;
3434 public:
35 X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
36 const TargetAsmInfo *T, bool F, bool V)
37 : AsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {
35 explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
36 const TargetAsmInfo *T, unsigned OL, bool V)
37 : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
3838 Subtarget = &TM.getSubtarget();
3939 }
4040
2424 ///
2525 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
2626 X86TargetMachine &tm,
27 bool fast, bool verbose) {
27 unsigned OptLevel, bool verbose) {
2828 const X86Subtarget *Subtarget = &tm.getSubtarget();
2929
3030 if (Subtarget->isFlavorIntel()) {
31 return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
31 return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo(),
32 OptLevel, verbose);
3233 } else {
33 return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
34 return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo(),
35 OptLevel, verbose);
3436 }
3537 }
3638
2424 namespace llvm {
2525
2626 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
27 X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
28 const TargetAsmInfo *T, bool F, bool V)
29 : AsmPrinter(O, TM, T, F, V) {}
27 explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
28 const TargetAsmInfo *T, unsigned OL, bool V)
29 : AsmPrinter(O, TM, T, OL, V) {}
3030
3131 virtual const char *getPassName() const {
3232 return "X86 Intel-Style Assembly Printer";
2424 /// createX86ISelDag - This pass converts a legalized DAG into a
2525 /// X86-specific DAG, ready for instruction scheduling.
2626 ///
27 FunctionPass *createX86ISelDag(X86TargetMachine &TM, bool Fast);
27 FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
2828
2929 /// createX86FloatingPointStackifierPass - This function returns a pass which
3030 /// converts floating point register references and pseudo instructions into
4343 ///
4444 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
4545 X86TargetMachine &tm,
46 bool fast, bool Verbose);
46 unsigned OptLevel, bool Verbose);
4747
4848 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
4949 /// to the specified MCE object.
133133 bool OptForSize;
134134
135135 public:
136 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
137 : SelectionDAGISel(tm, fast),
136 explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
137 : SelectionDAGISel(tm, OptLevel),
138138 TM(tm), X86Lowering(*TM.getTargetLowering()),
139139 Subtarget(&TM.getSubtarget()),
140140 OptForSize(false) {}
305305
306306 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
307307 SDNode *Root) const {
308 if (Fast) return false;
308 if (OptLevel == 0) return false;
309309
310310 if (U == Root)
311311 switch (U->getOpcode()) {
511511
512512
513513 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
514 /// This is only run if not in -fast mode (aka -O0).
514 /// This is only run if not in -O0 mode.
515515 /// This allows the instruction selector to pick more read-modify-write
516516 /// instructions. This is a common case:
517517 ///
713713 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
714714
715715 DEBUG(BB->dump());
716 if (!Fast)
716 if (OptLevel != 0)
717717 PreprocessForRMW();
718718
719 // FIXME: This should only happen when not -fast.
719 // FIXME: This should only happen when not compiled with -O0.
720720 PreprocessForFPConvert();
721721
722722 // Codegen the basic block.
17431743 /// createX86ISelDag - This pass converts a legalized DAG into a
17441744 /// X86-specific DAG, ready for instruction scheduling.
17451745 ///
1746 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1747 return new X86DAGToDAGISel(TM, Fast);
1748 }
1746 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
1747 return new X86DAGToDAGISel(TM, OptLevel);
1748 }
179179 // Pass Pipeline Configuration
180180 //===----------------------------------------------------------------------===//
181181
182 bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
182 bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
183183 // Install an instruction selector.
184 PM.add(createX86ISelDag(*this, Fast));
184 PM.add(createX86ISelDag(*this, OptLevel));
185185
186186 // If we're using Fast-ISel, clean up the mess.
187187 if (EnableFastISel)
193193 return false;
194194 }
195195
196 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
196 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
197197 // Calculate and set max stack object alignment early, so we can decide
198198 // whether we will need stack realignment (and thus FP).
199199 PM.add(createX86MaxStackAlignmentCalculatorPass());
200200 return false; // -print-machineinstr shouldn't print after this.
201201 }
202202
203 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
203 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
204204 PM.add(createX86FloatingPointStackifierPass());
205205 return true; // -print-machineinstr should print after this.
206206 }
207207
208 bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
209 bool Verbose, raw_ostream &Out) {
208 bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
209 unsigned OptLevel,
210 bool Verbose,
211 raw_ostream &Out) {
210212 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
211213 if (AsmPrinterCtor)
212 PM.add(AsmPrinterCtor(Out, *this, Fast, Verbose));
213 return false;
214 }
215
216 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
214 PM.add(AsmPrinterCtor(Out, *this, OptLevel, Verbose));
215 return false;
216 }
217
218 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
217219 bool DumpAsm, MachineCodeEmitter &MCE) {
218220 // FIXME: Move this to TargetJITInfo!
219221 // On Darwin, do not override 64-bit setting made in X86TargetMachine().
235237 if (DumpAsm) {
236238 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
237239 if (AsmPrinterCtor)
238 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
239 }
240
241 return false;
242 }
243
244 bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
245 bool DumpAsm, MachineCodeEmitter &MCE) {
240 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
241 }
242
243 return false;
244 }
245
246 bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
247 unsigned OptLevel, bool DumpAsm,
248 MachineCodeEmitter &MCE) {
246249 PM.add(createX86CodeEmitterPass(*this, MCE));
247250 if (DumpAsm) {
248251 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
249252 if (AsmPrinterCtor)
250 PM.add(AsmPrinterCtor(errs(), *this, Fast, true));
253 PM.add(AsmPrinterCtor(errs(), *this, OptLevel, true));
251254 }
252255
253256 return false;
4444 // set this functions to ctor pointer at startup time if they are linked in.
4545 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4646 X86TargetMachine &tm,
47 bool fast, bool verbose);
47 unsigned OptLevel, bool verbose);
4848 static AsmPrinterCtorFn AsmPrinterCtor;
4949
5050 public:
7373 }
7474
7575 // Set up the pass pipeline.
76 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
77 virtual bool addPreRegAlloc(PassManagerBase &PM, bool Fast);
78 virtual bool addPostRegAlloc(PassManagerBase &PM, bool Fast);
79 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
76 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
77 virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
78 virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
79 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
8080 bool Verbose, raw_ostream &Out);
81 virtual bool addCodeEmitter(PassManagerBase &PM, bool Fast,
81 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
8282 bool DumpAsm, MachineCodeEmitter &MCE);
83 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
83 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
8484 bool DumpAsm, MachineCodeEmitter &MCE);
8585
8686 /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
2323 FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
2424 FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
2525 XCoreTargetMachine &TM,
26 bool Fast, bool Verbose);
26 unsigned OptLevel, bool Verbose);
2727 } // end namespace llvm;
2828
2929 // Defines symbolic names for XCore registers. This defines a mapping from
5757 const XCoreSubtarget &Subtarget;
5858 public:
5959 XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
60 const TargetAsmInfo *T, bool F, bool V)
61 : AsmPrinter(O, TM, T, F, V), DW(0),
60 const TargetAsmInfo *T, unsigned OL, bool V)
61 : AsmPrinter(O, TM, T, OL, V), DW(0),
6262 Subtarget(*TM.getSubtargetImpl()) {}
6363
6464 virtual const char *getPassName() const {
104104 ///
105105 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
106106 XCoreTargetMachine &tm,
107 bool fast, bool verbose) {
108 return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast, verbose);
107 unsigned OptLevel,
108 bool verbose) {
109 return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
109110 }
110111
111112 // PrintEscapedString - Print each character of the specified string, escaping
5454 return 0;
5555 }
5656
57 bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
57 bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
58 unsigned OptLevel) {
5859 PM.add(createXCoreISelDag(*this));
5960 return false;
6061 }
6162
62 bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
63 bool Verbose, raw_ostream &Out) {
63 bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
64 unsigned OptLevel,
65 bool Verbose,
66 raw_ostream &Out) {
6467 // Output assembly language.
65 PM.add(createXCoreCodePrinterPass(Out, *this, Fast, Verbose));
68 PM.add(createXCoreCodePrinterPass(Out, *this, OptLevel, Verbose));
6669 return false;
6770 }
5151 static unsigned getModuleMatchQuality(const Module &M);
5252
5353 // Pass Pipeline Configuration
54 virtual bool addInstSelector(PassManagerBase &PM, bool Fast);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast,
54 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
5656 bool Verbose, raw_ostream &Out);
5757 };
5858
None ; RUN: llvm-as < %s | llc -fast
0 ; RUN: llvm-as < %s | llc -O0
11
22 define float @test(i32 %tmp12771278) {
33 switch i32 %tmp12771278, label %bb1279 [
None ; RUN: llvm-as < %s | llc -fast
0 ; RUN: llvm-as < %s | llc -O0
11
22 %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
33 @cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=2]
None ; RUN: llvm-as < %s | llc -fast
0 ; RUN: llvm-as < %s | llc -O0
11 ; PR 1323
22
33 ; ModuleID = 'test.bc'
None ; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -fast -relocation-model=pic -o -
0 ; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
11 ; PR1638
22
33 @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1]
0 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin
1 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -fast -regalloc=local
1 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
22
33 %struct.CGPoint = type { double, double }
44 %struct.NSArray = type { %struct.NSObject }
None ; RUN: llvm-as < %s | llc -march=x86 -fast -fast-isel=false | grep mov | count 5
0 ; RUN: llvm-as < %s | llc -march=x86 -O0 -fast-isel=false | grep mov | count 5
11 ; PR2343
22
33 %llvm.dbg.anchor.type = type { i32, i32 }
None ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast
0 ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0
11
22 define fastcc void @optimize_bit_field() nounwind {
33 bb4:
None ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil
0 ; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
11 ; rdar://6787136
22
33 %struct.X = type { i8, [32 x i8] }
0 ; RUN: llvm-as < %s | llc -march=x86 | grep {jo} | count 2
11 ; RUN: llvm-as < %s | llc -march=x86 | grep {jb} | count 2
2 ; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jo} | count 2
3 ; RUN: llvm-as < %s | llc -march=x86 -fast | grep {jb} | count 2
2 ; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jo} | count 2
3 ; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {jb} | count 2
44
55 @ok = internal constant [4 x i8] c"%d\0A\00"
66 @no = internal constant [4 x i8] c"no\0A\00"
None ; RUN: llvm-as < %s | llc -march=x86 -fast
0 ; RUN: llvm-as < %s | llc -march=x86 -O0
11
22 ; This file is for regression tests for cases where FastISel needs
33 ; to gracefully bail out and let SelectionDAGISel take over.
None ; RUN: llvm-as < %s | llc -march=x86-64 -fast | grep movslq
1 ; RUN: llvm-as < %s | llc -march=x86 -fast
0 ; RUN: llvm-as < %s | llc -march=x86-64 -O0 | grep movslq
1 ; RUN: llvm-as < %s | llc -march=x86 -O0
22 ; PR3181
33
44 ; GEP indices are interpreted as signed integers, so they
None ; RUN: llvm-as < %s | llc -march=x86 -fast | grep {sarl \$80, %eax}
0 ; RUN: llvm-as < %s | llc -march=x86 -O0 | grep {sarl \$80, %eax}
11 ; PR3242
22
33 define i32 @foo(i32 %x) nounwind {
None ; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | count 3
1 ; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | count 1
0 ; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
1 ; RUN: llvm-as < %s | llc -disable-fp-elim -O0 -mcpu=i486 | grep 3058016715 | count 1
22 ;; magic constants are 3.999f and half of 3.999
33 ; ModuleID = '1489.c'
44 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 | grep movsd | count 5
1 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -fast | grep movsd | count 5
1 ; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
22
33 @x = external global double
44
0 ; RUN: llvm-as < %s | llc
1 ; RUN: llvm-as < %s | llc -fast
1 ; RUN: llvm-as < %s | llc -O0
22 %llvm.dbg.anchor.type = type { i32, i32 }
33 %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
44 %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
None ; RUN: llvm-as < %s | llc -fast | grep "\\"foo" | count 3
0 ; RUN: llvm-as < %s | llc -O0 | grep "\\"foo" | count 3
11 ; 1 declaration, 1 definition and 1 pubnames entry.
22 target triple = "i386-apple-darwin*"
33 %llvm.dbg.anchor.type = type { i32, i32 }
None ; RUN: llvm-as < %s | llc -fast | grep "label" | count 8
0 ; RUN: llvm-as < %s | llc -O0 | grep "label" | count 8
11 ; PR2614
22 ; XFAIL: *
33
None ; RUN: llvm-as < %s | llc -fast | %prcontext ST 1 | grep 0x1 | count 1
0 ; RUN: llvm-as < %s | llc -O0 | %prcontext ST 1 | grep 0x1 | count 1
11
22 target triple = "i386-apple-darwin9.6"
33 %llvm.dbg.anchor.type = type { i32, i32 }
0 // This is a regression test on debug info to make sure that we can get a
11 // meaningful stack trace from a C++ program.
22 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
3 // RUN: llc --disable-fp-elim -o %t.s -f -fast -relocation-model=pic
3 // RUN: llc --disable-fp-elim -o %t.s -f -O0 -relocation-model=pic
44 // RUN: %compile_c %t.s -o %t.o
55 // RUN: %link %t.o -o %t.exe
66 // RUN: echo {break DeepStack::deepest\nrun 17\nwhere\n} > %t.in
0 // This is a regression test on debug info to make sure that we can access
11 // qualified global names.
22 // RUN: %llvmgcc -S -O0 -g %s -o - | llvm-as | \
3 // RUN: llc --disable-fp-elim -o %t.s -f -fast
3 // RUN: llc --disable-fp-elim -o %t.s -f -O0
44 // RUN: %compile_c %t.s -o %t.o
55 // RUN: %link %t.o -o %t.exe
66 // RUN: %llvmdsymutil %t.exe
None // RUN: %llvmgcc -c -g %s -o - | llc -fast -f -o %t.s
0 // RUN: %llvmgcc -c -g %s -o - | llc -O0 -f -o %t.s
11 // RUN: %compile_c %t.s -o %t.o
22 // PR4025
33
5454
5555 static cl::opt Force("f", cl::desc("Overwrite output files"));
5656
57 static cl::opt Fast("fast",
58 cl::desc("Generate code quickly, potentially sacrificing code quality"));
57 // Determine optimization level. Level -O0 is equivalent to "fast" code gen.
58 static cl::opt
59 OptLevel("O",
60 cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
61 cl::Prefix,
62 cl::ZeroOrMore,
63 cl::init(3));
5964
6065 static cl::opt
6166 TargetTriple("mtriple", cl::desc("Override target triple for module"));
256261 PM.add(createVerifierPass());
257262
258263 // Ask the target to add backend passes as necessary.
259 if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, Fast)) {
264 if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
260265 std::cerr << argv[0] << ": target does not support generation of this"
261266 << " file type!\n";
262267 if (Out != &outs()) delete Out;
282287 // Override default to generate verbose assembly.
283288 Target.setAsmVerbosityDefault(true);
284289
285 switch (Target.addPassesToEmitFile(Passes, *Out, FileType, Fast)) {
290 switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
286291 default:
287292 assert(0 && "Invalid file model!");
288293 return 1;
303308 break;
304309 }
305310
306 if (Target.addPassesToEmitFileFinish(Passes, MCE, Fast)) {
311 if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
307312 std::cerr << argv[0] << ": target does not support generation of this"
308313 << " file type!\n";
309314 if (Out != &outs()) delete Out;
649649 O << "\";\n\n";
650650
651651 O << " if (TAI->doesSupportDebugInformation() &&\n"
652 << " DW->ShouldEmitDwarfDebug() && !Fast) {\n"
652 << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
653653 << " DebugLoc CurDL = MI->getDebugLoc();\n\n"
654654 << " if (!CurDL.isUnknown()) {\n"
655655 << " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
464464 NumInputRootOps = N->getNumChildren();
465465
466466 if (DisablePatternForFastISel(N, CGP))
467 emitCheck("!Fast");
467 emitCheck("OptLevel != 0");
468468
469469 emitCheck(PredicateCheck);
470470 }