llvm.org GIT mirror llvm / 2e7e34b
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Barton 8 years ago
3 changed file(s) with 29 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
566566 bits<4> Rt2;
567567
568568 // Encode instruction operands.
569 let Inst{3-0} = src1{3-0};
570 let Inst{5} = src1{4};
569 let Inst{3-0} = src1{4-1};
570 let Inst{5} = src1{0};
571571 let Inst{15-12} = Rt;
572572 let Inst{19-16} = Rt2;
573573
616616 bits<4> src2;
617617
618618 // Encode instruction operands.
619 let Inst{3-0} = dst1{3-0};
620 let Inst{5} = dst1{4};
619 let Inst{3-0} = dst1{4-1};
620 let Inst{5} = dst1{0};
621621 let Inst{15-12} = src1;
622622 let Inst{19-16} = src2;
623623
41974197 DecodeStatus S = MCDisassembler::Success;
41984198 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
41994199 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4200 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4200 unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
42014201 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4202 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4202 Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
42034203
42044204 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
42054205 S = MCDisassembler::SoftFail;
42234223 DecodeStatus S = MCDisassembler::Success;
42244224 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
42254225 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4226 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4226 unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
42274227 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4228 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4228 Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
42294229
42304230 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
42314231 S = MCDisassembler::SoftFail;
194194
195195 @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
196196 vmov r0, r1, d16
197
198 @ Between two single precision registers and two core registers
199 vmov s3, s4, r1, r2
200 vmov s2, s3, r1, r2
201 vmov r1, r2, s3, s4
202 vmov r1, r2, s2, s3
203 @ CHECK: vmov s3, s4, r1, r2 @ encoding: [0x31,0x1a,0x42,0xec]
204 @ CHECK: vmov s2, s3, r1, r2 @ encoding: [0x11,0x1a,0x42,0xec]
205 @ CHECK: vmov r1, r2, s3, s4 @ encoding: [0x31,0x1a,0x52,0xec]
206 @ CHECK: vmov r1, r2, s2, s3 @ encoding: [0x11,0x1a,0x52,0xec]
207
208 @ Between one double precision register and two core registers
209 vmov d15, r1, r2
210 vmov d16, r1, r2
211 vmov r1, r2, d15
212 vmov r1, r2, d16
213 @ CHECK: vmov d15, r1, r2 @ encoding: [0x1f,0x1b,0x42,0xec]
214 @ CHECK: vmov d16, r1, r2 @ encoding: [0x30,0x1b,0x42,0xec]
215 @ CHECK: vmov r1, r2, d15 @ encoding: [0x1f,0x1b,0x52,0xec]
216 @ CHECK: vmov r1, r2, d16 @ encoding: [0x30,0x1b,0x52,0xec]
217
197218
198219 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
199220 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]