llvm.org GIT mirror llvm / 2e6ca7d
[WebAssembly] Enable SSA lowering and other pre-regalloc passes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247008 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 5 years ago
2 changed file(s) with 43 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
163163
164164 void WebAssemblyPassConfig::addPreRegAlloc() {}
165165
166 void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
166 void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
167 // This is list is derived from the regalloc pass list used in
168 // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
169 // don't run the actual register allocator, but we do run the passes which
170 // lower SSA form, so after these passes are complete, we have non-SSA
171 // virtual registers.
172
173 if (Optimized) {
174 addPass(&ProcessImplicitDefsID);
175 addPass(&LiveVariablesID);
176 addPass(&MachineLoopInfoID);
177 }
178
179 addPass(&PHIEliminationID);
180 addPass(&TwoAddressInstructionPassID, false);
181
182 if (Optimized) {
183 addPass(&RegisterCoalescerID);
184 addPass(&MachineSchedulerID);
185 }
186 }
167187
168188 void WebAssemblyPassConfig::addPostRegAlloc() {
169189 // FIXME: the following passes dislike virtual registers. Disable them for now
0 ; RUN: llc < %s -asm-verbose=false | FileCheck %s
1
2 ; Test that phis are lowered.
3
4 target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
5 target triple = "wasm32-unknown-unknown"
6
7 ; CHECK-LABEL: test0
8 ; CHECK: (setlocal [[REG:@.*]] (argument 0))
9 ; CHECK: (setlocal [[REG]] (sdiv [[REG]] {{.*}}))
10 ; CHECK: (return [[REG]])
11 define i32 @test0(i32 %p) {
12 entry:
13 %t = icmp slt i32 %p, 0
14 br i1 %t, label %true, label %done
15 true:
16 %a = sdiv i32 %p, 3
17 br label %done
18 done:
19 %s = phi i32 [ %a, %true ], [ %p, %entry ]
20 ret i32 %s
21 }