llvm.org GIT mirror llvm / 2e68b6f
Convert MaskedValueIsZero and all its users to use APInt. Also add a SignBitIsZero function to simplify a common use case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
10 changed file(s) with 107 addition(s) and 72 deletion(s). Raw diff Collapse all Expand all
554554 SDOperand FoldSetCC(MVT::ValueType VT, SDOperand N1,
555555 SDOperand N2, ISD::CondCode Cond);
556556
557 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
558 /// use this predicate to simplify operations downstream.
559 bool SignBitIsZero(SDOperand Op, unsigned Depth = 0) const;
560
557561 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
558562 /// use this predicate to simplify operations downstream. Op and Mask are
559563 /// known to be the same type.
560 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
564 bool MaskedValueIsZero(SDOperand Op, const APInt &Mask, unsigned Depth = 0)
561565 const;
562566
563567 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
217217 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
218218 SDOperand ReduceLoadWidth(SDNode *N);
219219
220 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
220 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask);
221221
222222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
223223 /// looking for aliasing nodes and adding them to the Aliases vector.
12251225 // If we know the sign bits of both operands are zero, strength reduce to a
12261226 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
12271227 if (!MVT::isVector(VT)) {
1228 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1229 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1230 DAG.MaskedValueIsZero(N0, SignBit))
1228 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
12311229 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
12321230 }
12331231 // fold (sdiv X, pow2) -> simple ops after legalize
13431341 // If we know the sign bits of both operands are zero, strength reduce to a
13441342 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
13451343 if (!MVT::isVector(VT)) {
1346 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1347 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1348 DAG.MaskedValueIsZero(N0, SignBit))
1344 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
13491345 return DAG.getNode(ISD::UREM, VT, N0, N1);
13501346 }
13511347
15871583 ConstantSDNode *N0C = dyn_cast(N0);
15881584 ConstantSDNode *N1C = dyn_cast(N1);
15891585 MVT::ValueType VT = N1.getValueType();
1586 unsigned BitWidth = MVT::getSizeInBits(VT);
15901587
15911588 // fold vector ops
15921589 if (MVT::isVector(VT)) {
16071604 if (N1C && N1C->isAllOnesValue())
16081605 return N0;
16091606 // if (and x, c) is known to be zero, return 0
1610 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1607 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
1608 APInt::getAllOnesValue(BitWidth)))
16111609 return DAG.getConstant(0, VT);
16121610 // reassociate and
16131611 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
16201618 return N1;
16211619 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
16221620 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1623 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1624 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1625 ~N1C->getValue() & InMask)) {
1621 SDOperand N0Op0 = N0.getOperand(0);
1622 APInt Mask = ~N1C->getAPIntValue();
1623 Mask.trunc(N0Op0.getValueSizeInBits());
1624 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
16261625 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1627 N0.getOperand(0));
1626 N0Op0);
16281627
16291628 // Replace uses of the AND with uses of the Zero extend node.
16301629 CombineTo(N, Zext);
16921691 MVT::ValueType EVT = LN0->getMemoryVT();
16931692 // If we zero all the possible extended bits, then we can turn this into
16941693 // a zextload if we are running before legalize or the operation is legal.
1695 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1694 unsigned BitWidth = N1.getValueSizeInBits();
1695 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1696 BitWidth - MVT::getSizeInBits(EVT))) &&
16961697 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
16971698 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
16981699 LN0->getBasePtr(), LN0->getSrcValue(),
17111712 MVT::ValueType EVT = LN0->getMemoryVT();
17121713 // If we zero all the possible extended bits, then we can turn this into
17131714 // a zextload if we are running before legalize or the operation is legal.
1714 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1715 unsigned BitWidth = N1.getValueSizeInBits();
1716 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1717 BitWidth - MVT::getSizeInBits(EVT))) &&
17151718 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
17161719 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
17171720 LN0->getBasePtr(), LN0->getSrcValue(),
17791782 ConstantSDNode *N0C = dyn_cast(N0);
17801783 ConstantSDNode *N1C = dyn_cast(N1);
17811784 MVT::ValueType VT = N1.getValueType();
1782 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
17831785
17841786 // fold vector ops
17851787 if (MVT::isVector(VT)) {
18031805 if (N1C && N1C->isAllOnesValue())
18041806 return N1;
18051807 // fold (or x, c) -> c iff (x & ~c) == 0
1806 if (N1C &&
1807 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1808 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
18081809 return N1;
18091810 // reassociate or
18101811 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
18701871 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
18711872 // We can only do this xform if we know that bits from X that are set in C2
18721873 // but not in C1 are already zero. Likewise for Y.
1873 uint64_t LHSMask = cast(N0.getOperand(1))->getValue();
1874 uint64_t RHSMask = cast(N1.getOperand(1))->getValue();
1874 const APInt &LHSMask =
1875 cast(N0.getOperand(1))->getAPIntValue();
1876 const APInt &RHSMask =
1877 cast(N1.getOperand(1))->getAPIntValue();
18751878
18761879 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
18771880 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
22702273 if (N1C && N1C->isNullValue())
22712274 return N0;
22722275 // if (shl x, c) is known to be zero, return 0
2273 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2276 if (DAG.MaskedValueIsZero(SDOperand(N, 0),
2277 APInt::getAllOnesValue(MVT::getSizeInBits(VT))))
22742278 return DAG.getConstant(0, VT);
22752279 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
22762280 return SDOperand(N, 0);
23622366
23632367
23642368 // If the sign bit is known to be zero, switch this to a SRL.
2365 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2369 if (DAG.SignBitIsZero(N0))
23662370 return DAG.getNode(ISD::SRL, VT, N0, N1);
23672371
23682372 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
23892393 if (N1C && N1C->isNullValue())
23902394 return N0;
23912395 // if (srl x, c) is known to be zero, return 0
2392 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2396 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0),
2397 APInt::getAllOnesValue(OpSizeInBits)))
23932398 return DAG.getConstant(0, VT);
23942399
23952400 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
30253030 /// GetDemandedBits - See if the specified operand can be simplified with the
30263031 /// knowledge that only the bits specified by Mask are used. If so, return the
30273032 /// simpler operand, otherwise return a null SDOperand.
3028 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
3033 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) {
30293034 switch (V.getOpcode()) {
30303035 default: break;
30313036 case ISD::OR:
30433048 if (ConstantSDNode *RHSC = dyn_cast(V.getOperand(1))) {
30443049 // See if we can recursively simplify the LHS.
30453050 unsigned Amt = RHSC->getValue();
3046 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
3047 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
3051 APInt NewMask = Mask << Amt;
3052 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
30483053 if (SimplifyLHS.Val) {
30493054 return DAG.getNode(ISD::SRL, V.getValueType(),
30503055 SimplifyLHS, V.getOperand(1));
31463151 SDOperand N1 = N->getOperand(1);
31473152 MVT::ValueType VT = N->getValueType(0);
31483153 MVT::ValueType EVT = cast(N1)->getVT();
3154 unsigned VTBits = MVT::getSizeInBits(VT);
31493155 unsigned EVTBits = MVT::getSizeInBits(EVT);
31503156
31513157 // fold (sext_in_reg c1) -> c1
31633169 }
31643170
31653171 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3166 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3172 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
31673173 return DAG.getZeroExtendInReg(N0, EVT);
31683174
31693175 // fold operands of sext_in_reg based on knowledge that the top bits are not
32553261 // See if we can simplify the input to this truncate through knowledge that
32563262 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
32573263 // -> trunc y
3258 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3264 SDOperand Shorter =
3265 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3266 MVT::getSizeInBits(VT)));
32593267 if (Shorter.Val)
32603268 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
32613269
44674475 // only the low bits are being used. For example:
44684476 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
44694477 SDOperand Shorter =
4470 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT()));
4478 GetDemandedBits(Value,
4479 APInt::getLowBitsSet(Value.getValueSizeInBits(),
4480 MVT::getSizeInBits(ST->getMemoryVT())));
44714481 AddToWorkList(Value.Val);
44724482 if (Shorter.Val)
44734483 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
17781778 case Legal:
17791779 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
17801780 break;
1781 case Promote:
1781 case Promote: {
17821782 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
17831783
17841784 // The top bits of the promoted condition are not necessarily zero, ensure
17851785 // that the value is properly zero extended.
1786 unsigned BitWidth = Tmp2.getValueSizeInBits();
17861787 if (!DAG.MaskedValueIsZero(Tmp2,
1787 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1788 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
17881789 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
17891790 break;
1791 }
17901792 }
17911793
17921794 // Basic block destination (Op#2) is always legal.
26412643 case Legal:
26422644 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
26432645 break;
2644 case Promote:
2646 case Promote: {
26452647 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
26462648 // Make sure the condition is either zero or one.
2649 unsigned BitWidth = Tmp1.getValueSizeInBits();
26472650 if (!DAG.MaskedValueIsZero(Tmp1,
2648 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2651 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
26492652 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
26502653 break;
2654 }
26512655 }
26522656 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
26532657 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
63376341 SDOperand LL, LH, RL, RH;
63386342 ExpandOp(Node->getOperand(0), LL, LH);
63396343 ExpandOp(Node->getOperand(1), RL, RH);
6340 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6344 unsigned OuterBitSize = Op.getValueSizeInBits();
6345 unsigned InnerBitSize = RH.getValueSizeInBits();
63416346 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
63426347 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6343 // FIXME: generalize this to handle other bit sizes
6344 if (LHSSB == 32 && RHSSB == 32 &&
6345 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6346 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6348 if (DAG.MaskedValueIsZero(Op.getOperand(0),
6349 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
6350 DAG.MaskedValueIsZero(Op.getOperand(1),
6351 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
63476352 // The inputs are both zero-extended.
63486353 if (HasUMUL_LOHI) {
63496354 // We can emit a umul_lohi.
63586363 break;
63596364 }
63606365 }
6361 if (LHSSB > BitSize && RHSSB > BitSize) {
6366 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
63626367 // The input values are both sign-extended.
63636368 if (HasSMUL_LOHI) {
63646369 // We can emit a smul_lohi.
506506 SDOperand LL, LH, RL, RH;
507507 GetExpandedOp(N->getOperand(0), LL, LH);
508508 GetExpandedOp(N->getOperand(1), RL, RH);
509 unsigned OuterBitSize = MVT::getSizeInBits(VT);
509510 unsigned BitSize = MVT::getSizeInBits(NVT);
510511 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
511512 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
512513
513 // FIXME: generalize this to handle other bit sizes
514 if (LHSSB == 32 && RHSSB == 32 &&
515 DAG.MaskedValueIsZero(N->getOperand(0), 0xFFFFFFFF00000000ULL) &&
516 DAG.MaskedValueIsZero(N->getOperand(1), 0xFFFFFFFF00000000ULL)) {
514 if (DAG.MaskedValueIsZero(N->getOperand(0),
515 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
516 DAG.MaskedValueIsZero(N->getOperand(1),
517 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
517518 // The inputs are both zero-extended.
518519 if (HasUMUL_LOHI) {
519520 // We can emit a umul_lohi.
445445
446446 // The top bits of the promoted condition are not necessarily zero, ensure
447447 // that the value is properly zero extended.
448 unsigned BitWidth = Cond.getValueSizeInBits();
448449 if (!DAG.MaskedValueIsZero(Cond,
449 MVT::getIntVTBitMask(Cond.getValueType())^1)) {
450 APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
450451 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
451452 MarkNewNodes(Cond.Val);
452453 }
462463
463464 // The top bits of the promoted condition are not necessarily zero, ensure
464465 // that the value is properly zero extended.
466 unsigned BitWidth = Cond.getValueSizeInBits();
465467 if (!DAG.MaskedValueIsZero(Cond,
466 MVT::getIntVTBitMask(Cond.getValueType())^1)) {
468 APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
467469 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
468470 MarkNewNodes(Cond.Val);
469471 }
11321132 return SDOperand();
11331133 }
11341134
1135 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
1136 /// use this predicate to simplify operations downstream.
1137 bool SelectionDAG::SignBitIsZero(SDOperand Op, unsigned Depth) const {
1138 unsigned BitWidth = Op.getValueSizeInBits();
1139 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
1140 }
1141
11351142 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
11361143 /// this predicate to simplify operations downstream. Mask is known to be zero
11371144 /// for bits that V cannot have.
1138 bool SelectionDAG::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
1145 bool SelectionDAG::MaskedValueIsZero(SDOperand Op, const APInt &Mask,
11391146 unsigned Depth) const {
1140 // The masks are not wide enough to represent this type! Should use APInt.
1141 if (Op.getValueType() == MVT::i128)
1142 return false;
1143
1144 uint64_t KnownZero, KnownOne;
1147 APInt KnownZero, KnownOne;
11451148 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
11461149 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
11471150 return (KnownZero & Mask) == Mask;
52105210 /// specified in the .td file (e.g. 255).
52115211 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
52125212 int64_t DesiredMaskS) const {
5213 uint64_t ActualMask = RHS->getValue();
5214 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5213 const APInt &ActualMask = RHS->getAPIntValue();
5214 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
52155215
52165216 // If the actual mask exactly matches, success!
52175217 if (ActualMask == DesiredMask)
52185218 return true;
52195219
52205220 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5221 if (ActualMask & ~DesiredMask)
5221 if (ActualMask.intersects(~DesiredMask))
52225222 return false;
52235223
52245224 // Otherwise, the DAG Combiner may have proven that the value coming in is
52255225 // either already zero or is not demanded. Check for known zero input bits.
5226 uint64_t NeededMask = DesiredMask & ~ActualMask;
5226 APInt NeededMask = DesiredMask & ~ActualMask;
52275227 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
52285228 return true;
52295229
52385238 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
52395239 /// specified in the .td file (e.g. 255).
52405240 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5241 int64_t DesiredMaskS) const {
5242 uint64_t ActualMask = RHS->getValue();
5243 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5241 int64_t DesiredMaskS) const {
5242 const APInt &ActualMask = RHS->getAPIntValue();
5243 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
52445244
52455245 // If the actual mask exactly matches, success!
52465246 if (ActualMask == DesiredMask)
52475247 return true;
52485248
52495249 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5250 if (ActualMask & ~DesiredMask)
5250 if (ActualMask.intersects(~DesiredMask))
52515251 return false;
52525252
52535253 // Otherwise, the DAG Combiner may have proven that the value coming in is
52545254 // either already zero or is not demanded. Check for known zero input bits.
5255 uint64_t NeededMask = DesiredMask & ~ActualMask;
5256
5257 uint64_t KnownZero, KnownOne;
5255 APInt NeededMask = DesiredMask & ~ActualMask;
5256
5257 APInt KnownZero, KnownOne;
52585258 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
52595259
52605260 // If all the missing bits in the or are already known to be set, match!
11861186 cast(N0.getOperand(1))->getValue() == 1) {
11871187 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
11881188 // can only do this if the top bits are known zero.
1189 unsigned BitWidth = N0.getValueSizeInBits();
11891190 if (DAG.MaskedValueIsZero(N0,
1190 MVT::getIntVTBitMask(N0.getValueType())-1)){
1191 APInt::getHighBitsSet(BitWidth,
1192 BitWidth-1))) {
11911193 // Okay, get the un-inverted input value.
11921194 SDOperand Val;
11931195 if (N0.getOpcode() == ISD::XOR)
13731375 if (N0.getOpcode() == ISD::XOR)
13741376 // If we know that all of the inverted bits are zero, don't bother
13751377 // performing the inversion.
1376 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1377 return DAG.getSetCC(VT, N0.getOperand(0),
1378 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1379 N0.getValueType()), Cond);
1378 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1379 return
1380 DAG.getSetCC(VT, N0.getOperand(0),
1381 DAG.getConstant(LHSR->getAPIntValue() ^
1382 RHSC->getAPIntValue(),
1383 N0.getValueType()),
1384 Cond);
13801385 }
13811386
13821387 // Turn (C1-X) == C2 --> X == C1-C2
13831388 if (ConstantSDNode *SUBC = dyn_cast(N0.getOperand(0))) {
13841389 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1385 return DAG.getSetCC(VT, N0.getOperand(1),
1386 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1387 N0.getValueType()), Cond);
1390 return
1391 DAG.getSetCC(VT, N0.getOperand(1),
1392 DAG.getConstant(SUBC->getAPIntValue() -
1393 RHSC->getAPIntValue(),
1394 N0.getValueType()),
1395 Cond);
13881396 }
13891397 }
13901398 }
9090 // see if the missing bits (0x1000) are already known zero if not, the zap
9191 // isn't okay to do, as it won't clear all the required bits.
9292 if (BitsToCheck &&
93 !CurDAG->MaskedValueIsZero(LHS, BitsToCheck))
93 !CurDAG->MaskedValueIsZero(LHS,
94 APInt(LHS.getValueSizeInBits(),
95 BitsToCheck)))
9496 return 0;
9597
9698 return Result;
818818 // On x86-64, the resultant disp must fit in 32-bits.
819819 isInt32(AM.Disp + CN->getSignExtended()) &&
820820 // Check to see if the LHS & C is zero.
821 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) {
821 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
822822 AM.Disp += CN->getValue();
823823 return false;
824824 }