llvm.org GIT mirror llvm / 2e48a70
rename isStore -> mayStore to more accurately reflect what it captures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
17 changed file(s) with 47 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
113113 (void) llvm::createPredicateSimplifierPass();
114114 (void) llvm::createCodeGenPreparePass();
115115 (void) llvm::createGVNPass();
116 (void) llvm::createValueInfoPass();
116117
117118 (void)new llvm::IntervalPartition();
118119 (void)new llvm::FindUsedTypes();
4949 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
5050 const unsigned M_LOAD_FLAG = 1 << 5;
5151
52 /// M_STORE_FLAG - This flag is set to any instruction that could possibly
52 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
5353 /// modify memory. Instructions with this flag set are not necessarily simple
5454 /// store instructions, they may store a modified value based on their operands,
5555 /// or may not actually modify anything, for example.
56 const unsigned M_STORE_FLAG = 1 << 6;
56 const unsigned M_MAY_STORE_FLAG = 1 << 6;
5757
5858 const unsigned M_INDIRECT_FLAG = 1 << 7;
5959 const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8;
282282 return get(Opcode).Flags & M_LOAD_FLAG;
283283 }
284284
285 /// isStore - Return true if this instruction could possibly modify memory.
285 /// mayStore - Return true if this instruction could possibly modify memory.
286286 /// Instructions with this flag set are not necessarily simple store
287287 /// instructions, they may store a modified value based on their operands, or
288288 /// may not actually modify anything, for example.
289 bool isStore(MachineOpCode Opcode) const {
290 return get(Opcode).Flags & M_STORE_FLAG;
289 bool mayStore(MachineOpCode Opcode) const {
290 return get(Opcode).Flags & M_MAY_STORE_FLAG;
291291 }
292292
293293 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
338338
339339 //===----------------------------------------------------------------------===//
340340 //
341 // ValueInfo - This pass performs FIXME
342 //
343 FunctionPass *createValueInfoPass();
344
345 //===----------------------------------------------------------------------===//
346 //
341347 // CodeGenPrepare - This pass prepares a function for instruction selection.
342348 //
343349 FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0);
352352 const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
353353 if (TID.Flags & M_CALL_FLAG)
354354 Time += 10;
355 else if (TID.Flags & (M_LOAD_FLAG|M_STORE_FLAG))
355 else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
356356 Time += 2;
357357 else
358358 ++Time;
891891 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
892892
893893 // Store doubleword
894 let isStore = 1 in
894 let mayStore = 1 in
895895 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
896896 "str", "d $src, $addr",
897897 []>, Requires<[IsARM, HasV5T]>;
944944 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
945945 []>;
946946
947 let isStore = 1 in
947 let mayStore = 1 in
948948 def STM : AXI4<0x0, (outs),
949949 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
950950 StFrm, "stm${p}${addr:submode} $addr, $src1",
293293 "str $src, $addr",
294294 [(store GPR:$src, t_addrmode_sp:$addr)]>;
295295
296 let isStore = 1 in {
296 let mayStore = 1 in {
297297 // Special instruction for spill. It cannot clobber condition register
298298 // when it's expanded by eliminateCallFramePseudoInstr().
299299 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
310310 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
311311 "pop $dst1", []>;
312312
313 let isStore = 1 in
313 let mayStore = 1 in
314314 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
315315 "push $src1", []>;
316316
121121 []>;
122122 } // isLoad
123123
124 let isStore = 1 in {
124 let mayStore = 1 in {
125125 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
126126 variable_ops),
127127 "fstm${addr:submode}d${p} ${addr:base}, $src1",
131131 variable_ops),
132132 "fstm${addr:submode}s${p} ${addr:base}, $src1",
133133 []>;
134 } // isStore
134 } // mayStore
135135
136136 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
137137
904904 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
905905 else // tLDR has an extra register operand.
906906 MI.addOperand(MachineOperand::CreateReg(0, false));
907 } else if (TII.isStore(Opcode)) {
907 } else if (TII.mayStore(Opcode)) {
908908 // FIXME! This is horrific!!! We need register scavenging.
909909 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
910910 // also a ABI register so it's possible that is is the register that is
540540 def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
541541 "sub $dst = $imm, $src2">, isA;
542542
543 let isStore = 1 in {
543 let mayStore = 1 in {
544544 def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
545545 "st1 [$dstPtr] = $value">, isM;
546546 def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
7272 const TargetInstrDescriptor &TID = TII.get(Opcode);
7373
7474 isLoad = TID.Flags & M_LOAD_FLAG;
75 isStore = TID.Flags & M_STORE_FLAG;
75 isStore = TID.Flags & M_MAY_STORE_FLAG;
7676
7777 unsigned TSFlags = TID.TSFlags;
7878
512512 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
513513 isPPC64;
514514
515 let isStore = 1 in
515 let mayStore = 1 in
516516 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
517517 "stdux $rS, $dst", LdStSTD,
518518 []>, isPPC64;
637637 [(store GPRC:$rS, xaddr:$dst)]>,
638638 PPC970_DGroup_Cracked;
639639
640 let isStore = 1 in {
640 let mayStore = 1 in {
641641 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
642642 "stwux $rS, $rA, $rB", LdStGeneral,
643643 []>;
190190 bit isBarrier = 0; // Can control flow fall through this instruction?
191191 bit isCall = 0; // Is this instruction a call instruction?
192192 bit isLoad = 0; // Is this instruction a load instruction?
193 bit isStore = 0; // Is this instruction a store instruction?
193 bit mayStore = 0; // Can this instruction modify memory?
194194 bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
195195 bit isTwoAddress = 0; // Is this a two address instruction?
196196 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
188188 def SDNPOutFlag : SDNodeProperty; // Write a flag result
189189 def SDNPInFlag : SDNodeProperty; // Read a flag operand
190190 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
191 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'isStore'.
191 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
192192
193193 //===----------------------------------------------------------------------===//
194194 // Selection DAG Node definitions.
8484 isBarrier = R->getValueAsBit("isBarrier");
8585 isCall = R->getValueAsBit("isCall");
8686 isLoad = R->getValueAsBit("isLoad");
87 isStore = R->getValueAsBit("isStore");
87 mayStore = R->getValueAsBit("mayStore");
8888 isImplicitDef= R->getValueAsBit("isImplicitDef");
8989 bool isTwoAddress = R->getValueAsBit("isTwoAddress");
9090 isPredicable = R->getValueAsBit("isPredicable");
9494 bool isBarrier;
9595 bool isCall;
9696 bool isLoad;
97 bool isStore;
97 bool mayStore;
9898 bool isImplicitDef;
9999 bool isPredicable;
100100 bool isConvertibleToThreeAddress;
142142
143143 class InstAnalyzer {
144144 const CodeGenDAGPatterns &CDP;
145 bool &isStore;
145 bool &mayStore;
146146 bool &isLoad;
147147 bool &NeverHasSideEffects;
148148 public:
149149 InstAnalyzer(const CodeGenDAGPatterns &cdp,
150 bool &isstore, bool &isload, bool &nhse)
151 : CDP(cdp), isStore(isstore), isLoad(isload), NeverHasSideEffects(nhse) {
150 bool &maystore, bool &isload, bool &nhse)
151 : CDP(cdp), mayStore(maystore), isLoad(isload), NeverHasSideEffects(nhse) {
152152 }
153153
154154 void Analyze(Record *InstRecord) {
175175
176176 // If node writes to memory, it obviously stores to memory.
177177 if (OpInfo.hasProperty(SDNPMayStore)) {
178 isStore = true;
178 mayStore = true;
179179 } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
180180 // If this is an intrinsic, analyze it.
181181 if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
182 isStore = true; // Intrinsics that can write to memory are 'isStore'.
182 mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
183183 }
184184 }
185185
190190 };
191191
192192 void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
193 bool &isStore, bool &isLoad,
193 bool &mayStore, bool &isLoad,
194194 bool &NeverHasSideEffects) {
195 isStore = isLoad = NeverHasSideEffects = false;
196
197 InstAnalyzer(CDP, isStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
198
199 // InstAnalyzer only correctly analyzes isStore so far.
200 if (Inst.isStore) { // If the .td file explicitly sets isStore, use it.
195 mayStore = isLoad = NeverHasSideEffects = false;
196
197 InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef);
198
199 // InstAnalyzer only correctly analyzes mayStore so far.
200 if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it.
201201 // If we decided that this is a store from the pattern, then the .td file
202202 // entry is redundant.
203 if (isStore)
204 fprintf(stderr, "Warning: isStore flag explicitly set on instruction '%s'"
203 if (mayStore)
204 fprintf(stderr,
205 "Warning: mayStore flag explicitly set on instruction '%s'"
205206 " but flag already inferred from pattern.\n",
206207 Inst.getName().c_str());
207 isStore = true;
208 mayStore = true;
208209 }
209210
210211 // These two override everything.
279280 const OperandInfoMapTy &OpInfo,
280281 std::ostream &OS) {
281282 // Determine properties of the instruction from its pattern.
282 bool isStore, isLoad, NeverHasSideEffects;
283 InferFromPattern(Inst, isStore, isLoad, NeverHasSideEffects);
283 bool mayStore, isLoad, NeverHasSideEffects;
284 InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects);
284285
285286 if (NeverHasSideEffects && Inst.mayHaveSideEffects) {
286287 std::cerr << "error: Instruction '" << Inst.getName()
307308 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
308309 if (Inst.isCall) OS << "|M_CALL_FLAG";
309310 if (isLoad) OS << "|M_LOAD_FLAG";
310 if (isStore) OS << "|M_STORE_FLAG";
311 if (mayStore) OS << "|M_MAY_STORE_FLAG";
311312 if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
312313 if (Inst.isPredicable) OS << "|M_PREDICABLE";
313314 if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";