llvm.org GIT mirror llvm / 2e489c4
Re-enable 91381 with fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
4 changed file(s) with 41 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
979979 setTargetDAGCombine(ISD::SRL);
980980 setTargetDAGCombine(ISD::STORE);
981981 setTargetDAGCombine(ISD::MEMBARRIER);
982 setTargetDAGCombine(ISD::ZERO_EXTEND);
982983 if (Subtarget->is64Bit())
983984 setTargetDAGCombine(ISD::MUL);
984985
57515752 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
57525753
57535754 // Use sbb x, x to materialize carry bit into a GPR.
5754 // FIXME: Temporarily disabled since it breaks self-hosting. It's apparently
5755 // miscompiling ARMISelDAGToDAG.cpp.
5756 if (0 && !isFP && X86CC == X86::COND_B) {
5755 if (X86CC == X86::COND_B)
57575756 return DAG.getNode(ISD::AND, dl, MVT::i8,
57585757 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
57595758 DAG.getConstant(X86CC, MVT::i8), Cond),
57605759 DAG.getConstant(1, MVT::i8));
5761 }
57625760
57635761 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
57645762 DAG.getConstant(X86CC, MVT::i8), Cond);
93489346 }
93499347 }
93509348
9349 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9350 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9351 // (and (i32 x86isd::setcc_carry), 1)
9352 // This eliminates the zext. This transformation is necessary because
9353 // ISD::SETCC is always legalized to i8.
9354 DebugLoc dl = N->getDebugLoc();
9355 SDValue N0 = N->getOperand(0);
9356 EVT VT = N->getValueType(0);
9357 if (N0.getOpcode() == ISD::AND &&
9358 N0.hasOneUse() &&
9359 N0.getOperand(0).hasOneUse()) {
9360 SDValue N00 = N0.getOperand(0);
9361 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9362 return SDValue();
9363 ConstantSDNode *C = dyn_cast(N0.getOperand(1));
9364 if (!C || C->getZExtValue() != 1)
9365 return SDValue();
9366 return DAG.getNode(ISD::AND, dl, VT,
9367 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9368 N00.getOperand(0), N00.getOperand(1)),
9369 DAG.getConstant(1, VT));
9370 }
9371
9372 return SDValue();
9373 }
9374
93519375 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
93529376 DAGCombinerInfo &DCI) const {
93539377 SelectionDAG &DAG = DCI.DAG;
93679391 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
93689392 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
93699393 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9394 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
93709395 }
93719396
93729397 return SDValue();
13361336 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
13371337 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins),
13381338 "sbb{q}\t$dst, $dst",
1339 [(set GR64:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>;
1340
1341 def : Pat<(i64 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
1339 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1340
1341 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
13421342 (SETB_C64r)>;
13431343
13441344 //===----------------------------------------------------------------------===//
4040 def SDTX86SetCC : SDTypeProfile<1, 2,
4141 [SDTCisVT<0, i8>,
4242 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
43 def SDTX86SetCC_C : SDTypeProfile<1, 2,
44 [SDTCisInt<0>,
45 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
4346
4447 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
4548 SDTCisVT<2, i8>]>;
8689 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
8790 [SDNPHasChain]>;
8891 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
89 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC>;
92 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
9093
9194 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
9295 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
30673070 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
30683071 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
30693072 "sbb{w}\t$dst, $dst",
3070 [(set GR16:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>,
3073 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
30713074 OpSize;
30723075 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
30733076 "sbb{l}\t$dst, $dst",
3074 [(set GR32:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>;
3077 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
30753078 } // isCodeGenOnly
30763079
30773080 def SETEr : I<0x94, MRM0r,
41844187 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
41854188 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
41864189
4187 // (anyext (setcc_carry)) -> (zext (setcc_carry))
4188 def : Pat<(i16 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
4190 // (anyext (setcc_carry)) -> (setcc_carry)
4191 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
41894192 (SETB_C16r)>;
4190 def : Pat<(i32 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
4193 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
41914194 (SETB_C32r)>;
41924195
41934196 //===----------------------------------------------------------------------===//
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
1 ; XFAIL: *
21 ; rdar://7329206
32
43 ; Use sbb x, x to materialize carry bit in a GPR. The value is either