llvm.org GIT mirror llvm / 2e0c5c5
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314062 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 2 years ago
15 changed file(s) with 1234 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
27782778 // - The value has already been zero-extended
27792779 // - The value is a positive constant
27802780 // - The value comes from a load that isn't a sign-extending load
2781 // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have
2782 // to conservatively actually clear the high bits.
2783 if (Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND)
2781 // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext.
2782 bool IsTruncateOfZExt = Opc == ISD::TRUNCATE &&
2783 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
2784 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
2785 if (Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND || IsTruncateOfZExt)
27842786 return addExtOrTrunc(Input, ExtOrTruncConversion::Ext);
27852787
27862788 ConstantSDNode *InputConst = dyn_cast(Input);
30353037 return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode,
30363038 getI32Imm(1, dl)), 0);
30373039 }
3040 case ISD::SETUGT:
3041 // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
3042 // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
3043 std::swap(LHS, RHS);
3044 LLVM_FALLTHROUGH;
3045 case ISD::SETULT: {
3046 // The upper 32-bits of the register can't be undefined for this sequence.
3047 LHS = zeroExtendInputIfNeeded(LHS);
3048 RHS = zeroExtendInputIfNeeded(RHS);
3049 SDValue Subtract =
3050 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3051 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
3052 Subtract, getI64Imm(1, dl),
3053 getI64Imm(63, dl)), 0);
3054 }
30383055 }
30393056 }
30403057
31743191 getI32Imm(1, dl), getI32Imm(63,dl)), 0);
31753192 return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift,
31763193 getI32Imm(-1, dl)), 0);
3194 }
3195 case ISD::SETUGT:
3196 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
3197 // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
3198 std::swap(LHS, RHS);
3199 LLVM_FALLTHROUGH;
3200 case ISD::SETULT: {
3201 // The upper 32-bits of the register can't be undefined for this sequence.
3202 LHS = zeroExtendInputIfNeeded(LHS);
3203 RHS = zeroExtendInputIfNeeded(RHS);
3204 SDValue Subtract =
3205 SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0);
3206 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
3207 Subtract, getI64Imm(63, dl)), 0);
31773208 }
31783209 }
31793210 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 %struct.tree_common = type { i8, [3 x i8] }
8 declare signext i32 @fn2(...) local_unnamed_addr #1
9
10 ; Function Attrs: nounwind
11 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
12 ; CHECK-LABEL: testCompare1:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK: lbz r3, 0(r3)
15 ; CHECK-DAG: clrlwi r3, r3, 31
16 ; CHECK-DAG: clrldi r3, r3, 32
17 ; CHECK: lbz r4, 0(r4)
18 ; CHECK-DAG: clrlwi r4, r4, 31
19 ; CHECK-DAG: clrldi r4, r4, 32
20 ; CHECK: sub r3, r3, r4
21 ; CHECK-NEXT: rldicl r3, r3, 1, 63
22 entry:
23 %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
24 %bf.clear = and i8 %bf.load, 1
25 %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
26 %bf.load1 = load i8, i8* %0, align 4
27 %bf.clear2 = and i8 %bf.load1, 1
28 %cmp = icmp ugt i8 %bf.clear, %bf.clear2
29 %conv = zext i1 %cmp to i32
30 %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
31 ret i32 undef
32 }
33
34 ; Function Attrs: norecurse nounwind readnone
35 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
36 ; CHECK-LABEL: testCompare2:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
39 ; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
40 ; CHECK-DAG: clrldi r3, r3, 32
41 ; CHECK-DAG: clrldi r4, r4, 32
42 ; CHECK: sub r3, r4, r3
43 ; CHECK-NEXT: rldicl r3, r3, 1, 63
44 ; CHECK-NEXT: blr
45 entry:
46 %and = and i32 %a, 1
47 %and1 = and i32 %b, 1
48 %cmp = icmp ugt i32 %and, %and1
49 %conv = zext i1 %cmp to i32
50 ret i32 %conv
51 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 %struct.tree_common = type { i8, [3 x i8] }
8 declare signext i32 @fn2(...) local_unnamed_addr #1
9
10 ; Function Attrs: nounwind
11 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
12 ; CHECK-LABEL: testCompare1:
13 ; CHECK: # BB#0: # %entry
14 ; CHECK: lbz r3, 0(r3)
15 ; CHECK-DAG: clrlwi r3, r3, 31
16 ; CHECK-DAG: clrldi r3, r3, 32
17 ; CHECK: lbz r4, 0(r4)
18 ; CHECK-DAG: clrlwi r4, r4, 31
19 ; CHECK-DAG: clrldi r4, r4, 32
20 ; CHECK: sub r3, r4, r3
21 ; CHECK-NEXT: rldicl r3, r3, 1, 63
22 entry:
23 %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
24 %bf.clear = and i8 %bf.load, 1
25 %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
26 %bf.load1 = load i8, i8* %0, align 4
27 %bf.clear2 = and i8 %bf.load1, 1
28 %cmp = icmp ult i8 %bf.clear, %bf.clear2
29 %conv = zext i1 %cmp to i32
30 %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
31 ret i32 undef
32 }
33
34 ; Function Attrs: norecurse nounwind readnone
35 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
36 ; CHECK-LABEL: testCompare2:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
39 ; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
40 ; CHECK-DAG: clrldi r3, r3, 32
41 ; CHECK-DAG: clrldi r4, r4, 32
42 ; CHECK: sub r3, r3, r4
43 ; CHECK-NEXT: rldicl r3, r3, 1, 63
44 ; CHECK-NEXT: blr
45 entry:
46 %and = and i32 %a, 1
47 %and1 = and i32 %b, 1
48 %cmp = icmp ult i32 %and, %and1
49 %conv = zext i1 %cmp to i32
50 ret i32 %conv
51 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
11 ; CHECK-LABEL: test_igtuc:
12 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ugt i8 %a, %b
17 %conv2 = zext i1 %cmp to i32
18 ret i32 %conv2
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
23 ; CHECK-LABEL: test_igtuc_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ugt i8 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind readnone
34 define signext i32 @test_igtuc_z(i8 zeroext %a) {
35 ; CHECK-LABEL: test_igtuc_z:
36 ; CHECK: cntlzw r3, r3
37 ; CHECK-NEXT: srwi r3, r3, 5
38 ; CHECK-NEXT: xori r3, r3, 1
39 ; CHECK-NEXT: blr
40 entry:
41 %cmp = icmp ne i8 %a, 0
42 %conv1 = zext i1 %cmp to i32
43 ret i32 %conv1
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
48 ; CHECK-LABEL: test_igtuc_sext_z:
49 ; CHECK: cntlzw r3, r3
50 ; CHECK-NEXT: srwi r3, r3, 5
51 ; CHECK-NEXT: xori r3, r3, 1
52 ; CHECK-NEXT: neg r3, r3
53 ; CHECK-NEXT: blr
54 entry:
55 %cmp = icmp ne i8 %a, 0
56 %sub = sext i1 %cmp to i32
57 ret i32 %sub
58 }
59
60 ; Function Attrs: norecurse nounwind
61 define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
62 ; CHECK-LABEL: test_igtuc_store:
63 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
64 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
65 entry:
66 %cmp = icmp ugt i8 %a, %b
67 %conv3 = zext i1 %cmp to i8
68 store i8 %conv3, i8* @glob, align 1
69 ret void
70 }
71
72 ; Function Attrs: norecurse nounwind
73 define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
74 ; CHECK-LABEL: test_igtuc_sext_store:
75 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
76 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
77 entry:
78 %cmp = icmp ugt i8 %a, %b
79 %conv3 = sext i1 %cmp to i8
80 store i8 %conv3, i8* @glob, align 1
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_igtuc_z_store(i8 zeroext %a) {
86 ; CHECK-LABEL: test_igtuc_z_store:
87 ; CHECK: cntlzw r3, r3
88 ; CHECK: srwi r3, r3, 5
89 ; CHECK: xori r3, r3, 1
90 ; CHECK: stb r3, 0(r4)
91 ; CHECK-NEXT: blr
92 entry:
93 %cmp = icmp ne i8 %a, 0
94 %conv2 = zext i1 %cmp to i8
95 store i8 %conv2, i8* @glob, align 1
96 ret void
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_igtuc_sext_z_store(i8 zeroext %a) {
101 ; CHECK-LABEL: test_igtuc_sext_z_store:
102 ; CHECK: cntlzw r3, r3
103 ; CHECK: srwi r3, r3, 5
104 ; CHECK: xori r3, r3, 1
105 ; CHECK: neg r3, r3
106 ; CHECK: stb r3, 0(r4)
107 ; CHECK-NEXT: blr
108 entry:
109 %cmp = icmp ne i8 %a, 0
110 %conv2 = sext i1 %cmp to i8
111 store i8 %conv2, i8* @glob, align 1
112 ret void
113 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
11 ; CHECK-LABEL: test_igtui:
12 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ugt i32 %a, %b
17 %conv = zext i1 %cmp to i32
18 ret i32 %conv
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
23 ; CHECK-LABEL: test_igtui_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ugt i32 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind readnone
34 define signext i32 @test_igtui_z(i32 zeroext %a) {
35 ; CHECK-LABEL: test_igtui_z:
36 ; CHECK: cntlzw r3, r3
37 ; CHECK-NEXT: srwi r3, r3, 5
38 ; CHECK-NEXT: xori r3, r3, 1
39 ; CHECK-NEXT: blr
40 entry:
41 %cmp = icmp ne i32 %a, 0
42 %conv = zext i1 %cmp to i32
43 ret i32 %conv
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
48 ; CHECK-LABEL: test_igtui_sext_z:
49 ; CHECK: cntlzw r3, r3
50 ; CHECK-NEXT: srwi r3, r3, 5
51 ; CHECK-NEXT: xori r3, r3, 1
52 ; CHECK-NEXT: neg r3, r3
53 ; CHECK-NEXT: blr
54 entry:
55 %cmp = icmp ne i32 %a, 0
56 %sub = sext i1 %cmp to i32
57 ret i32 %sub
58 }
59
60 ; Function Attrs: norecurse nounwind
61 define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
62 ; CHECK-LABEL: test_igtui_store:
63 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
64 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
65 entry:
66 %cmp = icmp ugt i32 %a, %b
67 %conv = zext i1 %cmp to i32
68 store i32 %conv, i32* @glob, align 4
69 ret void
70 }
71
72 ; Function Attrs: norecurse nounwind
73 define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
74 ; CHECK-LABEL: test_igtui_sext_store:
75 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
76 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
77 entry:
78 %cmp = icmp ugt i32 %a, %b
79 %sub = sext i1 %cmp to i32
80 store i32 %sub, i32* @glob, align 4
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_igtui_z_store(i32 zeroext %a) {
86 ; CHECK-LABEL: test_igtui_z_store:
87 ; CHECK: cntlzw r3, r3
88 ; CHECK: srwi r3, r3, 5
89 ; CHECK: xori r3, r3, 1
90 ; CHECK: stw r3, 0(r4)
91 ; CHECK-NEXT: blr
92 entry:
93 %cmp = icmp ne i32 %a, 0
94 %conv = zext i1 %cmp to i32
95 store i32 %conv, i32* @glob, align 4
96 ret void
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_igtui_sext_z_store(i32 zeroext %a) {
101 ; CHECK-LABEL: test_igtui_sext_z_store:
102 ; CHECK: cntlzw r3, r3
103 ; CHECK: srwi r3, r3, 5
104 ; CHECK: xori r3, r3, 1
105 ; CHECK: neg r3, r3
106 ; CHECK: stw r3, 0(r4)
107 ; CHECK-NEXT: blr
108 entry:
109 %cmp = icmp ne i32 %a, 0
110 %sub = sext i1 %cmp to i32
111 store i32 %sub, i32* @glob, align 4
112 ret void
113 }
114
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
11 ; CHECK-LABEL: test_igtus:
12 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ugt i16 %a, %b
17 %conv2 = zext i1 %cmp to i32
18 ret i32 %conv2
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
23 ; CHECK-LABEL: test_igtus_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ugt i16 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind readnone
34 define signext i32 @test_igtus_z(i16 zeroext %a) {
35 ; CHECK-LABEL: test_igtus_z:
36 ; CHECK: cntlzw r3, r3
37 ; CHECK-NEXT: srwi r3, r3, 5
38 ; CHECK-NEXT: xori r3, r3, 1
39 ; CHECK-NEXT: blr
40 entry:
41 %cmp = icmp ne i16 %a, 0
42 %conv1 = zext i1 %cmp to i32
43 ret i32 %conv1
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
48 ; CHECK-LABEL: test_igtus_sext_z:
49 ; CHECK: cntlzw r3, r3
50 ; CHECK-NEXT: srwi r3, r3, 5
51 ; CHECK-NEXT: xori r3, r3, 1
52 ; CHECK-NEXT: neg r3, r3
53 ; CHECK-NEXT: blr
54 entry:
55 %cmp = icmp ne i16 %a, 0
56 %sub = sext i1 %cmp to i32
57 ret i32 %sub
58 }
59
60 ; Function Attrs: norecurse nounwind
61 define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
62 ; CHECK-LABEL: test_igtus_store:
63 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
64 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
65 ; CHECK: blr
66 entry:
67 %cmp = icmp ugt i16 %a, %b
68 %conv3 = zext i1 %cmp to i16
69 store i16 %conv3, i16* @glob, align 2
70 ret void
71 }
72
73 ; Function Attrs: norecurse nounwind
74 define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
75 ; CHECK-LABEL: test_igtus_sext_store:
76 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
77 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
78 ; CHECK: blr
79 entry:
80 %cmp = icmp ugt i16 %a, %b
81 %conv3 = sext i1 %cmp to i16
82 store i16 %conv3, i16* @glob, align 2
83 ret void
84 }
85
86 ; Function Attrs: norecurse nounwind
87 define void @test_igtus_z_store(i16 zeroext %a) {
88 ; CHECK-LABEL: test_igtus_z_store:
89 ; CHECK: cntlzw r3, r3
90 ; CHECK: srwi r3, r3, 5
91 ; CHECK: xori r3, r3, 1
92 ; CHECK: sth r3, 0(r4)
93 ; CHECK-NEXT: blr
94 entry:
95 %cmp = icmp ne i16 %a, 0
96 %conv2 = zext i1 %cmp to i16
97 store i16 %conv2, i16* @glob, align 2
98 ret void
99 }
100
101 ; Function Attrs: norecurse nounwind
102 define void @test_igtus_sext_z_store(i16 zeroext %a) {
103 ; CHECK-LABEL: test_igtus_sext_z_store:
104 ; CHECK: cntlzw r3, r3
105 ; CHECK: srwi r3, r3, 5
106 ; CHECK: xori r3, r3, 1
107 ; CHECK: neg r3, r3
108 ; CHECK: sth r3, 0(r4)
109 ; CHECK-NEXT: blr
110 entry:
111 %cmp = icmp ne i16 %a, 0
112 %conv2 = sext i1 %cmp to i16
113 store i16 %conv2, i16* @glob, align 2
114 ret void
115 }
116
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
11 ; CHECK-LABEL: test_iltuc:
12 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ult i8 %a, %b
17 %conv2 = zext i1 %cmp to i32
18 ret i32 %conv2
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
23 ; CHECK-LABEL: test_iltuc_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ult i8 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind
34 define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
35 ; CHECK-LABEL: test_iltuc_store:
36 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
37 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
38 entry:
39 %cmp = icmp ult i8 %a, %b
40 %conv3 = zext i1 %cmp to i8
41 store i8 %conv3, i8* @glob, align 1
42 ret void
43 }
44
45 ; Function Attrs: norecurse nounwind
46 define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
47 ; CHECK-LABEL: test_iltuc_sext_store:
48 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
49 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
50 entry:
51 %cmp = icmp ult i8 %a, %b
52 %conv3 = sext i1 %cmp to i8
53 store i8 %conv3, i8* @glob, align 1
54 ret void
55 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
11 ; CHECK-LABEL: test_iltui:
12 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ult i32 %a, %b
17 %conv = zext i1 %cmp to i32
18 ret i32 %conv
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
23 ; CHECK-LABEL: test_iltui_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ult i32 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind
34 define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
35 ; CHECK-LABEL: test_iltui_store:
36 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
37 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
38 entry:
39 %cmp = icmp ult i32 %a, %b
40 %conv = zext i1 %cmp to i32
41 store i32 %conv, i32* @glob, align 4
42 ret void
43 }
44
45 ; Function Attrs: norecurse nounwind
46 define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
47 ; CHECK-LABEL: test_iltui_sext_store:
48 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
49 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
50 entry:
51 %cmp = icmp ult i32 %a, %b
52 %sub = sext i1 %cmp to i32
53 store i32 %sub, i32* @glob, align 4
54 ret void
55 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 ; Function Attrs: norecurse nounwind readnone
10 define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
11 ; CHECK-LABEL: test_iltus:
12 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
13 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ult i16 %a, %b
17 %conv2 = zext i1 %cmp to i32
18 ret i32 %conv2
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
23 ; CHECK-LABEL: test_iltus_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ult i16 %a, %b
29 %sub = sext i1 %cmp to i32
30 ret i32 %sub
31 }
32
33 ; Function Attrs: norecurse nounwind
34 define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
35 ; CHECK-LABEL: test_iltus_store:
36 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
37 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
38 entry:
39 %cmp = icmp ult i16 %a, %b
40 %conv3 = zext i1 %cmp to i16
41 store i16 %conv3, i16* @glob, align 2
42 ret void
43 }
44
45 ; Function Attrs: norecurse nounwind
46 define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
47 ; CHECK-LABEL: test_iltus_sext_store:
48 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
49 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
50 entry:
51 %cmp = icmp ult i16 %a, %b
52 %conv3 = sext i1 %cmp to i16
53 store i16 %conv3, i16* @glob, align 2
54 ret void
55 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
11 ; CHECK-LABEL: test_llgtuc:
12 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
13 ; CHECK: rldicl r3, [[REG]], 1, 63
14 ; CHECK-NEXT: blr
15 entry:
16 %cmp = icmp ugt i8 %a, %b
17 %conv3 = zext i1 %cmp to i64
18 ret i64 %conv3
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
23 ; CHECK-LABEL: test_llgtuc_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
25 ; CHECK: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ugt i8 %a, %b
29 %conv3 = sext i1 %cmp to i64
30 ret i64 %conv3
31 }
32
33 ; Function Attrs: norecurse nounwind readnone
34 define i64 @test_llgtuc_z(i8 zeroext %a) {
35 ; CHECK-LABEL: test_llgtuc_z:
36 ; CHECK: cntlzw r3, r3
37 ; CHECK: srwi r3, r3, 5
38 ; CHECK: xori r3, r3, 1
39 ; CHECK-NEXT: blr
40 entry:
41 %cmp = icmp ne i8 %a, 0
42 %conv2 = zext i1 %cmp to i64
43 ret i64 %conv2
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
48 ; CHECK-LABEL: test_llgtuc_sext_z:
49 ; CHECK: cntlzw r3, r3
50 ; CHECK: srwi r3, r3, 5
51 ; CHECK: xori r3, r3, 1
52 ; CHECK: neg r3, r3
53 ; CHECK-NEXT: blr
54 entry:
55 %cmp = icmp ne i8 %a, 0
56 %conv2 = sext i1 %cmp to i64
57 ret i64 %conv2
58 }
59
60 ; Function Attrs: norecurse nounwind
61 define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
62 ; CHECK-LABEL: test_llgtuc_store:
63 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
64 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
65 entry:
66 %cmp = icmp ugt i8 %a, %b
67 %conv3 = zext i1 %cmp to i8
68 store i8 %conv3, i8* @glob, align 1
69 ret void
70 }
71
72 ; Function Attrs: norecurse nounwind
73 define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
74 ; CHECK-LABEL: test_llgtuc_sext_store:
75 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
76 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
77 entry:
78 %cmp = icmp ugt i8 %a, %b
79 %conv3 = sext i1 %cmp to i8
80 store i8 %conv3, i8* @glob, align 1
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llgtuc_z_store(i8 zeroext %a) {
86 ; CHECK-LABEL: test_llgtuc_z_store:
87 ; CHECK: cntlzw r3, r3
88 ; CHECK: srwi r3, r3, 5
89 ; CHECK: xori r3, r3, 1
90 ; CHECK: stb r3, 0(r4)
91 ; CHECK-NEXT: blr
92 entry:
93 %cmp = icmp ne i8 %a, 0
94 %conv2 = zext i1 %cmp to i8
95 store i8 %conv2, i8* @glob, align 1
96 ret void
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
101 ; CHECK-LABEL: test_llgtuc_sext_z_store:
102 ; CHECK: cntlzw r3, r3
103 ; CHECK: srwi r3, r3, 5
104 ; CHECK: xori r3, r3, 1
105 ; CHECK: neg r3, r3
106 ; CHECK: stb r3, 0(r4)
107 ; CHECK-NEXT: blr
108 entry:
109 %cmp = icmp ne i8 %a, 0
110 %conv2 = sext i1 %cmp to i8
111 store i8 %conv2, i8* @glob, align 1
112 ret void
113 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
11 ; CHECK-LABEL: test_llgtui:
12 ; CHECK-NOT: clrldi
13 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
14 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
15 entry:
16 %cmp = icmp ugt i32 %a, %b
17 %conv1 = zext i1 %cmp to i64
18 ret i64 %conv1
19 }
20
21 ; Function Attrs: norecurse nounwind readnone
22 define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
23 ; CHECK-LABEL: test_llgtui_sext:
24 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
25 ; CHECK-NEXT: sradi r3, [[REG]], 63
26 ; CHECK-NEXT: blr
27 entry:
28 %cmp = icmp ugt i32 %a, %b
29 %conv1 = sext i1 %cmp to i64
30 ret i64 %conv1
31 }
32
33 ; Function Attrs: norecurse nounwind readnone
34 define i64 @test_llgtui_z(i32 zeroext %a) {
35 ; CHECK-LABEL: test_llgtui_z:
36 ; CHECK: cntlzw r3, r3
37 ; CHECK-NEXT: srwi r3, r3, 5
38 ; CHECK-NEXT: xori r3, r3, 1
39 ; CHECK-NEXT: blr
40 entry:
41 %cmp = icmp ne i32 %a, 0
42 %conv1 = zext i1 %cmp to i64
43 ret i64 %conv1
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define i64 @test_llgtui_sext_z(i32 zeroext %a) {
48 ; CHECK-LABEL: test_llgtui_sext_z:
49 ; CHECK: cntlzw r3, r3
50 ; CHECK-NEXT: srwi r3, r3, 5
51 ; CHECK-NEXT: xori r3, r3, 1
52 ; CHECK-NEXT: neg r3, r3
53 ; CHECK-NEXT: blr
54 entry:
55 %cmp = icmp ne i32 %a, 0
56 %conv1 = sext i1 %cmp to i64
57 ret i64 %conv1
58 }
59
60 ; Function Attrs: norecurse nounwind
61 define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
62 ; CHECK-LABEL: test_llgtui_store:
63 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
64 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
65 entry:
66 %cmp = icmp ugt i32 %a, %b
67 %conv = zext i1 %cmp to i32
68 store i32 %conv, i32* @glob, align 4
69 ret void
70 }
71
72 ; Function Attrs: norecurse nounwind
73 define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
74 ; CHECK-LABEL: test_llgtui_sext_store:
75 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
76 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
77 entry:
78 %cmp = icmp ugt i32 %a, %b
79 %sub = sext i1 %cmp to i32
80 store i32 %sub, i32* @glob, align 4
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llgtui_z_store(i32 zeroext %a) {
86 ; CHECK-LABEL: test_llgtui_z_store:
87 ; CHECK: cntlzw r3, r3
88 ; CHECK: srwi r3, r3, 5
89 ; CHECK: xori r3, r3, 1
90 ; CHECK: stw r3, 0(r4)
91 ; CHECK-NEXT: blr
92 entry:
93 %cmp = icmp ne i32 %a, 0
94 %conv = zext i1 %cmp to i32
95 store i32 %conv, i32* @glob, align 4
96 ret void
97 }
98
99 ; Function Attrs: norecurse nounwind
100 define void @test_llgtui_sext_z_store(i32 zeroext %a) {
101 ; CHECK-LABEL: test_llgtui_sext_z_store:
102 ; CHECK: cntlzw r3, r3
103 ; CHECK: srwi r3, r3, 5
104 ; CHECK: xori r3, r3, 1
105 ; CHECK: neg r3, r3
106 ; CHECK: stw r3, 0(r4)
107 ; CHECK-NEXT: blr
108 entry:
109 %cmp = icmp ne i32 %a, 0
110 %sub = sext i1 %cmp to i32
111 store i32 %sub, i32* @glob, align 4
112 ret void
113 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
11 ; CHECK-LABEL: test_llgtus:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
14 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp ugt i16 %a, %b
18 %conv3 = zext i1 %cmp to i64
19 ret i64 %conv3
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
24 ; CHECK-LABEL: test_llgtus_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
27 ; CHECK-NEXT: sradi r3, [[REG]], 63
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp ugt i16 %a, %b
31 %conv3 = sext i1 %cmp to i64
32 ret i64 %conv3
33 }
34
35 ; Function Attrs: norecurse nounwind readnone
36 define i64 @test_llgtus_z(i16 zeroext %a) {
37 ; CHECK-LABEL: test_llgtus_z:
38 ; CHECK: # BB#0: # %entry
39 ; CHECK-NEXT: cntlzw r3, r3
40 ; CHECK-NEXT: srwi r3, r3, 5
41 ; CHECK-NEXT: xori r3, r3, 1
42 ; CHECK-NEXT: blr
43 entry:
44 %cmp = icmp ne i16 %a, 0
45 %conv2 = zext i1 %cmp to i64
46 ret i64 %conv2
47 }
48
49 ; Function Attrs: norecurse nounwind readnone
50 define i64 @test_llgtus_sext_z(i16 zeroext %a) {
51 ; CHECK-LABEL: test_llgtus_sext_z:
52 ; CHECK: # BB#0: # %entry
53 ; CHECK-NEXT: cntlzw r3, r3
54 ; CHECK-NEXT: srwi r3, r3, 5
55 ; CHECK-NEXT: xori r3, r3, 1
56 ; CHECK-NEXT: neg r3, r3
57 ; CHECK-NEXT: blr
58 entry:
59 %cmp = icmp ne i16 %a, 0
60 %conv2 = sext i1 %cmp to i64
61 ret i64 %conv2
62 }
63
64 ; Function Attrs: norecurse nounwind
65 define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
66 ; CHECK-LABEL: test_llgtus_store:
67 ; CHECK: # BB#0: # %entry
68 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
69 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
70 entry:
71 %cmp = icmp ugt i16 %a, %b
72 %conv3 = zext i1 %cmp to i16
73 store i16 %conv3, i16* @glob, align 2
74 ret void
75 }
76
77 ; Function Attrs: norecurse nounwind
78 define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
79 ; CHECK-LABEL: test_llgtus_sext_store:
80 ; CHECK: # BB#0: # %entry
81 ; CHECK: sub [[REG:r[0-9]+]], r4, r3
82 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
83 entry:
84 %cmp = icmp ugt i16 %a, %b
85 %conv3 = sext i1 %cmp to i16
86 store i16 %conv3, i16* @glob, align 2
87 ret void
88 }
89
90 ; Function Attrs: norecurse nounwind
91 define void @test_llgtus_z_store(i16 zeroext %a) {
92 ; CHECK-LABEL: test_llgtus_z_store:
93 ; CHECK: # BB#0: # %entry
94 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
95 ; CHECK-NEXT: cntlzw r3, r3
96 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
97 ; CHECK-NEXT: srwi r3, r3, 5
98 ; CHECK-NEXT: xori r3, r3, 1
99 ; CHECK-NEXT: sth r3, 0(r4)
100 ; CHECK-NEXT: blr
101 entry:
102 %cmp = icmp ne i16 %a, 0
103 %conv2 = zext i1 %cmp to i16
104 store i16 %conv2, i16* @glob, align 2
105 ret void
106 }
107
108 ; Function Attrs: norecurse nounwind
109 define void @test_llgtus_sext_z_store(i16 zeroext %a) {
110 ; CHECK-LABEL: test_llgtus_sext_z_store:
111 ; CHECK: # BB#0: # %entry
112 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
113 ; CHECK-NEXT: cntlzw r3, r3
114 ; CHECK-NEXT: srwi r3, r3, 5
115 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
116 ; CHECK-NEXT: xori r3, r3, 1
117 ; CHECK-NEXT: neg r3, r3
118 ; CHECK-NEXT: sth r3, 0(r4)
119 ; CHECK-NEXT: blr
120 entry:
121 %cmp = icmp ne i16 %a, 0
122 %conv2 = sext i1 %cmp to i16
123 store i16 %conv2, i16* @glob, align 2
124 ret void
125 }
126
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
11 ; CHECK-LABEL: test_llltuc:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
14 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp ult i8 %a, %b
18 %conv3 = zext i1 %cmp to i64
19 ret i64 %conv3
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
24 ; CHECK-LABEL: test_llltuc_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
27 ; CHECK-NEXT: sradi r3, [[REG]], 63
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp ult i8 %a, %b
31 %conv3 = sext i1 %cmp to i64
32 ret i64 %conv3
33 }
34
35 ; Function Attrs: norecurse nounwind
36 define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
37 ; CHECK-LABEL: test_llltuc_store:
38 ; CHECK: # BB#0: # %entry
39 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
40 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
41 entry:
42 %cmp = icmp ult i8 %a, %b
43 %conv3 = zext i1 %cmp to i8
44 store i8 %conv3, i8* @glob, align 1
45 ret void
46 }
47
48 ; Function Attrs: norecurse nounwind
49 define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
50 ; CHECK-LABEL: test_llltuc_sext_store:
51 ; CHECK: # BB#0: # %entry
52 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
53 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
54 entry:
55 %cmp = icmp ult i8 %a, %b
56 %conv3 = sext i1 %cmp to i8
57 store i8 %conv3, i8* @glob, align 1
58 ret void
59 }
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
11 ; CHECK-LABEL: test_llltui:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NOT: clrldi
14 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
15 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
16 ; CHECK-NEXT: blr
17 entry:
18 %cmp = icmp ult i32 %a, %b
19 %conv1 = zext i1 %cmp to i64
20 ret i64 %conv1
21 }
22
23 ; Function Attrs: norecurse nounwind readnone
24 define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
25 ; CHECK-LABEL: test_llltui_sext:
26 ; CHECK: # BB#0: # %entry
27 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
28 ; CHECK-NEXT: sradi r3, [[REG]], 63
29 ; CHECK-NEXT: blr
30 entry:
31 %cmp = icmp ult i32 %a, %b
32 %conv1 = sext i1 %cmp to i64
33 ret i64 %conv1
34 }
35
36 ; Function Attrs: norecurse nounwind readnone
37 define i64 @test_llltui_z(i32 zeroext %a) {
38 ; CHECK-LABEL: test_llltui_z:
39 ; CHECK: # BB#0: # %entry
40 ; CHECK-NEXT: li r3, 0
41 ; CHECK-NEXT: blr
42 entry:
43 ret i64 0
44 }
45
46 ; Function Attrs: norecurse nounwind readnone
47 define i64 @test_llltui_sext_z(i32 zeroext %a) {
48 ; CHECK-LABEL: test_llltui_sext_z:
49 ; CHECK: # BB#0: # %entry
50 ; CHECK-NEXT: li r3, 0
51 ; CHECK-NEXT: blr
52 entry:
53 ret i64 0
54 }
55
56 ; Function Attrs: norecurse nounwind
57 define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
58 ; CHECK-LABEL: test_llltui_store:
59 ; CHECK: # BB#0: # %entry
60 ; CHECK-NOT: clrldi
61 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
62 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
63 entry:
64 %cmp = icmp ult i32 %a, %b
65 %conv = zext i1 %cmp to i32
66 store i32 %conv, i32* @glob, align 4
67 ret void
68 }
69
70 ; Function Attrs: norecurse nounwind
71 define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
72 ; CHECK-LABEL: test_llltui_sext_store:
73 ; CHECK: # BB#0: # %entry
74 ; CHECK-NOT: clrldi
75 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
76 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
77 entry:
78 %cmp = icmp ult i32 %a, %b
79 %sub = sext i1 %cmp to i32
80 store i32 %sub, i32* @glob, align 4
81 ret void
82 }
83
84 ; Function Attrs: norecurse nounwind
85 define void @test_llltui_z_store(i32 zeroext %a) {
86 ; CHECK-LABEL: test_llltui_z_store:
87 ; CHECK: # BB#0: # %entry
88 ; CHECK: li [[REG:r[0-9]+]], 0
89 ; CHECK: stw [[REG]], 0(r3)
90 ; CHECK-NEXT: blr
91 entry:
92 store i32 0, i32* @glob, align 4
93 ret void
94 }
95
96 ; Function Attrs: norecurse nounwind
97 define void @test_llltui_sext_z_store(i32 zeroext %a) {
98 ; CHECK-LABEL: test_llltui_sext_z_store:
99 ; CHECK: # BB#0: # %entry
100 ; CHECK: li [[REG:r[0-9]+]], 0
101 ; CHECK: stw [[REG]], 0(r3)
102 ; CHECK-NEXT: blr
103 entry:
104 store i32 0, i32* @glob, align 4
105 ret void
106 }
107
0 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 ; Function Attrs: norecurse nounwind readnone
10 define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
11 ; CHECK-LABEL: test_llltus:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
14 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp ult i16 %a, %b
18 %conv3 = zext i1 %cmp to i64
19 ret i64 %conv3
20 }
21
22 ; Function Attrs: norecurse nounwind readnone
23 define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
24 ; CHECK-LABEL: test_llltus_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
27 ; CHECK-NEXT: sradi r3, [[REG]], 63
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp ult i16 %a, %b
31 %conv3 = sext i1 %cmp to i64
32 ret i64 %conv3
33 }
34
35 ; Function Attrs: norecurse nounwind
36 define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
37 ; CHECK-LABEL: test_llltus_store:
38 ; CHECK: sub [[REG:r[2-9]+]], r3, r4
39 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
40 entry:
41 %cmp = icmp ult i16 %a, %b
42 %conv3 = zext i1 %cmp to i16
43 store i16 %conv3, i16* @glob, align 2
44 ret void
45 }
46
47 ; Function Attrs: norecurse nounwind
48 define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
49 ; CHECK-LABEL: test_llltus_sext_store:
50 ; CHECK: # BB#0: # %entry
51 ; CHECK: sub [[REG:r[0-9]+]], r3, r4
52 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
53 entry:
54 %cmp = icmp ult i16 %a, %b
55 %conv3 = sext i1 %cmp to i16
56 store i16 %conv3, i16* @glob, align 2
57 ret void
58 }