llvm.org GIT mirror llvm / 2de896a
[PowerPC] Revert r310346 (and followups r310356 & r310424) which introduce a miscompile bug. There appears to be a bug where the generated code to extract the sign bit doesn't work correctly for 32-bit inputs. I've replied to the original commit pointing out the problem. I think I see by inspection (and reading the manual for PPC) how to fix this, but I can't be 100% confident and I also don't know what the best way to test this is. Currently it seems nearly impossible to get the backend to hit this code path, but the patch autohr is likely in a better position to craft such test cases than I am, and based on where the bug is it should be easily done. Original commit message for r310346: """ [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it adds the handling for the special case where RHS == 0. Differential Revision: https://reviews.llvm.org/D34048 """ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310809 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 2 years ago
13 changed file(s) with 0 addition(s) and 951 deletion(s). Raw diff Collapse all Expand all
281281 // SExtInvert - invert the condition code, sign-extend value
282282 enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
283283
284 // Comparisons against zero to emit GPR code sequences for. Each of these
285 // sequences may need to be emitted for two or more equivalent patterns.
286 // For example (a >= 0) == (a > -1).
287 enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
288
289284 bool trySETCC(SDNode *N);
290285 bool tryEXTEND(SDNode *N);
291286 bool tryLogicOpOfCompares(SDNode *N);
293288 SDValue signExtendInputIfNeeded(SDValue Input);
294289 SDValue zeroExtendInputIfNeeded(SDValue Input);
295290 SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
296 SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
297 ZeroCompare CmpTy);
298291 SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
299292 int64_t RHSValue, SDLoc dl);
300293 SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
28032796 NatWidthRes, SubRegIdx), 0);
28042797 }
28052798
2806 // Produce a GPR sequence for compound comparisons (<=, >=) against zero.
2807 // Handle both zero-extensions and sign-extensions.
2808 SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
2809 ZeroCompare CmpTy) {
2810 EVT InVT = LHS.getValueType();
2811 bool Is32Bit = InVT == MVT::i32;
2812 SDValue ToExtend;
2813
2814 // Produce the value that needs to be either zero or sign extended.
2815 switch (CmpTy) {
2816 case ZeroCompare::GEZExt:
2817 case ZeroCompare::GESExt:
2818 ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
2819 dl, InVT, LHS, LHS), 0);
2820 break;
2821 case ZeroCompare::LEZExt:
2822 case ZeroCompare::LESExt: {
2823 if (Is32Bit) {
2824 SDValue Neg =
2825 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
2826 ToExtend =
2827 SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
2828 Neg, getI64Imm(1, dl),
2829 getI64Imm(63, dl)), 0);
2830 } else {
2831 SDValue Addi =
2832 SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
2833 getI64Imm(~0ULL, dl)), 0);
2834 ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
2835 Addi, LHS), 0);
2836 }
2837 break;
2838 }
2839 }
2840
2841 // For 64-bit sequences, the extensions are the same for the GE/LE cases.
2842 if (!Is32Bit &&
2843 (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
2844 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
2845 ToExtend, getI64Imm(1, dl),
2846 getI64Imm(63, dl)), 0);
2847 if (!Is32Bit &&
2848 (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
2849 return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
2850 getI64Imm(63, dl)), 0);
2851
2852 assert(Is32Bit && "Should have handled the 32-bit sequences above.");
2853 // For 32-bit sequences, the extensions differ between GE/LE cases.
2854 switch (CmpTy) {
2855 case ZeroCompare::GEZExt: {
2856 SDValue ShiftOps[] =
2857 { ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
2858 return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
2859 ShiftOps), 0);
2860 }
2861 case ZeroCompare::GESExt:
2862 return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
2863 getI32Imm(31, dl)), 0);
2864 case ZeroCompare::LEZExt:
2865 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, ToExtend,
2866 getI32Imm(1, dl)), 0);
2867 case ZeroCompare::LESExt:
2868 return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, ToExtend,
2869 getI32Imm(-1, dl)), 0);
2870 }
2871
2872 // The above case covers all the enumerators so it can't have a default clause
2873 // to avoid compiler warnings.
2874 llvm_unreachable("Unknown zero-comparison type.");
2875 }
2876
28772799 /// Produces a zero-extended result of comparing two 32-bit values according to
28782800 /// the passed condition code.
28792801 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
29072829 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
29082830 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
29092831 getI32Imm(1, dl)), 0);
2910 }
2911 case ISD::SETGE: {
2912 // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
2913 // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
2914 if(IsRHSZero)
2915 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
2916
2917 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2918 // by swapping inputs and falling through.
2919 std::swap(LHS, RHS);
2920 ConstantSDNode *RHSConst = dyn_cast(RHS);
2921 IsRHSZero = RHSConst && RHSConst->isNullValue();
2922 LLVM_FALLTHROUGH;
2923 }
2924 case ISD::SETLE: {
2925 // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
2926 // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
2927 if(IsRHSZero)
2928 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
2929 SDValue Sub =
2930 SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
2931 SDValue Shift =
2932 SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
2933 getI64Imm(1, dl), getI64Imm(63, dl)), 0);
2934 return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
2935 MVT::i32, Shift, getI32Imm(1, dl)), 0);
29362832 }
29372833 }
29382834 }
29802876 SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
29812877 getI32Imm(1, dl)), 0);
29822878 return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
2983 }
2984 case ISD::SETGE: {
2985 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
2986 // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
2987 if (IsRHSZero)
2988 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
2989
2990 // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
2991 // by swapping inputs and falling through.
2992 std::swap(LHS, RHS);
2993 ConstantSDNode *RHSConst = dyn_cast(RHS);
2994 IsRHSZero = RHSConst && RHSConst->isNullValue();
2995 LLVM_FALLTHROUGH;
2996 }
2997 case ISD::SETLE: {
2998 // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
2999 // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
3000 if (IsRHSZero)
3001 return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
3002 SDValue SUBFNode =
3003 SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
3004 LHS, RHS), 0);
3005 SDValue Srdi =
3006 SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
3007 SUBFNode, getI64Imm(1, dl),
3008 getI64Imm(63, dl)), 0);
3009 return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
3010 getI32Imm(-1, dl)), 0);
30112879 }
30122880 }
30132881 }
+0
-68
test/CodeGen/PowerPC/testComparesigesc.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
10 ; CHECK-LABEL: test_igesc:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i8 %a, %b
18 %conv2 = zext i1 %cmp to i32
19 ret i32 %conv2
20 }
21
22 define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
23 ; CHECK-LABEL: test_igesc_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i8 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_igesc_store(i8 signext %a, i8 signext %b) {
36 ; CHECK-LABEL: test_igesc_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i8 %a, %b
47 %conv3 = zext i1 %cmp to i8
48 store i8 %conv3, i8* @glob, align 1
49 ret void
50 }
51
52 define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
53 ; CHECK-LABEL: test_igesc_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i8 %a, %b
64 %conv3 = sext i1 %cmp to i8
65 store i8 %conv3, i8* @glob, align 1
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesigesi.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
10 ; CHECK-LABEL: test_igesi:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i32 %a, %b
18 %conv = zext i1 %cmp to i32
19 ret i32 %conv
20 }
21
22 define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
23 ; CHECK-LABEL: test_igesi_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i32 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_igesi_store(i32 signext %a, i32 signext %b) {
36 ; CHECK-LABEL: test_igesi_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i32 %a, %b
47 %conv = zext i1 %cmp to i32
48 store i32 %conv, i32* @glob, align 4
49 ret void
50 }
51
52 define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
53 ; CHECK-LABEL: test_igesi_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i32 %a, %b
64 %sub = sext i1 %cmp to i32
65 store i32 %sub, i32* @glob, align 4
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesigess.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
10 ; CHECK-LABEL: test_igess:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i16 %a, %b
18 %conv2 = zext i1 %cmp to i32
19 ret i32 %conv2
20 }
21
22 define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
23 ; CHECK-LABEL: test_igess_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i16 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_igess_store(i16 signext %a, i16 signext %b) {
36 ; CHECK-LABEL: test_igess_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i16 %a, %b
47 %conv3 = zext i1 %cmp to i16
48 store i16 %conv3, i16* @glob, align 2
49 ret void
50 }
51
52 define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
53 ; CHECK-LABEL: test_igess_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i16 %a, %b
64 %conv3 = sext i1 %cmp to i16
65 store i16 %conv3, i16* @glob, align 2
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesilesc.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
10 ; CHECK-LABEL: test_ilesc:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r3, r4
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sle i8 %a, %b
18 %conv2 = zext i1 %cmp to i32
19 ret i32 %conv2
20 }
21
22 define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
23 ; CHECK-LABEL: test_ilesc_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r3, r4
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sle i8 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
36 ; CHECK-LABEL: test_ilesc_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sle i8 %a, %b
47 %conv3 = zext i1 %cmp to i8
48 store i8 %conv3, i8* @glob, align 1
49 ret void
50 }
51
52 define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
53 ; CHECK-LABEL: test_ilesc_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sle i8 %a, %b
64 %conv3 = sext i1 %cmp to i8
65 store i8 %conv3, i8* @glob, align 1
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesilesi.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
10 ; CHECK-LABEL: test_ilesi:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r3, r4
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sle i32 %a, %b
18 %conv = zext i1 %cmp to i32
19 ret i32 %conv
20 }
21
22 define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
23 ; CHECK-LABEL: test_ilesi_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r3, r4
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sle i32 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
36 ; CHECK-LABEL: test_ilesi_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sle i32 %a, %b
47 %conv = zext i1 %cmp to i32
48 store i32 %conv, i32* @glob, align 4
49 ret void
50 }
51
52 define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
53 ; CHECK-LABEL: test_ilesi_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sle i32 %a, %b
64 %sub = sext i1 %cmp to i32
65 store i32 %sub, i32* @glob, align 4
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesiless.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
10 ; CHECK-LABEL: test_iless:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r3, r4
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sle i16 %a, %b
18 %conv2 = zext i1 %cmp to i32
19 ret i32 %conv2
20 }
21
22 define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
23 ; CHECK-LABEL: test_iless_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r3, r4
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sle i16 %a, %b
31 %sub = sext i1 %cmp to i32
32 ret i32 %sub
33 }
34
35 define void @test_iless_store(i16 signext %a, i16 signext %b) {
36 ; CHECK-LABEL: test_iless_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sle i16 %a, %b
47 %conv3 = zext i1 %cmp to i16
48 store i16 %conv3, i16* @glob, align 2
49 ret void
50 }
51
52 define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
53 ; CHECK-LABEL: test_iless_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sle i16 %a, %b
64 %conv3 = sext i1 %cmp to i16
65 store i16 %conv3, i16* @glob, align 2
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesllgesc.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i8 0, align 1
8
9 define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
10 ; CHECK-LABEL: test_llgesc:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i8 %a, %b
18 %conv3 = zext i1 %cmp to i64
19 ret i64 %conv3
20 }
21
22 define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
23 ; CHECK-LABEL: test_llgesc_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i8 %a, %b
31 %conv3 = sext i1 %cmp to i64
32 ret i64 %conv3
33 }
34
35 define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
36 ; CHECK-LABEL: test_llgesc_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i8 %a, %b
47 %conv3 = zext i1 %cmp to i8
48 store i8 %conv3, i8* @glob, align 1
49 ret void
50 }
51
52 define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
53 ; CHECK-LABEL: test_llgesc_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i8 %a, %b
64 %conv3 = sext i1 %cmp to i8
65 store i8 %conv3, i8* @glob, align 1
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesllgesi.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i32 0, align 4
8
9 define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
10 ; CHECK-LABEL: test_llgesi:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i32 %a, %b
18 %conv1 = zext i1 %cmp to i64
19 ret i64 %conv1
20 }
21
22 define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
23 ; CHECK-LABEL: test_llgesi_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i32 %a, %b
31 %conv1 = sext i1 %cmp to i64
32 ret i64 %conv1
33 }
34
35 define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
36 ; CHECK-LABEL: test_llgesi_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i32 %a, %b
47 %conv = zext i1 %cmp to i32
48 store i32 %conv, i32* @glob, align 4
49 ret void
50 }
51
52 define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
53 ; CHECK-LABEL: test_llgesi_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i32 %a, %b
64 %sub = sext i1 %cmp to i32
65 store i32 %sub, i32* @glob, align 4
66 ret void
67 }
+0
-68
test/CodeGen/PowerPC/testComparesllgess.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7 @glob = common local_unnamed_addr global i16 0, align 2
8
9 define i64 @test_llgess(i16 signext %a, i16 signext %b) {
10 ; CHECK-LABEL: test_llgess:
11 ; CHECK: # BB#0: # %entry
12 ; CHECK-NEXT: subf r3, r4, r3
13 ; CHECK-NEXT: rldicl r3, r3, 1, 63
14 ; CHECK-NEXT: xori r3, r3, 1
15 ; CHECK-NEXT: blr
16 entry:
17 %cmp = icmp sge i16 %a, %b
18 %conv3 = zext i1 %cmp to i64
19 ret i64 %conv3
20 }
21
22 define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
23 ; CHECK-LABEL: test_llgess_sext:
24 ; CHECK: # BB#0: # %entry
25 ; CHECK-NEXT: subf r3, r4, r3
26 ; CHECK-NEXT: rldicl r3, r3, 1, 63
27 ; CHECK-NEXT: addi r3, r3, -1
28 ; CHECK-NEXT: blr
29 entry:
30 %cmp = icmp sge i16 %a, %b
31 %conv3 = sext i1 %cmp to i64
32 ret i64 %conv3
33 }
34
35 define void @test_llgess_store(i16 signext %a, i16 signext %b) {
36 ; CHECK-LABEL: test_llgess_store:
37 ; CHECK: # BB#0: # %entry
38 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
39 ; CHECK-NEXT: subf r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: rldicl r3, r3, 1, 63
42 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
44 ; CHECK-NEXT: blr
45 entry:
46 %cmp = icmp sge i16 %a, %b
47 %conv3 = zext i1 %cmp to i16
48 store i16 %conv3, i16* @glob, align 2
49 ret void
50 }
51
52 define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
53 ; CHECK-LABEL: test_llgess_sext_store:
54 ; CHECK: # BB#0: # %entry
55 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
56 ; CHECK-NEXT: subf r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: rldicl r3, r3, 1, 63
59 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
61 ; CHECK-NEXT: blr
62 entry:
63 %cmp = icmp sge i16 %a, %b
64 %conv3 = sext i1 %cmp to i16
65 store i16 %conv3, i16* @glob, align 2
66 ret void
67 }
+0
-69
test/CodeGen/PowerPC/testCompareslllesc.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7
8 @glob = common local_unnamed_addr global i8 0, align 1
9
10 define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
11 ; CHECK-LABEL: test_lllesc:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: subf r3, r3, r4
14 ; CHECK-NEXT: rldicl r3, r3, 1, 63
15 ; CHECK-NEXT: xori r3, r3, 1
16 ; CHECK-NEXT: blr
17 entry:
18 %cmp = icmp sle i8 %a, %b
19 %conv3 = zext i1 %cmp to i64
20 ret i64 %conv3
21 }
22
23 define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
24 ; CHECK-LABEL: test_lllesc_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: subf r3, r3, r4
27 ; CHECK-NEXT: rldicl r3, r3, 1, 63
28 ; CHECK-NEXT: addi r3, r3, -1
29 ; CHECK-NEXT: blr
30 entry:
31 %cmp = icmp sle i8 %a, %b
32 %conv3 = sext i1 %cmp to i64
33 ret i64 %conv3
34 }
35
36 define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
37 ; CHECK-LABEL: test_lllesc_store:
38 ; CHECK: # BB#0: # %entry
39 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
40 ; CHECK-NEXT: subf r3, r3, r4
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
42 ; CHECK-NEXT: rldicl r3, r3, 1, 63
43 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: stb r3, 0(r12)
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp sle i8 %a, %b
48 %conv3 = zext i1 %cmp to i8
49 store i8 %conv3, i8* @glob, align 1
50 ret void
51 }
52
53 define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
54 ; CHECK-LABEL: test_lllesc_sext_store:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
57 ; CHECK-NEXT: subf r3, r3, r4
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
59 ; CHECK-NEXT: rldicl r3, r3, 1, 63
60 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: stb r3, 0(r12)
62 ; CHECK-NEXT: blr
63 entry:
64 %cmp = icmp sle i8 %a, %b
65 %conv3 = sext i1 %cmp to i8
66 store i8 %conv3, i8* @glob, align 1
67 ret void
68 }
+0
-69
test/CodeGen/PowerPC/testCompareslllesi.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7
8 @glob = common local_unnamed_addr global i32 0, align 4
9
10 define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
11 ; CHECK-LABEL: test_lllesi:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: subf r3, r3, r4
14 ; CHECK-NEXT: rldicl r3, r3, 1, 63
15 ; CHECK-NEXT: xori r3, r3, 1
16 ; CHECK-NEXT: blr
17 entry:
18 %cmp = icmp sle i32 %a, %b
19 %conv1 = zext i1 %cmp to i64
20 ret i64 %conv1
21 }
22
23 define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
24 ; CHECK-LABEL: test_lllesi_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: subf r3, r3, r4
27 ; CHECK-NEXT: rldicl r3, r3, 1, 63
28 ; CHECK-NEXT: addi r3, r3, -1
29 ; CHECK-NEXT: blr
30 entry:
31 %cmp = icmp sle i32 %a, %b
32 %conv1 = sext i1 %cmp to i64
33 ret i64 %conv1
34 }
35
36 define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
37 ; CHECK-LABEL: test_lllesi_store:
38 ; CHECK: # BB#0: # %entry
39 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
40 ; CHECK-NEXT: subf r3, r3, r4
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
42 ; CHECK-NEXT: rldicl r3, r3, 1, 63
43 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: stw r3, 0(r12)
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp sle i32 %a, %b
48 %conv = zext i1 %cmp to i32
49 store i32 %conv, i32* @glob, align 4
50 ret void
51 }
52
53 define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
54 ; CHECK-LABEL: test_lllesi_sext_store:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
57 ; CHECK-NEXT: subf r3, r3, r4
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
59 ; CHECK-NEXT: rldicl r3, r3, 1, 63
60 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: stw r3, 0(r12)
62 ; CHECK-NEXT: blr
63 entry:
64 %cmp = icmp sle i32 %a, %b
65 %sub = sext i1 %cmp to i32
66 store i32 %sub, i32* @glob, align 4
67 ret void
68 }
+0
-69
test/CodeGen/PowerPC/testComparesllless.ll less more
None ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
1 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
2 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
4 ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
7
8 @glob = common local_unnamed_addr global i16 0, align 2
9
10 define i64 @test_llless(i16 signext %a, i16 signext %b) {
11 ; CHECK-LABEL: test_llless:
12 ; CHECK: # BB#0: # %entry
13 ; CHECK-NEXT: subf r3, r3, r4
14 ; CHECK-NEXT: rldicl r3, r3, 1, 63
15 ; CHECK-NEXT: xori r3, r3, 1
16 ; CHECK-NEXT: blr
17 entry:
18 %cmp = icmp sle i16 %a, %b
19 %conv3 = zext i1 %cmp to i64
20 ret i64 %conv3
21 }
22
23 define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
24 ; CHECK-LABEL: test_llless_sext:
25 ; CHECK: # BB#0: # %entry
26 ; CHECK-NEXT: subf r3, r3, r4
27 ; CHECK-NEXT: rldicl r3, r3, 1, 63
28 ; CHECK-NEXT: addi r3, r3, -1
29 ; CHECK-NEXT: blr
30 entry:
31 %cmp = icmp sle i16 %a, %b
32 %conv3 = sext i1 %cmp to i64
33 ret i64 %conv3
34 }
35
36 define void @test_llless_store(i16 signext %a, i16 signext %b) {
37 ; CHECK-LABEL: test_llless_store:
38 ; CHECK: # BB#0: # %entry
39 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
40 ; CHECK-NEXT: subf r3, r3, r4
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
42 ; CHECK-NEXT: rldicl r3, r3, 1, 63
43 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: sth r3, 0(r12)
45 ; CHECK-NEXT: blr
46 entry:
47 %cmp = icmp sle i16 %a, %b
48 %conv3 = zext i1 %cmp to i16
49 store i16 %conv3, i16* @glob, align 2
50 ret void
51 }
52
53 define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
54 ; CHECK-LABEL: test_llless_sext_store:
55 ; CHECK: # BB#0: # %entry
56 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
57 ; CHECK-NEXT: subf r3, r3, r4
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
59 ; CHECK-NEXT: rldicl r3, r3, 1, 63
60 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: sth r3, 0(r12)
62 ; CHECK-NEXT: blr
63 entry:
64 %cmp = icmp sle i16 %a, %b
65 %conv3 = sext i1 %cmp to i16
66 store i16 %conv3, i16* @glob, align 2
67 ret void
68 }