llvm.org GIT mirror llvm / 2de0572
Remove redundant semicolons which are null statements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitri Gribenko 8 years ago
6 changed file(s) with 7 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
441441
442442 // Compute the number of register mask instructions in this block.
443443 std::pair &RMB = RegMaskBlocks[MBB->getNumber()];
444 RMB.second = RegMaskSlots.size() - RMB.first;;
444 RMB.second = RegMaskSlots.size() - RMB.first;
445445 }
446446
447447 // Create empty intervals for registers defined by implicit_def's (except
498498 RegMaskBits.push_back(MO->getRegMask());
499499 }
500500 // Compute the number of register mask instructions in this block.
501 RMB.second = RegMaskSlots.size() - RMB.first;;
501 RMB.second = RegMaskSlots.size() - RMB.first;
502502 }
503503 }
504504
219219 FI != FE; ++FI) {
220220
221221 // Assign a serial number to this basic block.
222 BasicBlocks[*FI] = BasicBlockNumbering.size();;
222 BasicBlocks[*FI] = BasicBlockNumbering.size();
223223 BasicBlockNumbering.push_back(*FI);
224224
225225 BlockLiveness[*FI].Begin.resize(NumSlot);
202202 StringRef Name;
203203 if (getParser().ParseIdentifier(Name))
204204 return TokError("expected identifier in directive");
205 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);;
205 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
206206
207207 if (getLexer().isNot(AsmToken::Comma))
208208 return TokError("unexpected token in directive");
409409 if (Type == macho::RIT_ARM_Half) {
410410 // The other-half value only gets populated for the movt and movw
411411 // relocation entries.
412 uint32_t Value = 0;;
412 uint32_t Value = 0;
413413 switch ((unsigned)Fixup.getKind()) {
414414 default: break;
415415 case ARM::fixup_arm_movw_lo16:
212212 case MipsSubtarget::N32: return "abiN32";
213213 case MipsSubtarget::N64: return "abi64";
214214 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
215 default: llvm_unreachable("Unknown Mips ABI");;
215 default: llvm_unreachable("Unknown Mips ABI");
216216 }
217217 }
218218
1102311023 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
1102411024 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
1102511025
11026 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
11026 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
1102711027 }
1102811028 // fall through
1102911029 case MVT::v4i32: