llvm.org GIT mirror llvm / 2dd9bf3
fix typos in comments; NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308126 91177308-0d34-0410-b5e6-96231b3b80d8 Hiroshi Inoue 3 years ago
4 changed file(s) with 5 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
365365 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
366366 /// use an offset.eq
367367 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
368 /// rewriten in @p MI.
368 /// rewritten in @p MI.
369369 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
370370 /// amount that is off the limit of the legal offset.
371371 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
7373 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
7474 CallingConv::ID CC) const {
7575 if (CC == CallingConv::GHC)
76 // This is academic becase all GHC calls are (supposed to be) tail calls
76 // This is academic because all GHC calls are (supposed to be) tail calls
7777 return CSR_AArch64_NoRegs_RegMask;
7878 if (CC == CallingConv::AnyReg)
7979 return CSR_AArch64_AllRegs_RegMask;
116116 CallingConv::ID CC) const {
117117 const ARMSubtarget &STI = MF.getSubtarget();
118118 if (CC == CallingConv::GHC)
119 // This is academic becase all GHC calls are (supposed to be) tail calls
119 // This is academic because all GHC calls are (supposed to be) tail calls
120120 return CSR_NoRegs_RegMask;
121121
122122 if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
162162 // both or otherwise does not want to enable this optimization, the function
163163 // should return NULL
164164 if (CC == CallingConv::GHC)
165 // This is academic becase all GHC calls are (supposed to be) tail calls
165 // This is academic because all GHC calls are (supposed to be) tail calls
166166 return nullptr;
167167 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
168168 : CSR_AAPCS_ThisReturn_RegMask;
4949 # CHECK-THUMB: [0xde,0xf3,0x00,0x8f]
5050
5151 # SUBS PC, LR, #0 should have the same encoding as ERET.
52 # The conditional forms can't be tested becuse the ARM assembler parser doesn't
52 # The conditional forms can't be tested because the ARM assembler parser doesn't
5353 # accept SUBS PC, LR, #, only the unconditonal form is allowed. This
5454 # is due to the way that the custom parser handles optional operands; see the
5555 # FIXME in ARM/AsmParser/ARMAsmParser.cpp.