llvm.org GIT mirror llvm / 2d90299
AMDGPU: Preserve undef flag when expanding SI_IF Fixes undefined value verifier error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355426 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 7 months ago
2 changed file(s) with 40 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
198198 MachineInstr *And =
199199 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B64), Tmp)
200200 .addReg(CopyReg)
201 //.addReg(AMDGPU::EXEC)
202 .addReg(Cond.getReg());
201 .add(Cond);
202
203203 setImpSCCDefDead(*And, true);
204204
205205 MachineInstr *Xor = nullptr;
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
12
23 # Check that assert is not triggered
3 # GCN-LABEL: name: si-lower-control-flow{{$}}
4 # GCN-CHECK: S_LOAD_DWORD_IMM
5
6 --- |
7
8 define amdgpu_kernel void @si-lower-control-flow() {
9 ret void
10 }
114
125 ...
136 ---
147 name: si-lower-control-flow
158 body: |
169 bb.0:
10 ; GCN-LABEL: name: si-lower-control-flow
11 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
12 ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0
13 ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc
14 ; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
15 ; GCN: S_ENDPGM
1716 %0:sgpr_64 = COPY $sgpr4_sgpr5
1817 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
1918 %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
2019 %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
2120 S_ENDPGM
2221 ...
22
23 ---
24 name: preserve_undef_flag_si_if_src
25 tracksRegLiveness: true
26 body: |
27 ; GCN-LABEL: name: preserve_undef_flag_si_if_src
28 ; GCN: bb.0:
29 ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
30 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
31 ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
32 ; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
33 ; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
34 ; GCN: SI_MASK_BRANCH %bb.2, implicit $exec
35 ; GCN: S_BRANCH %bb.1
36 ; GCN: bb.1:
37 ; GCN: successors: %bb.2(0x80000000)
38 ; GCN: bb.2:
39 ; GCN: S_ENDPGM
40 bb.0:
41 successors: %bb.1, %bb.2
42
43 %1:sreg_64 = SI_IF undef %0:sreg_64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
44 S_BRANCH %bb.1
45
46 bb.1:
47 successors: %bb.2
48
49 bb.2:
50 S_ENDPGM
51
52 ...