llvm.org GIT mirror llvm / 2cfd52c
Give getPointerRegClass() a "kind" value so that targets can support multiple different pointer register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
11 changed file(s) with 28 addition(s) and 26 deletion(s). Raw diff Collapse all Expand all
513513 }
514514
515515 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
516 /// values.
517 virtual const TargetRegisterClass *getPointerRegClass() const {
516 /// values. If a target supports multiple different pointer register classes,
517 /// kind specifies which one is indicated.
518 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
518519 assert(0 && "Target didn't implement getPointerRegClass!");
519520 return 0; // Must return a value in order to compile with VS 2005
520521 }
None //===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
0 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
223223 return Reserved;
224224 }
225225
226 bool
227 ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
226 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
227 unsigned Reg) const {
228228 switch (Reg) {
229229 default: break;
230230 case ARM::SP:
242242 return false;
243243 }
244244
245 const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
245 const TargetRegisterClass *
246 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
246247 return &ARM::GPRRegClass;
247248 }
248249
None //===- ARMBaseRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
0 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
7373
7474 BitVector getReservedRegs(const MachineFunction &MF) const;
7575
76 const TargetRegisterClass *getPointerRegClass() const;
76 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
7777
7878 std::pair
7979 getAllocationOrder(const TargetRegisterClass *RC,
218218
219219 /// getPointerRegClass - Return the register class to use to hold pointers.
220220 /// This is used for addressing modes.
221 const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
222 {
221 const TargetRegisterClass *
222 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
223223 return &SPU::R32CRegClass;
224224 }
225225
4242
4343 /// getPointerRegClass - Return the register class to use to hold pointers.
4444 /// This is used for addressing modes.
45 virtual const TargetRegisterClass *getPointerRegClass() const;
45 virtual const TargetRegisterClass *
46 getPointerRegClass(unsigned Kind = 0) const;
4647
4748 //! Return the array of callee-saved registers
4849 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
4545 return CalleeSavedRegs;
4646 }
4747
48 const TargetRegisterClass* const*
48 const TargetRegisterClass *const *
4949 MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
5050 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
5151 &MSP430::GR16RegClass, &MSP430::GR16RegClass,
5858 return CalleeSavedRegClasses;
5959 }
6060
61 BitVector
62 MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
61 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
6362 BitVector Reserved(getNumRegs());
6463
6564 // Mark 4 special registers as reserved.
7574 return Reserved;
7675 }
7776
78 const TargetRegisterClass* MSP430RegisterInfo::getPointerRegClass() const {
77 const TargetRegisterClass *
78 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
7979 return &MSP430::GR16RegClass;
8080 }
8181
3939 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
4040
4141 BitVector getReservedRegs(const MachineFunction &MF) const;
42 const TargetRegisterClass* getPointerRegClass() const;
42 const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;
4343
4444 bool hasFP(const MachineFunction &MF) const;
4545 bool hasReservedCallFrame(MachineFunction &MF) const;
139139
140140 /// getPointerRegClass - Return the register class to use to hold pointers.
141141 /// This is used for addressing modes.
142 const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
142 const TargetRegisterClass *
143 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
143144 if (Subtarget.isPPC64())
144145 return &PPC::G8RCRegClass;
145 else
146 return &PPC::GPRCRegClass;
146 return &PPC::GPRCRegClass;
147147 }
148148
149149 const unsigned*
3636
3737 /// getPointerRegClass - Return the register class to use to hold pointers.
3838 /// This is used for addressing modes.
39 virtual const TargetRegisterClass *getPointerRegClass() const;
39 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
4040
4141 /// Code Generation virtual methods...
4242 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
244244 return 0;
245245 }
246246
247 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
248 const X86Subtarget *Subtarget = &TM.getSubtarget();
249 if (Subtarget->is64Bit())
247 const TargetRegisterClass *X86RegisterInfo::
248 getPointerRegClass(unsigned Kind) const {
249 if (TM.getSubtarget().is64Bit())
250250 return &X86::GR64RegClass;
251 else
252 return &X86::GR32RegClass;
251 return &X86::GR32RegClass;
253252 }
254253
255254 const TargetRegisterClass *
101101
102102 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
103103 /// values.
104 const TargetRegisterClass *getPointerRegClass() const;
104 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
105105
106106 /// getCrossCopyRegClass - Returns a legal register class to copy a register
107107 /// in the specified class to or from. Returns NULL if it is possible to copy