llvm.org GIT mirror llvm / 2ceb2cf
initial code for forming an FGETSIGN node. This is disabled until legalizer support goes in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45323 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 12 years ago
1 changed file(s) with 26 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
943943 KnownZero |= ~InMask & DemandedMask;
944944 break;
945945 }
946 case ISD::FGETSIGN:
947 // All bits are zero except the low bit.
948 KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
949 break;
950 case ISD::BIT_CONVERT:
951 #if 0
952 // If this is an FP->Int bitcast and if the sign bit is the only thing that
953 // is demanded, turn this into a FGETSIGN.
954 if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) &&
955 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
956 !MVT::isVector(Op.getOperand(0).getValueType())) {
957 // Only do this xform if FGETSIGN is valid or if before legalize.
958 if (!TLO.AfterLegalize ||
959 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
960 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
961 // place. We expect the SHL to be eliminated by other optimizations.
962 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
963 Op.getOperand(0));
964 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
965 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
966 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
967 Sign, ShAmt));
968 }
969 }
970 #endif
971 break;
946972 case ISD::ADD:
947973 case ISD::SUB:
948974 case ISD::INTRINSIC_WO_CHAIN: