llvm.org GIT mirror llvm / 2ca6265
remove a bunch of unused private methods found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204560 91177308-0d34-0410-b5e6-96231b3b80d8 Nuno Lopes 6 years ago
24 changed file(s) with 2 addition(s) and 261 deletion(s). Raw diff Collapse all Expand all
104104 void RewriteUse(MachineOperand &U);
105105
106106 private:
107 void ReplaceRegWith(unsigned OldReg, unsigned NewReg);
108107 unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB);
109108
110109 void operator=(const MachineSSAUpdater&) LLVM_DELETED_FUNCTION;
853853 /// processType - Process DIType.
854854 void processType(DIType DT);
855855
856 /// processLexicalBlock - Process DILexicalBlock.
857 void processLexicalBlock(DILexicalBlock LB);
858
859856 /// processSubprogram - Process DISubprogram.
860857 void processSubprogram(DISubprogram SP);
861858
229229 U.setReg(NewVR);
230230 }
231231
232 void MachineSSAUpdater::ReplaceRegWith(unsigned OldReg, unsigned NewReg) {
233 MRI->replaceRegWith(OldReg, NewReg);
234
235 AvailableValsTy &AvailableVals = getAvailableVals(AV);
236 for (DenseMap::iterator
237 I = AvailableVals.begin(), E = AvailableVals.end(); I != E; ++I)
238 if (I->second == OldReg)
239 I->second = NewReg;
240 }
241
242232 /// SSAUpdaterTraits - Traits for the SSAUpdaterImpl
243233 /// template, specialized for MachineSSAUpdater.
244234 namespace llvm {
174174 void ReleaseSuccessors(SUnit *SU);
175175 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
176176 void ListScheduleTopDown();
177 void StartBlockForKills(MachineBasicBlock *BB);
178177
179178 void dumpSchedule() const;
180179 void emitNoop(unsigned CurCycle);
624624 RegVTs.push_back(RegisterVT);
625625 Reg += NumRegs;
626626 }
627 }
628
629 /// areValueTypesLegal - Return true if types of all the values are legal.
630 bool areValueTypesLegal(const TargetLowering &TLI) {
631 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
632 MVT RegisterVT = RegVTs[Value];
633 if (!TLI.isTypeLegal(RegisterVT))
634 return false;
635 }
636 return true;
637627 }
638628
639629 /// append - Add the specified values to this one.
10861086 }
10871087 }
10881088
1089 /// processLexicalBlock
1090 void DebugInfoFinder::processLexicalBlock(DILexicalBlock LB) {
1091 DIScope Context = LB.getContext();
1092 if (Context.isLexicalBlock())
1093 return processLexicalBlock(DILexicalBlock(Context));
1094 else if (Context.isLexicalBlockFile()) {
1095 DILexicalBlockFile DBF = DILexicalBlockFile(Context);
1096 return processLexicalBlock(DILexicalBlock(DBF.getScope()));
1097 } else
1098 return processSubprogram(DISubprogram(Context));
1099 }
1100
11011089 /// processSubprogram - Process DISubprogram.
11021090 void DebugInfoFinder::processSubprogram(DISubprogram SP) {
11031091 if (!addSubprogram(SP))
5757 DenseMap FlagMap;
5858
5959 DenseMap SymbolMap;
60
61 bool needsSet(const MCExpr *Value);
6260
6361 void EmitRegisterName(int64_t Register);
6462 void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override;
376376 /// @returns A StringRef starting at Cur which covers the longest contiguous
377377 /// sequence of ns-uri-char.
378378 StringRef scan_ns_uri_char();
379
380 /// @brief Scan ns-plain-one-line[133] starting at \a Cur.
381 StringRef scan_ns_plain_one_line();
382379
383380 /// @brief Consume a minimal well-formed code unit subsequence starting at
384381 /// \a Cur. Return false if it is not the same Unicode scalar value as
870867 break;
871868 }
872869 return StringRef(Start, Current - Start);
873 }
874
875 StringRef Scanner::scan_ns_plain_one_line() {
876 StringRef::iterator start = Current;
877 // The first character must already be verified.
878 ++Current;
879 while (true) {
880 if (Current == End) {
881 break;
882 } else if (*Current == ':') {
883 // Check if the next character is a ns-char.
884 if (Current + 1 == End)
885 break;
886 StringRef::iterator i = skip_ns_char(Current + 1);
887 if (Current + 1 != i) {
888 Current = i;
889 Column += 2; // Consume both the ':' and ns-char.
890 } else
891 break;
892 } else if (*Current == '#') {
893 // Check if the previous character was a ns-char.
894 // The & 0x80 check is to check for the trailing byte of a utf-8
895 if (*(Current - 1) & 0x80 || skip_ns_char(Current - 1) == Current) {
896 ++Current;
897 ++Column;
898 } else
899 break;
900 } else {
901 StringRef::iterator i = skip_nb_char(Current);
902 if (i == Current)
903 break;
904 Current = i;
905 ++Column;
906 }
907 }
908 return StringRef(start, Current - start);
909870 }
910871
911872 bool Scanner::consume(uint32_t Expected) {
719719 return ListRecTy::get(SubType);
720720 }
721721 }
722 }
723
724 /// ParseIDValue - Parse an ID as a value and decode what it means.
725 ///
726 /// IDValue ::= ID [def local value]
727 /// IDValue ::= ID [def template arg]
728 /// IDValue ::= ID [multiclass local value]
729 /// IDValue ::= ID [multiclass template argument]
730 /// IDValue ::= ID [def name]
731 ///
732 Init *TGParser::ParseIDValue(Record *CurRec, IDParseMode Mode) {
733 assert(Lex.getCode() == tgtok::Id && "Expected ID in ParseIDValue");
734 std::string Name = Lex.getCurStrVal();
735 SMLoc Loc = Lex.getLoc();
736 Lex.Lex();
737 return ParseIDValue(CurRec, Name, Loc);
738722 }
739723
740724 /// ParseIDValue - This is just like ParseIDValue above, but it assumes the ID
166166 SubClassReference ParseSubClassReference(Record *CurRec, bool isDefm);
167167 SubMultiClassReference ParseSubMultiClassReference(MultiClass *CurMC);
168168
169 Init *ParseIDValue(Record *CurRec, IDParseMode Mode = ParseValueMode);
170169 Init *ParseIDValue(Record *CurRec, const std::string &Name, SMLoc NameLoc,
171170 IDParseMode Mode = ParseValueMode);
172171 Init *ParseSimpleValue(Record *CurRec, RecTy *ItemType = 0,
3232 namespace {
3333
3434 class AArch64TTI final : public ImmutablePass, public TargetTransformInfo {
35 const AArch64TargetMachine *TM;
3635 const AArch64Subtarget *ST;
3736 const AArch64TargetLowering *TLI;
3837
39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
40 /// are set if the result needs to be inserted and/or extracted from vectors.
41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
42
4338 public:
44 AArch64TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
39 AArch64TTI() : ImmutablePass(ID), ST(0), TLI(0) {
4540 llvm_unreachable("This pass cannot be directly constructed");
4641 }
4742
4843 AArch64TTI(const AArch64TargetMachine *TM)
49 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
44 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
5045 TLI(TM->getTargetLowering()) {
5146 initializeAArch64TTIPass(*PassRegistry::getPassRegistry());
5247 }
206206 const { return 0; }
207207 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
208208 const { return 0; }
209 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
210 const { return 0; }
211209 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
212210 const { return 0; }
213211 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
217215 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
218216 const { return 0; }
219217 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
220 const { return 0; }
221 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
222218 const { return 0; }
223219 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
224220 const { return 0; }
237233 const { return 0; }
238234 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
239235 unsigned Op) const { return 0; }
240 unsigned getSsatBitPosValue(const MachineInstr &MI,
241 unsigned Op) const { return 0; }
242 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
243 const {return 0; }
244236 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
245237 const { return 0; }
246238
269261 return 0;
270262 }
271263
272 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
273 const { return 0;}
274264 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
275265 const { return 0;}
276266 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
280270 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
281271 const { return 0; }
282272 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
283 const { return 0; }
284 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
285273 const { return 0; }
286274 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
287275 const { return 0; }
104104
105105 // Code from FastISel.cpp.
106106 private:
107 unsigned FastEmitInst_(unsigned MachineInstOpcode,
108 const TargetRegisterClass *RC);
109107 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
110108 const TargetRegisterClass *RC,
111109 unsigned Op0, bool Op0IsKill);
122120 const TargetRegisterClass *RC,
123121 unsigned Op0, bool Op0IsKill,
124122 uint64_t Imm);
125 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
126 const TargetRegisterClass *RC,
127 unsigned Op0, bool Op0IsKill,
128 const ConstantFP *FPImm);
129123 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
130124 const TargetRegisterClass *RC,
131125 unsigned Op0, bool Op0IsKill,
134128 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
135129 const TargetRegisterClass *RC,
136130 uint64_t Imm);
137 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
138 const TargetRegisterClass *RC,
139 uint64_t Imm1, uint64_t Imm2);
140
141 unsigned FastEmitInst_extractsubreg(MVT RetVT,
142 unsigned Op0, bool Op0IsKill,
143 uint32_t Idx);
144131
145132 // Backend specific FastISel code.
146133 private:
312299 return Op;
313300 }
314301
315 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
316 const TargetRegisterClass* RC) {
317 unsigned ResultReg = createResultReg(RC);
318 const MCInstrDesc &II = TII.get(MachineInstOpcode);
319
320 AddOptionalDefs(
321 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg));
322 return ResultReg;
323 }
324
325302 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
326303 const TargetRegisterClass *RC,
327304 unsigned Op0, bool Op0IsKill) {
423400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
424401 .addReg(Op0, Op0IsKill * RegState::Kill)
425402 .addImm(Imm));
426 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
427 TII.get(TargetOpcode::COPY), ResultReg)
428 .addReg(II.ImplicitDefs[0]));
429 }
430 return ResultReg;
431 }
432
433 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
434 const TargetRegisterClass *RC,
435 unsigned Op0, bool Op0IsKill,
436 const ConstantFP *FPImm) {
437 unsigned ResultReg = createResultReg(RC);
438 const MCInstrDesc &II = TII.get(MachineInstOpcode);
439
440 // Make sure the input operand is sufficiently constrained to be legal
441 // for this instruction.
442 Op0 = constrainOperandRegClass(II, Op0, 1);
443 if (II.getNumDefs() >= 1) {
444 AddOptionalDefs(
445 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
446 .addReg(Op0, Op0IsKill * RegState::Kill)
447 .addFPImm(FPImm));
448 } else {
449 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
450 .addReg(Op0, Op0IsKill * RegState::Kill)
451 .addFPImm(FPImm));
452403 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
453404 TII.get(TargetOpcode::COPY), ResultReg)
454405 .addReg(II.ImplicitDefs[0]));
502453 TII.get(TargetOpcode::COPY), ResultReg)
503454 .addReg(II.ImplicitDefs[0]));
504455 }
505 return ResultReg;
506 }
507
508 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
509 const TargetRegisterClass *RC,
510 uint64_t Imm1, uint64_t Imm2) {
511 unsigned ResultReg = createResultReg(RC);
512 const MCInstrDesc &II = TII.get(MachineInstOpcode);
513
514 if (II.getNumDefs() >= 1) {
515 AddOptionalDefs(
516 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
517 .addImm(Imm1)
518 .addImm(Imm2));
519 } else {
520 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
521 .addImm(Imm1).addImm(Imm2));
522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523 TII.get(TargetOpcode::COPY),
524 ResultReg)
525 .addReg(II.ImplicitDefs[0]));
526 }
527 return ResultReg;
528 }
529
530 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
531 unsigned Op0, bool Op0IsKill,
532 uint32_t Idx) {
533 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
534 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
535 "Cannot yet extract from physregs");
536
537 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
538 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
539 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
540456 return ResultReg;
541457 }
542458
116116 unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
117117 unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
118118
119 void emitGlobalAddressUnaligned(const GlobalValue *GV, unsigned Reloc,
120 int Offset) const;
121
122119 /// Expand pseudo instructions with accumulator register operands.
123120 void expandACCInstr(MachineBasicBlock::instr_iterator MI,
124121 MachineBasicBlock &MBB, unsigned Opc) const;
279276 MayNeedFarStub));
280277 }
281278
282 void MipsCodeEmitter::emitGlobalAddressUnaligned(const GlobalValue *GV,
283 unsigned Reloc, int Offset) const {
284 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
285 const_cast(GV), 0, false));
286 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset() + Offset,
287 Reloc, const_cast(GV), 0, false));
288 }
289
290279 void MipsCodeEmitter::
291280 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
292281 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
383383 unsigned getOffsetOf(MachineInstr *MI) const;
384384 unsigned getUserOffset(CPUser&) const;
385385 void dumpBBs();
386 void verify();
387386
388387 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
389388 unsigned Disp, bool NegativeOK);
390389 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
391390 const CPUser &U);
392
393 bool isLongFormOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
394 const CPUser &U);
395391
396392 void computeBlockSize(MachineBasicBlock *MBB);
397393 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
425421
426422 char MipsConstantIslands::ID = 0;
427423 } // end of anonymous namespace
428
429
430 bool MipsConstantIslands::isLongFormOffsetInRange
431 (unsigned UserOffset, unsigned TrialOffset,
432 const CPUser &U) {
433 return isOffsetInRange(UserOffset, TrialOffset,
434 U.getLongFormMaxDisp(), U.NegOk);
435 }
436424
437425 bool MipsConstantIslands::isOffsetInRange
438426 (unsigned UserOffset, unsigned TrialOffset,
24392439 }
24402440 return true;
24412441 }
2442
2443 // Return true if N is a undef or a constant.
2444 // If N was undef, return a (i8imm 0) in Retval
2445 // If N was imm, convert it to i8imm and return in Retval
2446 // Note: The convert to i8imm is required, otherwise the
2447 // pattern matcher inserts a bunch of IMOVi8rr to convert
2448 // the imm to i8imm, and this causes instruction selection
2449 // to fail.
2450 bool NVPTXDAGToDAGISel::UndefOrImm(SDValue Op, SDValue N, SDValue &Retval) {
2451 if (!(N.getOpcode() == ISD::UNDEF) && !(N.getOpcode() == ISD::Constant))
2452 return false;
2453
2454 if (N.getOpcode() == ISD::UNDEF)
2455 Retval = CurDAG->getTargetConstant(0, MVT::i8);
2456 else {
2457 ConstantSDNode *cn = cast(N.getNode());
2458 unsigned retval = cn->getZExtValue();
2459 Retval = CurDAG->getTargetConstant(retval, MVT::i8);
2460 }
2461 return true;
2462 }
9090
9191 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
9292
93 bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
94
9593 };
9694 }
126126 bool SelectStore(const Instruction *I);
127127 bool SelectBranch(const Instruction *I);
128128 bool SelectIndirectBr(const Instruction *I);
129 bool SelectCmp(const Instruction *I);
130129 bool SelectFPExt(const Instruction *I);
131130 bool SelectFPTrunc(const Instruction *I);
132131 bool SelectIToFP(const Instruction *I, bool IsSigned);
325325 private:
326326 void initializeCallbacks(Module &M);
327327
328 bool ShouldInstrumentGlobal(GlobalVariable *G);
329328 bool LooksLikeCodeInBug11395(Instruction *I);
330 void FindDynamicInitializers(Module &M);
331329 bool GlobalIsLinkerInitialized(GlobalVariable *G);
332330 bool InjectCoverage(Function &F, const ArrayRef AllBlocks);
333331 void InjectCoverageAtBlock(Function &F, BasicBlock &BB);
6161
6262 BasicBlock *getTrapBB();
6363 void emitBranchToTrap(Value *Cmp = 0);
64 bool computeAllocSize(Value *Ptr, APInt &Offset, Value* &OffsetValue,
65 APInt &Size, Value* &SizeValue);
6664 bool instrument(Value *Ptr, Value *Val);
6765 };
6866 }
500500 Instruction *OrigIns;
501501 ShadowOriginAndInsertPoint(Value *S, Value *O, Instruction *I)
502502 : Shadow(S), Origin(O), OrigIns(I) { }
503 ShadowOriginAndInsertPoint() : Shadow(0), Origin(0), OrigIns(0) { }
504503 };
505504 SmallVector InstrumentationList;
506505 SmallVector StoreList;
7878 return dyn_cast(BB->getTerminator());
7979 }
8080
81 /// Return the condition of the branch terminating the given basic block.
82 static Value *getBrCondtion(BasicBlock *);
83
8481 /// Derive the precondition block (i.e the block that guards the loop
8582 /// preheader) from the given preheader.
8683 static BasicBlock *getPrecondBb(BasicBlock *PreHead);
289286 return Br->isUnconditional() && BB->size() == 1;
290287 }
291288 return false;
292 }
293
294 Value *LIRUtil::getBrCondtion(BasicBlock *BB) {
295 BranchInst *Br = getBranch(BB);
296 return Br ? Br->getCondition() : 0;
297289 }
298290
299291 BasicBlock *LIRUtil::getPrecondBb(BasicBlock *PreHead) {
490490 }
491491 void visitCallSite (CallSite CS);
492492 void visitResumeInst (TerminatorInst &I) { /*returns void*/ }
493 void visitUnwindInst (TerminatorInst &I) { /*returns void*/ }
494493 void visitUnreachableInst(TerminatorInst &I) { /*returns void*/ }
495494 void visitFenceInst (FenceInst &I) { /*returns void*/ }
496495 void visitAtomicCmpXchgInst (AtomicCmpXchgInst &I) { markOverdefined(&I); }
4040
4141 void run(raw_ostream &o);
4242 private:
43 void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace);
44 void emitGetValueBit(raw_ostream &o, const std::string &Namespace);
4543 int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
4644 std::string getInstructionCase(Record *R, CodeGenTarget &Target);
4745 void AddCodeToMergeInOperand(Record *R, BitsInit *BI,