llvm.org GIT mirror llvm / 2c383d8
move SETB pseudos into the same place in InstrCompiler.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
2 changed file(s) with 13 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
627627 X86_COND_NO, EFLAGS))]>, TB;
628628 } // Constraints = "$src1 = $dst"
629629
630
631
632630 let Uses = [EFLAGS] in {
633 // Use sbb to materialize carry bit.
634 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
635 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
636 // However, Pat<> can't replicate the destination reg into the inputs of the
637 // result.
638 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
639 // X86CodeEmitter.
640 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
641 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
642 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
643 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
644 OpSize;
645 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
646 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
647 } // isCodeGenOnly
648631
649632 def SETEr : I<0x94, MRM0r,
650633 (outs GR8 :$dst), (ins),
157157 "", [(set GR64:$dst, i64immZExt32:$src)]>;
158158
159159
160 // Use sbb to materialize carry flag into a GPR.
161 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
160 // Use sbb to materialize carry bit.
161 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
162 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
162163 // However, Pat<> can't replicate the destination reg into the inputs of the
163164 // result.
164 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
165 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
165166 // X86CodeEmitter.
166 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
167 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
168 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
169 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
170 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
171 OpSize;
172 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
173 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
167174 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
168175 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
176 } // isCodeGenOnly
177
169178
170179 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
171180 (SETB_C64r)>;